DATE 2005 - OpenAccess Migration within Philips Semiconductor

OpenAccess MigrationOpenAccess Migrationwithin Philips Semiconductorswithin Philips Semiconductors

Timothy J. EhrlerTimothy J. EhrlerSenior Principal EngineerSenior Principal Engineer

Design Technology GroupDesign Technology GroupPhilips SemiconductorsPhilips [email protected]@philips.com

DATE 2005DATE 2005

2OpenAccess @ DATE 2005, Tim Ehrler, Mar 2005

• Direct OpenAccess Relationships– Member of OpenAccess Coalition– Member of the OpenAccess Change Team– Vice-chair of the Golden Gate Bridge Working Group

• Between OpenAccess and Synopsys MilkyWay– Chairperson of the Timing/Constraints Working Group– Conference presentations, panel discussions

• Philips Activities– Training– Information distribution & education– Source/binaries downloads– Application development– Design environment migration– Timing Constraint Development & Implementation

Participation & Involvement

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Contents:Contents:Delay CalculationDelay CalculationStatic Timing AnalysisStatic Timing AnalysisGateGate--level Simulationlevel SimulationPower EstimationPower EstimationScreenerScreenerVerification of specificationVerification of specification

Contents:Contents:RTL SimulationRTL SimulationArchitectural AnalysisArchitectural AnalysisBus interfacesBus interfacesSoftware code developmentSoftware code developmentRSP platformRSP platformFeasibility: Performance, Area, Feasibility: Performance, Area, Power, Clocking, Test managementPower, Clocking, Test management

Contents:Contents:Block level synthesisBlock level synthesisCreate top level design (CPU, DSP, Create top level design (CPU, DSP, analog, memory, HDLi templates, analog, memory, HDLi templates, I/O, schematics)I/O, schematics)DFT (scan insertion, MBIST, DFT (scan insertion, MBIST, JTAG, padring)JTAG, padring)FloorplanningFloorplanning

SPEC

IP

Library Models

Behavioral RTLDesign

Verilog or VHDL

Verilog or VHDLRTL description

Functional DesignVerilog or VHDL

LayoutLayout

Verilog or VHDLStructural Netlist

Logic & TimingVerification

Verilog or VHDL

Library Models

Test ProgramTest ProgramGenerationGeneration

SDB

Ref Libs

LDB

Ref Libs

Ref Libs

Contents:Contents:Hierarchy planningHierarchy planningAutomatic flatten for P&RAutomatic flatten for P&Rprepre--route P/G, clock netsroute P/G, clock netsArea estimationArea estimation

Contents:Contents:Cell and Block P&RCell and Block P&RTiming driven extensionsTiming driven extensions

Partitioning &Floorplanning

Layout:Cell & Block

LDB

Layout:Chip Assembly

Design Finishing

LDB GDS-IILib Rules,

Timing,Package

Contents:Contents:Insert core & pad fillersInsert core & pad fillersSymbolic verificationSymbolic verificationBond diagramBond diagram

Verification

Contents:Contents: DRC, LVS, DRC, LVS, Plots, Extraction, Circuit Plots, Extraction, Circuit Simulation, BackSimulation, Back--annotation annotation & Timing Analysis& Timing Analysis

To Factory FinishTo Factory Finishand Mask Makingand Mask Making

• Design issues now requires more effective solutions– Feature size, complexity, reuse, etc.

The State of Design Processing

To MaskShop

FromSSDE

PhysicalPartitionTiming

Constraints

PhysicalPartitionNetlist

PhysicalPartitionPhysical

Constraints

PhysicalPartitionPhysical

model

PhysicalPartitionTimingmodel

PhysicalPartitionPowermodel

Block Implementation

IP cores

PhyscialExploration

SoCEncounter

PartitioningSoCEncounte

rDMS

Logic SynthesisDesign

CompilerRTL

Prot

otyp

ing

PhysicalExploration Partitioning Logic

SynthesisDFT

Architecture

SVCLDV

Diesel

DebugDebussy

ECFormality

Des

ign-

InVe

rific

atio

n

DebugSimulationVerificationCoverage

EquivalenceChecking

ECFormality

PowerAnalysis

ExternalNetlists(Firm IP)

IP cores

PlacementBased

Optimisation

DFT PostPlacement

OptimisationPhys

ical

Synt

hesi

s

Clock Tree

Signal RoutingAntennas Decaps/

Fillers

Post RouteFix

EditingCrosstalk

Rou

ting

&Fi

nal

Opt

imis

atio

n

Verif

icat

ion

Sign

off From

AMSDE/RFDE

ToAMSDE/

RFDE

AMSDERFDE

IP Design

Chi

p Ph

ysic

alVe

rific

atio

n

PackageAssemblyFinishing

Design ChipFinishing

DesignPhysical

Verification

I/O &Hierarchical

Planning

Power GridDesign /Analysis

HierarchicalSTA

Chip PhysicalArchitecture

ChipAssembly

FloorplanImplementation

IP Screening

NetlistScreening

ConstraintsScreening

Screeners

SynthesisConstraints

ESD

Timing &CrosstalkAnalysis

PowerDistribution

AnalysisParasitic

Extraction

– Individual EDA vendors focus on particular design spaces (synthesis, timing, routing, etc.)

– No vendor can provide the “optimal” design solution

– Specific design issues require “best-in-class” tools to address

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Impact on Design Data

• Design data explosion becomes significant bottleneck

– Many tools require proprietary data formats

– Suites often import same data between different tools

– Translators must often be built to transfer data between tools

– New tool evaluation / deployment implies major CAD design environment / flow integration efforts

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• Design data export / translate / import takes time …


Addressing the Problem• Standardized design data model / structure

StandardAPI

ReferenceImplementation

Synthesis

Static Timing

Design for Test

Floorplanning

Place & Route

PrototypeApplication

StandardData

Model

EXTAPI

• Standard, extensible interface to design data– Provides consistent access by any compliant EDA tool– Enables prototypical application / database development

• Corresponding reference implementation– Provides compliant database, eliminating internal developments– Enables quick acceptance & application development

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Finding an Available Solution

• Community effort to provide true IC design tool interoperability, not just design data storage / exchange

– Employs open, standard application programming interface (API)• Built on Genesis 2 contributed by Cadence Design Systems• Includes extensible prototyping capabilities• Enables custom design data management

– Provides reference database implementation supporting the API• Supports multiple platforms & operating systems• Includes additional utilities & translators (import/export)

– Supported by neutral Coalition of industry leaders under SiliconIntegration Initiative (SI2) bylaws

• Directed by 12-member Change Team

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Where OpenAccess is Applicable

RadioFrequency

DesignEnvironment

Analog /Mixed-Signal

DesignEnvironment

System-on-ChipDesign

Environment

System &SoftwareDesign

Environment

IP Integration

IP/IC Creation

DesignData

Processes

DesignData

Exchange

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Improving Design Data Processing• Reduce / eliminate design data exchange files

– Reduce storage requirements– Reduce import/export time– Reduce design data content and [mis-]interpretation issues

• Improve task interoperability– Enable more efficient tool usage– Simplify task methodology development– Allow refinement / optimization of current methodologies

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Enhancing Design Data Exchange• Robust interface for IP, blocks

– Provide standard, consistent database access

– Allow more appropriate and applicable tool usage

– IP generated or created independently of tool / environment

• Significantly reduce reuse requirements

– Reduce design data file requirements

– Consistent design data and information requirements for IP and blocks

• IP & block usage independent of source environment

– IP in any design environment available for use within any other

Flow A Flow B

Flow A Flow B

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Evolving Data-File Based Flows …

TaskFlowTaskFlow

TaskFlowTaskFlow

TaskFlowTaskFlow

TaskFlowTaskFlow

TaskFlowTaskFlow

datadata

datadata

datadata

datadata

datadata

datadata

DesignEnvironment

input

internal

output

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… to OpenAccess Environments

TaskFlowTaskFlow

TaskFlowTaskFlow

TaskFlowTaskFlow

TaskFlowTaskFlow

TaskFlowTaskFlow

Ope

nAcc

ess

data

base common

DesignEnvironment

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Migration Roadmap• OpenAccess 2.2 supporting tool availability at issue

– Only OA 2.2 addresses release compatibility, supports needs– Production EDA tool releases occur 2nd quarter at earliest– Aligned design environments releases occur end of 3rd quarter– Too late for full evaluation and development of task flows

• Develop limited OpenAccess task flows in 2005– In parallel with current aligned design environment releases– Implement where designer can gain most productivity

• DFII based flows (AMSDE, RFDE, IP blocks) replacing CDBA• Interfaces between SoCDE and AMSDE & RFDE (e.g., ICC)

• Full deployment with 2006 aligned releases– Embracing OA 2.2.x with richer tool support (timing constraints, etc.)– Include internal & external DFT capabilities– Better support Philips reuse methodologies– Address and resolve library issues and concerns

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Timing Constraints Development• SDC-equivalent timing constraint capability requested

– Requirements defined by workgroup from Oct. 2003 through Mar. 2004• Persistent data representation only, not command language equivalence

– Cadence lacked resources, so Philips volunteered development

• Development done from Aug. 2004 through Feb. 2005– Based on OA 2.2 beta b005, later on release 2.2.0– Constraints classified into 5 categories for implementation– Compatibility and extensibility primary concerns

• Required non-trivial re-architecture and data structure changes– Implementation turned over to Cadence for integration Mar 1. 2005

• Affected over 50K lines in over 130 new or modified source files• Full regression test cases• ‘doxygen’ API specifications

• Will present experience at 6th OpenAccess Conference in April

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Documents

DATE 2005 - OpenAccess Migration within Philips Semiconductor