Data Converters

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Many physically-based values are best represented with real-numbers as opposed to a discrete number of values. However, in computers we are practically limited in the number of distinct values we can represent.

So, how can we represent real numbers?-> We create a mapping of codes to physical values such as the following.

Representing Real Numbers Limited # of Bits

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Can only pick 8 real-valued points called quantization levels

Choosing Quantization Levels

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Quantization:"rounding" of real number to one of a limited set real-numbered quantization levels

Quantization error is the difference between a desired real number and its quantized value

Coding: mapping of set of real numbers toa digital code

Digital Code to Real Value Mapping

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Lets represent the voltage range [0 V, 10 V) with a three bit code.

2 1 0 Value

0 0 0 0Vref/8

0 0 1 1Vref/8

0 1 0 2Vref/8

0 1 1 3Vref/8

1 0 0 4Vref/8

1 0 1 5Vref/8

1 1 0 6Vref/8

1 1 1 7Vref/8

Common binary coding uses POWERS OF 2 for bit weightings:

The A/D coding just described uses real-valued weightings instead, increased by powers of two:

The step size between quantization levels corresponds to the real-value weighting of the LSB:

Comparison to binary number representation

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A common circuit provides binary-weighted contributions:

relies on digital outputs matching voltages•

requires many different precise, accurate

resistances

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A Digital to Analog Converters (DAC)

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Only 2 precise resistor values are required, value doesn't matter as much matching among them

•

The error of each resistor spread across codes more than previous

•

Monolithic implementations available (constrains errors to guarantee that increasing code always corresponds to a higher value...important for some feedback and control applications)

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R-2-R Ladder DAC

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Output is current instead of voltage•Common for high-speed converters•Voltage can be set using a resistor or by a user-selected external high-speed active current-to-voltage converter

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Current-Output DACs

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A cheap DAC can be built using digital driver and a low-pass filter. The duty cycle of the digital signal sets the analog output level.

PWM-based DAC

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An analog-to-digital conversion (abbreviated ADC, A/D or A to D) is a process that converts a continuous quantity (continuous in time and possible values ) to a discrete-time, discrete value (digital) representation

Mapping to discrete values•

Updating/defining value at discrete times*•

ADC is:

*discrete value continuous-time converters are possible

ADC

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Mapping Continuous Voltage to

Digital Codes

Discrete Time Measurements

...together make a

discrete-valued signal

with updates at

discrete times

Analog Waveform to Digital Waveform

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Single or parallel stages•Single conversion step or successive approximation steps•One or multiple clock cycles•

ADCs may use

The various architectures trade off the performance metrics discussed, as well as cost, power, size, etc...

ADC

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Flash: uses parallel stages for speed, precision/accuracy is

sacrificed by needing many so many parts matched

Pipelined: uses multiple stages to resolve signal, good

throughput but larger latency

Successive Approximation and Algorithmic: uses multiple

iterations to resolve signal, slow

Algorithmic: uses multiple iterations to resolve signal, slow

Sigma-Delta: performs fast conversion on signal changes but

effectively slow sensing/detections of total signal/large

changes

Trends

Flash•

Pipelined•

Successive-Approximation•

Sigma-Delta•

Common ADC Architectures

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Sample rate/ throughput: number of measurements of amplitude per second. Higher sampling rates are better but increase data-rates, power, cost, etc...

How fast is fast enough? The commonly-cited value is 2-times the frequency of the highest frequency component into the ADC, (this allows perfect reconstruction of the continuous waveform). Often an analog low-pass filter is used before the ADC to limit the required sampling frequency.Sometimes a technique call oversampling is used: it involves sample faster than needed and digitally averaging results to remove some noise. For AVR, see application note http://www.atmel.com/images/doc8003.pdf

Latency: time between sampling a voltage and getting the corresponding value

Performance Metrics

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Bit depth :determines number of discrete values that can be represented, sets bound on combination of precision and rangeof each measurement of amplitude.

If the offset of the measured value from the true value maters, you care about accuracy.

•

If you care how small of a voltage step you can resolve you care about precision.

•

Often these ideas are combined under the umbrella term "accuracy"

•

(Look up INL/DNL: integral and differential error to find formal metrics used for converters.)

Precision vs Accuracy:

Monolithic: means that digital codes strictly increase when analog voltage increases

Performance Metrics

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Differential input is useful

when the potential to be

measured is not referenced to

ground.

It is also useful for rejecting

noise on ground or

differences between grounds

Pseudo-differential is like

differential but Vin- pin must

be close in terms of voltage

to ground. (~.7) and is used

only for noise rejection.<- Noise between grounds ->

Differential and Pseudo-differential Input

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Hold

A Sample and Hold (S/H) is required to hold an analog signal while a (initial) conversion can completeThe most basic S/H is a switch and a capacitor.

Sample-and-Hold

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Some ADCs include a internal "Track and Hold" buffer to drive the sample capacitance

For fast operation, a driver must be able to set the capacitor quickly and accurately. For fast settling a small RC is required, i.e. a low output resistance is required by the driver. For this purpose, the ADC datasheet may specify a maximum output impedance for the driver along with a minimum current drive ability.

Sample and Hold - Driving Sampling Capacitor

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A Sample-and-Hold is required to Hold the signal while a conversion can start/complete

The switch is implemented with FET that unfortunately leaks current and causes droop during hold.So, hold times can not be indefinite and thus ADC's often require a minimum clock rate to ensure processing happens quickly enough

Sample and Hold - Droop

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Common Analog to Digital (ADC) Architectures

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N-bit Flash ADC

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An analog approximation "guess" is made by increasing a digital code to a DAC. Once the analog approximation crosses the input, waveform is reached, the digital code is saved

Digital Ramp ADC

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An analog approximation "guess" is made by stepping the previous digital code up or down each cycle. This is fast and works well if the analog input waveform doesn't move too quickly.

Tracking ADC

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An analog approximation is made in the analog domain by integrating a constant current onto a capacitor. A digital timer determines the analog value by the time needed for the approximation to reach the analog input.

Integrating Reference Ramp ADC

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Measures time to discharge a capacitor based on input signal•

Very precise, but slow•

Value based on one R and one C (Assuming amplifier gain is

large), but can be calibrated

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Dual-Slope ADC

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breaks conversion up into several

stages

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Has inherent latency•

Pipelined-ADC

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rather than converting successively smaller signals

-multiplies residual error rather than

Algorithmic ADC

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slower than flash, takes several iterations •

accuracy determined by DAC & Comparator•

Successive-Approximation ADC

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Idea: sample signal and sense only changes and do it so fast

that only small changes need to be digitized using low-

resolution components

http://www.numerix-dsp.com/appsnotes/APR8-sigma-delta.pdf

Sigma-Delta ADC

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http://www.analog.com/static/imported-files/application_notes/292524291525717245054923680458171AN283.pdf

basically swap digital and

analog parts

Sigma-Delta DAC

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10-bit Resolution

• 0 - VCC ADC Input Voltage

Range

• ADC clock can be 50KHz to

1MHz

• Full resolution (10 bits)

frequency range 50KHz-

200KHz

• Up to 15 ksps at to get

Maximum Resolution (200 kHz

ADC clock)

NOTE the 200 kHz ADC

clock and compared to the 15

ksps spec.

http://www.atmel.com/Images/doc8018.pdf

ADC of Atmega169P

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Each conversion takes 13 clocks,

• So, ADC clock = 200KHz----> 200KHZ/13HZ ~15K sample

(15ksps)

More Info: Characterization and Calibration of the ADC on an

AVR

http://www.atmel.com/dyn/resources/prod_documents/doc255

9.pdf

Conversion Timing

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