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Grant Agreement number: 248972

Project acronym: NaNoC

Project title: “Nanoscale Silicon-Aware Network-on-Chip Design Platform”

Seventh Framework Programme

Funding Scheme: Collaborative project

Theme ICT-2009.3.2 Design of semiconductor components and

electronic based miniaturised systems

Start date of project: 01/01/2010 Duration: 36 months

D7.1 Dissemination Report

Due date of deliverable: M36

Actual submission date: M36

Organization name of lead beneficiary for this deliverable: LTQ

Work package contributing to the Deliverable: 7

Dissemination Level

PU Public PU

PP Restricted to other programme participants (including the

Commission Services)

RE Restricted to a group specified by the consortium (including the

Commission Services)

CO Confidential, only for members of the consortium (including the

Commission Services)

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APPROVED BY:

Partners Date

All partners 16th January 2013

1. INDEX  2.   ABSTRACT ...............................................................................................................3  3.   GLOSSARY ...............................................................................................................3  4.   DISSEMINATION.....................................................................................................4  1.1.   Introduction .............................................................................................................4  1.2.   Task 7.1: Publications .............................................................................................4  1.1.1.   Peer-reviewed conference papers .........................................................................4  1.1.2.   Peer-reviewed journal papers ...............................................................................9  1.1.3.   Invited Talk ........................................................................................................10  1.1.4.   European Nanoelectronics Forum 2012 .............................................................10  1.1.5.   Book Chapters ....................................................................................................11  1.1.6.   Conference Posters .............................................................................................11  1.1.7.   Conference Tutorials ..........................................................................................11  1.1.8.   Interviews ...........................................................................................................11  1.1.9.   Press Releases.....................................................................................................12  1.1.10.   Video ................................................................................................................12  1.1.11.   Internal Dissemination......................................................................................12  1.1.12.   Patents...............................................................................................................12  1.3.   Task 7.2: Summer schools.....................................................................................13  1.4.   Task 7.3: Web site .................................................................................................13  5.   CONCLUSIONS ......................................................................................................14  

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2. ABSTRACT  

In NaNoC the dissemination of project results was considered as a continuous task

over the project lifetime. Hence after the three years of project run time, many such

results have been finalized, leading to 36 published papers in peer-reviewed

conferences, and 12 published in peer-reviewed journals – with 2 of them awarded as

best papers of the respective conference event.

The NaNoC summer school was successfully carried out with 70 students coming

from all over the world to Munich. 4 Patents have been filed.

As a technical highlight a new EDA file exchange format, the CEF format, was

specified and disclosed.

Among the many other dissemination activities are press releases, public videos,

interviews etc. All these are accessible via the NaNoC website (www.nanoc-project.eu),

which is the central place to go for all project-related information.

3. GLOSSARY    

EDA.............. Electronic Design Automation

NoC............... Network-on-chip

SoC ............... System-on-chip

TEKLA ......... Teklatech A/S, NaNoC partner

INOCS .......... iNoCs SaRL, NaNoC partner

LTQ .............. Lantiq GmbH, NaNoC partner

IMC............... Intel Mobile Communications GmbH, NaNoC partner

UNIFE .......... University of Ferrara, NaNoC partner

UPV .............. Polytechnical University of Valencia, NaNoC project leader

SIMULA....... Simula Research Lab, NaNoC partner

CEF............... Common Exchange Format, specified by NaNoC

IC-NAO ........ Integrated Circuit Noise Analysis and Optimization

HT................. Hold Time Robustness

DATE ........... Design Automation & Test in Europe, yearly conference

IEEE ............. Institute of Electrical and Electronics Engineers, US standardization body

IET................ Institution of Engineering and Technology

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4. DISSEMINATION  

1.1. Introduction  

The NaNoC project used all possible methods to disseminate the results of their

work. They are grouped in this document according to the three tasks specified for this

work package: publications, summer schools and web site.

The publications section is structured according to all detailed activities: conference/

journal papers, press releases, video etc. We highlight the joint publications and indicate

the partners involved. 16 joint publications were achieved, reflecting the high

interactions between partners.

1.2. Task  7.1:  Publications    

1.1.1. Peer-­reviewed  conference  papers  

1. Hernández, C.; Silla, F. & Duato, J. “A methodology for the characterization of

process variation in NoC links”, Design, Automation & Test in Europe

Conference (DATE), 2010, 685-690

2. Hernández, C.; Roca, A.; Silla, F.; Flich, J. & Duato, J. “Improving the

Performance of GALS-Based NoCs in the Presence of Process Variation”

Fourth ACM/IEEE International Symposium on Networks-on-Chip (NOCS),

2010, 35-42

3. Rodrigo, S.; Flich, J.; Roca, A.; Medardoni, S.; Bertozzi, D.; Camacho, J.; Silla,

F. & Duato, J. “Addressing Manufacturing Challenges with Cost-Efficient Fault

Tolerant Routing”. Fourth ACM/IEEE International Symposium on Networks-

on-Chip (NOCS), 2010, 25-32, joint publication between UPV and UNIFE.

4. Gilabert, F.; Gómez, M. E.; Medardoni, S. & Bertozzi, D. “Improved Utilization

of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-

processor Systems-on-Chip” Fourth ACM/IEEE International Symposium on

Networks-on-Chip (NOCS), 2010, 165-172, joint publication between UPV and

UNIFE.

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5. Strano, A.; Bertozzi, D.; C. Hernández & Silla, F. “Process Variation and Layout

Mismatch Tolerant Design of Source Synchronous Links for GALS NoC”, 12th

IEEE International Symposium on System-on-Chip (SoC 2010), 2010, 43-48,

joint publication between UPV and UNIFE.

6. Roca; J. Flich; F. Silla; J. Duato: “VCTlite: Towards an Efficient

Implementation of Virtual Cut-Through Switching in On-Chip Networks” 2010

International Conference on High Performance Computing, Goa, India,

December 2010.

7. Antoni Roca, José Flich, Federico Silla, José Duato “A Latency-Efficient Router

Architecture for CMP Systems” in 2010 13th Euromicro Conference on Digital

System Design: Architectures, Methods and Tools (2010)

8. Ludovici, D.; Gilabert, F.; Gomez, M. E.; Gaydadjiev, G. & Bertozzi, D.

“Contrasting Topologies for Regular Interconnection Networks under the

Constraints of Nanoscale Silicon Technology”. 3rd International Workshop on

Network on Chip Architectures (NoCArc'10), 2010, joint publication between

UPV and UNIFE.

9. M. Ferraresi, G. Gobbo, D. Ludovici, and D. Bertozzi, “Bringing Network-on-

Chip Links to 45nm.,” in International Symposium on System on Chip (SoC),

2011, pp. 122-127.

10. Ghiribaldi, D. Ludovici, M. Favalli, and D. Bertozzi, “System-Level

Infrastructure for Boot-time Testing and Configuration of Networks-on-Chip

with Programmable Routing Logic.,” in 19th IFIP/IEEE International

Conference on Very Large Scale Integration (VLSI-SoC), 2011, pp. 308-313.

11. Hernández, F. Silla, and J. Duato, “Energy and Performance Efficient Thread

Mapping in NoC-Based CMPs under Process Variations,” in Parallel Processing

(ICPP), 2011 International Conference on, 2011, pp. 41-50.

12. Roca, C. Hernández, J. Flich, F. Silla, and J. Duato, “A Distributed Switch

Architecture for On-Chip Networks,” in ICPP, 2011, pp. 21-30.

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13. F. O. Sem-Jacobsen, S. Rodrigo Mocholi, and T. Skeie, “iFDOR: dynamic

rerouting on-chip,” in Proceedings of the Fifth International Workshop on

Interconnection Network Architecture: On-Chip, Multi-Chip, 2011, pp. 11-14.

14. Roca, J. Flich, F. Silla, and J. Duato, “A Full Custom Modular Switch for CMP

systems,” in 7th HiPEAC Summer School on Advanced Computer Architecture

and Compilation for Embedded Systems (ACACES), 2011.

15. Strano, D. Bertozzi, A. Grasset, and S. Yehia, “Exploiting structural redundancy

of SIMD accelerators for their built-in self-testing/diagnosis and

reconfiguration” in ASAP 11, 2011, pp. 141-148.

16. Strano, C. Gómez, D. Ludovici, M. Favalli, M. E. Gómez, and D. Bertozzi,

“Exploiting Network-on-Chip structural redundancy for a cooperative and

scalable built-in self-test architecture.,” in Design, Automation & Test in Europe

Conference & Exhibition (DATE), 2011, pp. 1-6, joint publication between

UPV and UNIFE.

17. H. F. Tatenguem, D. Ludovici, A. Strano, H. Reinig, and D. Bertozzi,

“Contrasting Multi-Synchronous MPSoC Design Styles for Fine-Grained Clock

Domain Partitioning: the Full-HD Video Playback Case Study.,” in 4th

International Workshop on Network on Chip Architectures (NoCArc’11), 2011,

joint publication between UNIFE and IMC.

18. Francisco Triviño, Francisco J. Alfaro, José L. Sanchez, and José Flich, “A Fast

Centralized Computation Routing Algorithm for Self-Configuring NoC

Systems,” in the 18th International Conference on High Performance Computing

(HiPC), 2011, pp. 1-10.

19. Francisco Triviño, Francisco J. Andujar, Francisco J. Alfaro, José L. Sanchez,

and Alberto Ros, “Self-Related Traces: An Alternative to Full-System

Simulation for NoCs,” in High Performance Computing and Simulation (HPCS),

2011 International Conference on, 2011, pp. 819-824.

20. M. Lodde and J. Flich "Memory Hierarchy and Network Co-design through

Trace-Driven Simulation". ACACES 2011, Seventh International Summer

School on Advanced Computer. Fiuggi (Italy), 2011

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21. S. Terenzi, A. Strano, and D. Bertozzi, “Optimizing Built-In Pseudo-Random

Self-Testing for Network-on-Chip Switches.,” in Interconnection Network

Architecture: On-Chip, Multi-Chip (INA-OCMC), 2012.

22. F. Triviño, J. L. Sánchez, F. J. Alfaro, and J. Flich, “Exploring NoC

Virtualization Alternatives in CMPs,” in The 20th Euromicro International

Conference on Parallel, Distributed and Network-Based Computing (PDP), pp.

437-482, 2012.

23. Alessandro Strano, Francisco Triviño, José Flich, Davide Bertozzi, José L.

Sanchez, Francisco J. Alfaro: “OSR-Lite: Fast and Deadlock-Free NoC

Reconfiguration Framework” in International Conference on Embedded

Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII)

(2012), Best Paper Award, joint publication between UPV and UNIFE.

24. M. Lodde, T.Roca and J. Flich "Heterogeneous Network Design for Effective

Support of Invalidation-based Coherency Protocols", in 6th International

Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip,

2012

25. M. Lodde, J. Flich and M.E. Acacio "Heterogeneous NoC Design for for

Efficient Broadcast-based Coherence Protocol Support", in Sixth ACM/IEEE

International Symposium on Networks-on-Chip (NOCS), 2012

26. Nicola Caselli, Alessandro Strano, Daniele Ludovici, Davide Bertozzi:

“Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous

Channels” in IEEE 6th International Symposium on Embedded Multicore SoCs

(MCSOC12) (2012). Best Paper Award.

27. Hervé Tatenguem, Alessandro Strano, Vineeth Govind, Jaan Raik, Davide

Bertozzi: “Ultra-Low Latency NoC testing via Pseudo-Random Test Pattern

Compaction”. ACACES 2012, Eighth International Summer School on

Advanced Computer. Fiuggi (Italy), 2012.

28. Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf

Schlichtmann “Non-intrusive trace & debug noc architecture with accurate

timestamping for GALS SoCs” in Proceedings of the eighth IEEE/ACM/IFIP

international conference on Hardware/software codesign and system synthesis

(2012), joint publication between UNIFE and IMC.

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29. Herve Tatenguem, Alessandro Strano, Vineeth Govind, Jaan Raik, Davide

Bertozzi: “Ultra-Low Latency NoC testing via Pseudo-Random Test Pattern

Compaction” in International Symposium on System on Chip (SoC). (2012)

30. Alberto Ghiribaldi, Alessandro Strano, Michele Favalli, Davide Bertozzi:

“Power Efficiency of Switch Architecture Extensions for Fault Tolerant NoC

Design” in Third International Green Computing Conference (IGCC'12) (2012)

31. Samuel Rodrigo, Frank Olaf Sem-Jacobsen, Herve Tatenguem, Tor Skeie,

Davide Bertozzi “Cost-effective Contention Avoidance in a CMP with Shared

Memory Controllers” in 18th International European Conference on Parallel and

Distributed Computing (Euro-Par 2012) (2012), joint publication between

SIMULA and UNIFE.

32. Alessandro Strano, Davide Bertozzi, Federico Angiolini, Lorenzo Di Gregorio,

Frank Olaf Sem-Jacobsen, Vladimir Todorov, et al. “Quest for the ultimate

Network-on-Chip: the NaNoC project” in Interconnection Network

Architecture: On-Chip, Multi-Chip (INA-OCMC) (2012), joint publication

between all partners.

33. Roca, A.; Hernández Luz, C. ; Flich, J.; Silla, F. ; Duato, J. "Enabling High-

Performance Crossbars through a Floorplan-Aware Design," 2012 41st

International Conference on Parallel Processing, pp. 269-278, 2012

34. Q. Yu, J. Cano, J. Flich and P. Ampadu. “Transient and Permanent Error Control

for High End Multiprocessor Systems-on-Chip”, in Sixth ACM/IEEE

International Symposium on Networks-on-Chip (NOCS 2012), Lyngby,

Denmark, May 2012.

35. Francisco Triviño, Davide Bertozzi, and José Flich. “A Fast Algorithm for

Runtime Reconfiguration to Maximize the Lifetime of Nanoscale NoCs”. In

Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC),

2013, joint publication between UPV and UNIFE.

36. Alberto Ghiribaldi, Davide Bertozzi, Steven Nowick, “A Transition-Signaling

Bundled Data NoC Switch Architecture for Cost-Effective GALS Multicore

Systems”, accepted in October 2012 for presentation at the Design Automation

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and Test in Europe Conference, march 18-22 2013, accepted, but not published

yet.

1.1.2. Peer-­reviewed  journal  papers  

37. Francisco Triviño, José Luis Sánchez, Francisco José Alfaro, José Flich:

“Virtualizing network-on-chip resources in chip-multiprocessors” in

Microprocessors and Microsystems, vol. 35, issue 2, pp. 230-245, 2010.

38. C. Hernández, A. Roca, J. Flich, F. Silla, and J. Duato, “Fault-Tolerant Vertical

Link Design for Effective 3D Stacking,” Computer Architecture Letters, vol. 10,

no. 2, pp. 41-44, 2011.

39. A. Roca, J. Flich, F. Silla, and J. Duato, “A low-latency modular switch for

CMP systems,” Microprocessors and Microsystems - Embedded Hardware

Design, vol. 35, no. 8, pp. 742-754, 2011.

40. Hernández, C.; Roca, A.; Silla, F.; Flich, J. & Duato, J. ,“Characterizing the

impact of process variation on 45 nm NoC-based CMPs” in Journal of Parallel

and Distributed Computing, Volume 71, Issue 5, May 2011, Pages 651–663.

41. S. Rodrigo Mocholi, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho,

F. Silla, and J. Duato. Cost-Efficient On-Chip Routing Implementations for

CMP and MPSoC Systems, IEEE Transactions on Computed Aided Design

30(4):534-547 , 2011, joint publication between UPV and UNIFE.

42. A. Strano, C. Hernández, F. Silla, and D. Bertozzi, “Self-Calibrating Source

Synchronous Communication for Delay Variation Tolerant GALS Network-on-

Chip Design.,” in Special issue of the International Journal of Embedded and

Real-Time Communication Systems (IJERTCS)., 2011, joint publication

between UPV and UNIFE.

43. Hernández, C.; Roca, A.; Silla, F.; Flich, J. & Duato, J. , “On the Impact of

Within-Die Process Variation in GALS-Based NoC Performance”. IEEE Trans.

on CAD of Integrated Circuits and Systems, Volume 31, issue 2, 294-307, 2012.

44. Francisco Triviño, José L. Sánchez, Francisco J. Alfaro, and José Flich.

Network-on-Chip Virtualization in Chip-Multiprocessor Systems. International

Journal of Systems Architecture, Volume 58, Issues 3-4, pp. 126–139, March

2012.

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45. Alessandro Strano, Nicola Caselli, Simone Terenzi, Davide Bertozzi

“Optimizing Pseudo-Random Built-In Self-Testing of Fully Synchronous as

well as Multisynchronous Networks-on-Chip” in Special issue of the

International Journal of IET Computers & Digital Techniques. (2012)

46. A. Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José

Flich, José L. Sánchez, Francisco J. Alfaro, Michele Favalli, and Davide

Bertozzi, “A Complete Self-Testing and Self-Configuring NoC Infrastructure for

Cost-Effective MPSoCs,” (ACM) Journal of Transactions on Embedded

Computing Systems (TECS), 2012, joint publication between UPV and

UNIFE.

47. F. O. Sem-Jacobsen, S. Rodrigo Mocholi, T. Skeie, A. Strano, and D. Bertozzi,

“An Efficient, Low-Cost Routing Framework for Convex Mesh Partitions to

Support Virtualisation,” ACM TECS Special Issue on On-Chip and Off-Chip

Network Architectures, 2013, joint publication between UNIFE and SIMULA.

48. F. O. Sem-Jacobsen, S. Rodrigo Mocholi, A. Strano, T. Skeie, D. Bertozzi, and

F. Gilabert, “Enabling Power Efficiency through Dynamic Rerouting on-Chip,”

ACM TECS Special Issue on On-Chip and Off-Chip Network Architectures,

2013, joint publication between SIMULA and UNIFE.

1.1.3. Invited  Talk  

Federico Angiolini, iNOCs: “Synthesis of On-Chip Interconnects” at the Winter

School on Design Technologies for Heterogeneous Embedded Systems, http://fetch-

conference.org/, January 7-9, 2013.

1.1.4. European  Nanoelectronics  Forum  2012  

NaNoC project presented a poster at the forum which took place November 20-21 in

Munich, Germany. See http://www.nanoelectronicsforum.org/. It consisted of 2 pages in

A0 format. The poster is included here:

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1.1.5. Book  Chapters  

1. The following chapters have been published in the book “Designing Networks On-

Chip Architectures in the Nanoscale Era”, edited by José Flich and Davide Bertozzi,

published by Chapman & Hall/CRC Press (Taylor and Francis), ISBN-13: 978-

1439837108

- Chapter 2: Switch Architecture, by G. Dimitrakopoulos and D. Bertozzi. - Chapter 4: Topology Exploration, by F. Gilabert, D. Ludovici, M.E. Gómez, and

D. Bertozzi - Chapter 5: Routing Algorithms and Mechanisms, by J. Flich, S. Rodrigo, A.

Roca, and S. Medardoni - Chapter 12: Congestion Management and Process Variation, by J. Flich, F. Silla,

C. Hernández, and M. Lodde - Appendix: Switch Models, by D. Bertozzi, S. Medardoni, A. Roca, J. Flich, F.

Silla, and F. Gilabert

2. The following chapter has been published in the book “Communication

Architectures for Systems-on-Chip” in CRC Press, 2011:

- F. Angiolini, S. Murali, „Quality-of-Service in NoCs“, book chapter, pp. 127-157.

1.1.6.     Conference  Posters  

1. HiPEAC Innovation Event, May 3-5, 2010, Edinburgh UK

https://sites.google.com/site/nanocproject/file-cabinet

1.1.7. Conference  Tutorials  

1. Sonntag, S. & Gilabert, F. Design space exploration and performance evaluation

at Electronic System Level for NoC-based MPSoC. IEEE/ACM International

Conference on Computer-Aided Design (ICCAD), 2010, 336-339

1.1.8.     Interviews  

1. J. Flich. Interview on UPV campus television, 2010

http://sites.google.com/site/nanocproject/news/nanocinthenews

2. J. Duato, J. Flich. Interview on UPV campus television, 2010

http://sites.google.com/site/nanocproject/news/nanoconupvtv

3. D. Bertozzi. I ricercatori e I fondicomunitari. Interview, Sept. 2010

http://www.nottericercatori.it/2010/i-ricercatori-e-i-fondi-comunitari/

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4. A. Strano. Interview on UNIFE TV, Sept. 2010

http://www.youtube.com/watch?v=ncRBVjK5YOY

5. Duato J. Interview in research EU. Results supplements, nº 29 November 2010

Blooming innovation: Interview with Professor José Duato of NaNoC.

1.1.9. Press  Releases  

1. Developing an innovative design platform for future Network-on-Chip,

Innovations Report, June 2010

http://www.innovations-

report.com/html/reports/information_technology/developing_innovative_design_p

latform_future_network_155875.html

2. European NaNoC project to focus on future Network-on-Chip design platform.

EETimes.eu, June 2010

http://sites.google.com/site/nanocproject/news/nanocpressrelease

1.1.10. Video  

A video has been produced for illustrating the NaNoC project to a general and

widespread audience with no technical background:

http://www.youtube.com/watch?v=cRGNom0sY0g

1.1.11. Internal  Dissemination  

Lantiq has linked the video about NaNoC on its web site and it has circulated the

paper “Quest for the ultimate Network-on-Chip: the NaNoC project” though the news

channel and the intranet of the company.

http://www.lantiq.com/news-center/lantiq-video

1.1.12. Patents  

[1] Vladimir Todorov et al. “System having trace resources”, filed on December 27,

US patent, 13/337,406, 2011

[2] Vladimir Todorov et al. "Methods and Apparatuses for Interconnect Tracing"

filed on July 20, US patent 13/554,039, 2012.

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[3] Frank-Olaf Sem-Jacobsen et al. “Method and apparatus for determining paths

between source/destination pairs”, US patent application no. 13/630,826, foreseen

embargo date Nov 11, 2013

[4] Frank-Olaf Sem-Jacobsen et al. “Method and apparatus for determining paths

between source/destination pairs”, European patent application no. 12189314.3,

foreseen embargo date Apr 19, 2014

1.3.   Task  7.2:  Summer  schools    

1. NaNoC partners M. Lodde and J. Flich contributed to the 7th International

Summer School on Advanced Computer Architecture and Compilation for High-

Performance and Embedded Systems, 2011:

- "Memory Hierarchy and Network Co-design through Trace-Driven Simulation"

2. NaNoC summer school has been held in Munich by Intel in July 2012. 14

lectures from NaNoC experts from project partners, academia and industry, over

3 days have been followed by 70 students. Details are reported in a separate

summer school report.

1.4.     Task  7.3:  Web  site    

Partner SIMULA has successfully maintained the NaNoC website www.nanoc-

project.eu without downtime. It was set up a few days after project start and filled

gradually with project results such as the references to published papers and other

events. It especially provides the Common Exchange Format (CEF) documentation

with proper formatting for web reading next to the print format.

CEF is an XML-based file format developed within NaNoC for tool interoperability.

It allows a flow of information between many tools up and down in the design

hierarchy.

Website statistics from Google show slightly increasing activity over time. Figure 1

below show the hits per day over the 1096 days (3 years) project run time.

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Figure 1: NaNoC web site accesses over project time

The following chart shows the regional distribution of the web site visitors.

Figure 2: NaNoC web site access statistics

5. CONCLUSIONS  

The joint dissemination activity of all project partners from the beginning of the

project, lead to an impressive outcome, with scientific articles, web site and summer

school as the highlights.