D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP

2002-12-13

DESIGN AND IMPLEMENTAION OF A DDR SDRAM CONTROLLER

FOR SYSTEM ON CHIP

Magnus Själander

MO/EAB/RTN/D Magnus Själander2002-12-13 2

Contents

• Double Data Rate Interfaces• DDR SDRAM Architecture and Functionality• DDR Memory Controller• Data Resynchronization• Floorplan and Place & Route• Future Work• Conclusion


Double Data Rate Interfaces

Advantages• Time of Flight• Clock Skew• Pin Count • BandwidthDisadvantage• Synchronization

Clk

Data

SDR

D0 D1 D2 D3 D4 D5 D6 D7

DDR

Clk

Data D0 D1 D2 D3 D4 D5 D6 D7

Data Strobe

Don't care

New• Data Transmissions on rising and falling edge• Data Strobe


SDRAM Architecture

• Four Banks• Row and Column Select Lines• 1T Memory Cells• Sense Amplifiers• Global Data Path

Row Decoder Row Decoder

Col

umn

Dec

oder

and

Glo

bal D

ata

lines


Central I/ORow Decoder Row Decoder


BL

WL

BL*

Cs

CBL

BL

BL*

M1VDD

SE*

SE

Sen

se A

mpl

ifier

s

Sen

se A

mpl

ifier

s

Col

umn

Dec

oder

and

Glo

bal D

ata

lines

Sen

se A

mpl

ifier

s

Sen

se A

mpl

ifier

s

Col

umn

Dec

oder

and

Glo

bal D

ata

lines

Sen

se A

mpl

ifier

s

Sen

se A

mpl

ifier

s

Col

umn

Dec

oder

and

Glo

bal D

ata

lines

Sen

se A

mpl

ifier

s

Sen

se A

mpl

ifier

s


DDR SDRAM Architecture

• 2n-prefetch• Delay Lock Loop

Add

ress

Reg

iste

r

Row

Dec

oder

Col

umn

Buf

fer Column Decoder

Programming Register

Latency and Burst Length

DLL Stro

beG

en.

Ref

resh

Cou

nter

Row

Buf

fer

Bank Select

Bank 1

Bank 2

Bank 3

Bank 4

Sen

se A

MP

2n-p

refe

tch

Out

put B

uffe

rI/O

Con

trolInput Buffer

Data Input RegisterSerial to Parallel

64

64

32

Timing Register

ADDR

CK, CK

CK, CK

CK

, CK

CK

, CK

DQ

DQS

CK

E

CS

RA

S

CA

S

WE

DM

WE

i

DM

i

WEi

DMi


DDR SDRAM Improvements

• Long Delay in Column Decode and Data Lines

• Added a Delay Lock Loop to Increase Clock Frequency

Clk

D0Data

Readstarted

Dataavailable

7 nsD1

Clk

Data D0 D1

Readstarted

Dataavailable

7 ns

Delayed Clk

Delay

7 ns

Clock period

5 ns

Clock period

DDR SDRAM

SDR SDRAM


DDR SDRAM Commands

Same Commands as for Standard SDRAM• READ• WRITE• ACTIVATE• PRECHARGE• REFRESH• MRS (Mode Register Set)Added• EMRS (Extended MRS)


DDR SDRAM Memory Controller

AHB

Core MemoryController

DQeven

DQodd

AH

B B

uss

DDRSDRAM

Command

Write Data

Read Data

Command

Write Data

Command

Read Data

Read Data


APB

AP

B B

uss

CommandData

Initialize

Address

Address

Address

Data

DQData Mask

DQS

Data Strobe


Core Memory Controller

CurrentAddress

NextAddress Open Banks

Read WriteCommand

CommandTiming

Address

Address

Increment

Activate/PrechargeCommand

Read/WriteCommand

CommandAddress

Row

Open

Command

Address

Boundary

RefreshRefresh

Address

Address

InitializeInitialize Initialization

Command

Address

Enable DQS


AHB Interface

CoreMemory

Controller

AH

B B

uss

DDRSDRAM

Command

Write Data

Read Data

Write Data

Command

Read DataOdd

AHB Interface

Address

Address

x2

DataBuffer

AHBCore

Read DataEven

Data

Addr

Data

Data

Addr

Data

Command

Address

DQeven

DQodd

SamplePresent

Increment Counter

Data MaskDQ

Data Strobe

DQS


Arbiter

AHB I

Core MemoryController

DQeven

DQodd

AH

B B

uss 0

DDRSDRAM

Command

Write Data

Read Data

Write Data

Command

Read Data

Read Data


Address

Address

DQ

Data Mask

DQS

Data Strobe

AHB II

Command

Write Data

Read Data

AddressAH

B B

uss 1

Arbiter

CommandAddress

Command

AddressCommandAddress

Write Data

Data MaskWrite Data

DataStrobe

DataStrobe


Capturing the Data

• Phase Shift the Data Strobe• Resynchronize the Data

Clk

Command READ NOPNOP

Address Col n

Data Strobe

Data

Don't care


Phase Shift the Data Strobe

• Delay Lock Loop• Inverter Delay• PCB Line Delay• Programmable Delay Line with Temperature Sensing

Programmable Delay Line

Programmable Look Up Table

Data StrobeDelayed 90o

Data Strobe

Temperature Sensor

Digital Delay Line

Phase Detector and Control Logic

Data Strobe Data StrobeDelayed 90o


Synchronization of the Data

One Flip-Flop for each Flank to Sample D Q

D Q

Data Strobe

Data Data Odd

Data Even

Data Strobe

Data

Data Even

Data Odd

0 1 2 3 4 5 6 7

0 2 4 6

1 3 5 7

Do not care


Synchronization of the Data Continued

Reference Clk

Clk x2

Data Even 0

Data Strobe

Rising Edge of Data Strobe

Data Stable

Reference Clock Low

Reference Clk

Clk x2

Data Even 0

Data Strobe

Not stable

Rising Edge of Data Strobe

Data Stable

Reference Clock High


Synchronization of the Data Continued

Simplified Phase Detector

Clk I

Clk II

Q I

Q II

Phase

Undefined

D QI

D QII

Clk II

Clk I

High

High

& S Q

R

Phase

Time LineTime LineTime Line


Floorplan

Data Buffer (AHB II)

Data Buffer (AHB I)

630 m

50 m

700 m15 m

35 m

155 m

50 m

185 m

50 m

155 m

50 m

700 m

AHB Interface region

20 m

DDR Memory Controller

DDR ControlSignals

Address andData Buss

AHB I Read, Write and Address Buss

AHB II Read, Write and Address Buss

Clock Signals

APB Signals

AHB I ControlSignals

AHB II ControlSignals


Place & Route

AHB II

ABH IData Buffer I

Data Buffer II

AHB CoreAHB x2

APB

RefreshInitialization

Current Address

RW commandCommand TimingOpen Banks Top

Arbiter Next Address Data Out


Future Work

• Improved Refresh Handling• Attempt to Reduce Initial Latency for Bursts• Improved Buffer Handling


Conclusion

• Working Implementation• Smaller Changes to Improve Performance• Highlights Difficulties and Solutions

2002-12-13

Questions ?

Documents

D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP