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DESIGN AND IMPLEMENTATION OF THE DIGITAL CONTROLLER FOR A FUEL CELL DC-DC POWER CONVERTER SYSTEM
O.A. AHMED, J.A.M. BLEIJS
presentation Outline
IntroductionDynamic Performance of PEMFCFC Converter FeaturesController DesignSimulation ResultsControl Algorithm ImplementationConverter System ImplementationConclusions
2
Introduction
Back-up diesel generator PV system Wind Turbine
H2
Battery - +
Battery or Ultra-capacitor
DC =
AC ~ Critical
AC load
Single or three-phase AC load
DC =
DC =
AC =
DC =
AC ~
DC = AC
link
bus
DC ~
DC =
AC =
DC =
Fuel Cell system
DC =
DC =
DC link bus, voltage between 600V ~800V
DC Microgrid Power System
3
Introduction
DC Microgrid may comprise of :A dispatchable power generator, such as the fuel cell (FC) or a back-up diesel generator.Non-dispatchable sources, such as solar PV and wind turbines. Energy storage, such as ultra-capacitor or battery.The overall efficiency of the distributed system depends on efficiency of power electronic converters. To obtain a cost-effective converter solution:High efficiency.Low cost.Robust control system
4
objective
Development of a Two-Loop Controller for
a High Efficiency
FBCFC for a FC generator
Dynamic Response
Analysis and Modeling of a Ballard Nexa 1.2kW PEMFC
Digital Controller
Design Based on a
TMS320F2812 DSP
5
Dynamic Performance of PEMFC
Experimental Dynamic Response Set-up for
PEMFC
Nexa data acquisition system is inadequate to show actual response.
Fast-acting switches and high speed transducers are used.
The gross stack current is 1.3 of the nominal current.
6
Dynamic Performance of PEMFCAccurate transient response
using experimenta
l set-up
Data log file
7
Dynamic Performance of PEMFC
Rp
RLoad
Continuous
pow ergui
current
f uel f low rate
Air f low rate
fuel flow rate regulator1
v
+
-simout2
To Workspace2
simout1
To Workspace1
simout
To Workspace
Scope3
Scope2
Scope1
g m
1 2
Ideal Switch
[I]
Goto3
[Pulse]
Goto2
[V]
Goto1
[A]
GotoFuelFr
AirFr
m
+
-
Fuel Cell Stack1
[I]
From3
[Pulse]
From2
[V]
From1
[A]
From
i
+
-
Breaker Control
<Voltage><Voltage>
<Current>
<Stack Ef f iciency (%)>
<Stack consumption (Standard lpm) [Air(Yellow); Fuel(Magenta)]>
<Flow Rate (lpm) [Air(Yellow); Fuel(Magenta)]>
<Stack consumption (lpm) [Air(Yellow); Fuel(Magenta)]>
<Utilization (%) [O2(Yellow); H2(Magenta)]>
<Slope of Taf el curv e>
<Exchange current i0 (A)>
<Nerst v oltage En (V)><Nerst v oltage En (V)>
<Open circuit v oltage Eoc (V)>
DC bus current
DC bus v oltage
Fuel cell model of test with resistive load
8
Dynamic Performance of PEMFC
Simulated Transient Response of FC model
4 5 6 7 8 9 10 11 12 13 140
10
20
30
40
50
60
70
Time (s)
Sta
ck V
olta
ge (V
), S
tack
Cur
rent
(A)
Stack Current
Stack Voltage
9
FC Converter Features
The clamp switch gives zero voltage switching (ZVS) for all switches at turn on and alleviates the usual voltage ringing across the bridge switches (S1~S4);
At turn off the voltage across all switching devices is clamped to the capacitor voltage.
The output rectifier diodes operate with zero current switching (ZCS).
Full bridge with voltage doubler technique results in reduced voltage across output capacitors and diode rectifier. Minimizes the voltage rating of the semiconductor devices. Reduces the turn ratio of high frequency transformer to half that of the conventional FBCFC.
FBCFC for FC system
S4
S3
S2
Lb=475µH iLb
vfc =50-26V
C1
HF Tr.
5:37
D2
io
vo
+
-
Ro
LLK=2µH D1
S1
C2
Cp1 Cp3
Cp2 Cp4
Cpc
A
B
iLk vpri
Ca
Sc
iCa
vSc
vCa
ic1
ic2
10µF Cp1~ Cp4=16nF
C1= C2=400µF
9nF
S1~S4=SKM120B020
Sc=IXFK73N30
D1= D2= C2D05120A
Untapped secondary winding transformer simplifies the transformer construction, improves window utilization, and results in lower leakage inductance.
10
Controller Design
Initially an analogue PI was designed for the FBCFC based on its small signal transfer functions .
Digital average current (DAC) mode control and predictive current control (PCC) techniques can be used for the system.
Since FC takes 0.24 second to respond after a sudden load application from no-load DAC is selected without need for a complex control algorithm.
Two-loop PI digital controller
11
Controller Design
The designed digital controller takes into account the sampling delay (Hsmp) and the computation delay (Hc).
Two PI controllers with anti-windup protection were designed and their optimal parameters obtained using the Control Design Toolbox in Matlab.
Based on the designed digital controller loop for the FBCFC, the transfer function for the current, voltage and overall open loop response of the system are obtained .
12
Controller Design
Bode Plot of Current Controller Open Loop
The plot indicate that inner loop Cid(z) gain has a desired crossover frequency at 5kHz with a phase margin of 590.
Digital PI parameters for Cid(z) are: Kpc= 0.1147, and Kic= 506.66.
13
Controller Design
Bode Plot of Voltage Controller Open Loop
To accommodate the slow FC response, low bandwidth is used for voltage loop Cvi(z).
The voltage loop has a crossover frequency of 149Hz and a phase margin of 58.70.
Digital PI parameters for Cvi(z) are: Kpv = 1.08625,Kiv = 100.748
14
Controller Design
Bode Plot of Overall Open Loop System
Due to the active clamp the resonance is absence.
The plots show that the bandwidth and phase margin of the controller system are designed as desired.
15
simulation results
Output voltage waveform during load changes
The simulated dynamic response of the converter at sudden load changes shows that the voltage recovers to its steady-state value within 15m sec.
Designed PI digital controller has been implemented in a DSP; the on-chip ADC converter, PWM “compare function” and other functions were emulated in Simulink.
16
control algorithm implementation
NO
NO
YES
Update Duty Cycle of PWM
DE =5%
DE < 5%?
YES DE > 42%?
END
Receiving Data from the Host Setting the RTDX in non-blocking
mode
Update Compare Register 2 CMPR2 =TPR-CMPR1
NO
YES
DE =42%
0.506*T1PR > CMPR1 > 0.725*T1PR
Initialization of DSP Event manager (EVA) initialization Enabling PIE peripheral interrupts Setting ACTR register, setting
PWM1&PWM3 active high and PWM2&PWM4 active low
Setting DPTCONx Register
Start
IQ math library in CCS is used for the PI compensators, ADC results and ADC and PWM scaling factors.
The number of GP timers in a DSP is limited to four. The PWM signals for all switches are generated using only one GP timer with dead-band zone. Flow chart of the overlap PWM
algorithm for FBCFC
17
control algorithm implementation
Software block diagram of 32-bit PI digital control for voltage and current
loop
IQ_Nmpy IQN×IQN
Kp
IQ_Nmpy IQN×IQN
Ki IQ_Nmpy IQN×IQN
Kcorr
max
min
1/Z +
+
+ + + + + -
Ref
FDB Saturation
Anti-windup
-
32-bit PI controller
Fbk
18
converter system implementation
FBCFC with voltage doubler but without clamp circuit:
secondary voltage (ch3), drain-source voltage across S1 (ch4)
The sampling frequencies are chosen 20 kHz for the current-loop and 2.5 kHz for the voltage-loop controllers.
The FBCFC without clamp circuit shows high voltage overshoots across the MOSFETs resulting in increase switching and conduction losses and reducing the converter’s efficiency.
Proposed FBCFC: primary voltage (ch3), FC current
(ch4), clamp switch voltage (ch2)
19
converter system implementation
Simulated and Experimental Converter
Efficiency
20
conclusions
FC experiments showed that the number of measurement points using Nexa log file is not sufficient to plot the accurate transient response characteristics of the FC stack. It is observed that the modelled FC matches very well with the real FC system results
A two-loop digital controller with anti-windup protection has been developed for a 1.2kW active clamp FBCFC topology with a voltage doubler.
The experimental results have validated the accurate modelling for the FC converter system.
Simulation and practical measurements of the proposed converter and other configurations at different loads have shown that the proposed configuration has the highest efficiency.
21
