CUSTOM MANUfACTURED IN U.S.A. BV RADIO SHACK, … · 5-Meg Hard Disk ®_-----Service Manual Ripple Voltages +5 12V-12V Efficiency 65 50 150 150 mV mV mV % Over-voltage Protection

CUSTOM MANUfACTURED IN U.S.A. BV RADIO SHACK, A DIVISION Of TANDV CORPORATION

5-Meg Hard Disk Service Manua1

------------- TRS-SO ® --~--------

TRS-SO® 5-Meg Hard Disk

Service Manua1

Cata10g Number 26-1130

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5-Meg Hard Disk-----------TRS-aO ®

Service Manual

TRS-80· 5-Meg Hard Disk Service Manual

copyright© 1982 Tandy Corporation

AIl Rights Reserved

Reproduction or use, without express written permission fromTandy Corporation, of any portion of this manual isprohibited. While reasonable efforts have been taken in thepreparation of this manual to assure its accuracy, Tandycorporation assumes no liability resulting from any errorsor omissions in this manual, or from the use of theinformation obtained herein.

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.......5...-....M....e....g.......H....a....r.....d_D....i ....s.....k.............. TRS-SO ®

Contents

Warnings

1/ Overview.

2/ Technical Specifications.

3/ Connections •.Model I ...

4/ Power-Up and Power-Down.

5/ Replacement Procedures.

Service Manual

.5

• • 7

• •••• 0 • Il............ .. 15

.19

.23

6/ Maintenance .••.•.••. .25

7/ Theory of Operation •...••.•.••Hard Disk Control1er Board •.

.29•••• 34

8/ Troubleshooting the Power SupplyDrive Only) .•...•...•.•....•.••

<Secondary.47

9/ Printed Circuit Boards. .51

10/ Wiring Diagrams.

11/ Parts List.

12/ Schematics.

.53

.57

.63

13/ Supplement CI ••••••••••••• CI ••• 69

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5-Meg Hard Disk Service Manual

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************************************************************Warnings

************************************************************

Do not move or tilt the Hard Disk Drive unit while the driveis running. Permanent damage to the drive may occurresulting in the loss of information or damage to the disk.

Do not drop the Hard Disk Drive unit from any height aspermanent damage to the drive may occur.

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5-Meg Hard Disk

1/ Overview

®Service Manual

The TRS-SO 5-Meg Hard Disk Unit consists of twonon-removable 5.25-inch disks. There are four Read/Writeheads {one on each side of each platter> which move towardsor away from the center of the disk as needed.

The Disks and Read/Write heads are fully enclosed in asealed chamber. A special air filteration system preventsdust and other particles, which destroy data, from reachingthe disks. Another filtering system allows pressureequalization with the "outside" air pressure.

UNDER NO CIRCUMSTANCES MUST THE CHAMBER BE UNSEALED IN THEFIELD. A CLASS 100 CLEAN ROOM ENVIRONMENT IS NEEDED FORUNDER-THE-BUBBLE REPAIR.

On aIl Hard Disk Units, flaws in the media are indentifiedat the factory before the disk drives are delivered to thecustomer. Attached to the bottom of each disk drive unit isa "Media Error Map". This map identifies the flawed trackson that particular unit.

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5-Meg Hard Disk Service Manual®_-------------

2/ Technical Specifications

Basica11y, the hard disk unit consists of two platters (ordisks) lying paraI leI within the unit. There are also fourRead/Write heads, one on each side of each platter. Theseheads move towards or away from the center of the disk asneeded.

When a unit is purchased, there will be no more than 3tracks per head with defects. This will not exceed 8 tracksper drive with defects. Also there will not be any flaws onTrack O.

Disks/PlattersHeads/Recording SurfacesTracks per InchCylindersTracks

24

254153612

============================================================Hard Disk Cylinders Tracks Sectors Bytes

1 1531

61241

19,584128

321

5,013,50432,7688,192

256============================================================

AC Power Requirements50/60 Hz +/- 0.5 Hz100/115 VAC installations (90 to 127 V)200/230 VAC installations (100 to 253 V)Fuse 2.5 at 250 Volts (InternaI)

========================================================Power Supply (Primary Drive) Operating Characteristics

Vin RangeInput Select l15VInput Select 230V

Line Frequency

Min

90198

47

Typ

115230

50/60

Max

135264

63

Units

VrmsVrms

Hz

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5-Meg Hard Disk Service Manual®

Output Voltages VI +5V 4.95 5.1 5.25 VoltsV3 +12V Il.4 12 12.6 VoltsV4 -12V Il -12 -15 Volts

Output Curren't VI +5V 2.50 5.0 AmpsV3 +12V .75 2.0 AmpsV4 -12V .005 .10 Amps

Ripple Voltages VI +5V 50 mVV3 +12V 150 mVV4 -12V 150 mV

Efficiency 70 %

Hold Up TimeFull Load, Low Line 10 mSecFull Load, Nom Line 16 mSec

Over-Voltage Protection 5.80 6.80 Volts========================================================

========================================================Power Supply (Secondary Drive) Operating Characteristics

Min Typ Max Units

Vin RangeInput Select l15V 95 115Input Select 230v 180 230

Line Frequency 47 50/60

Output Voltages +5V 4.75 5+12V Il.4 12-12V -11 -12

Output Current +5V .45+12V .75-12V .005

135 Vrms264 Vrms

63 Hz

5.25 Volts12.6 Volts-15 Volts

2.5 Amps2.0 Amps.10 Amps

Load Regulation(measured by varyingload on considered outputfrom typ to either min or maxrated load) +5V 5

l2V -5-12V -8.3

5525

%%%

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5-Meg Hard Disk Service Manual®_-------------Ripple Voltages +5

12V-12V

Efficiency 65

50150150

mVmVmV

%

Over-voltage Protection 5.80 6.80 Volts========================================================Dimensions

HeightwidthLengthWeight

primarySecondary

EnvironmentAmbient Temperature

Relative HumidityMaximum Wet BulbHeat DissipationAltitude

5.50 in (13.97 cm)14.00 in (35.56 cm)15.00 in (38.10 cm)

15.5 lbs (33.10 kg)12.5 lbs (27.5 kg)

50 to 95 degrees F.(10 to 35 degrees C.)8% to 80%78% non-condensing

operating: 0 to 6000 feet(0 to 1829 meters)storage: -1000 to 12000feet(-305 to 3656 meters)

Warm-Up PeriodMinimum On Power-up 2 minutesMinimum to Turn System On

After Turning System Off 15 seconds

Hard Disk DriveDisk Organization

Tracks per UnitTracks per PlatterSectors per TrackBytes per SectorCylinders per DiskAverage LatencyRotational SpeedRecording DensityFlux DensityTrack Density

Storage Capacity (Hard Disk)Unformatted

Bytes per Track

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612306342561538.34 msec3600 rpm +/- 1%76907690254

10400

5-Meg Hard Disk

-------------- TIQ!~.,8:Cl ®

Bytes perSurfaceBytes per Drive

FormattedBytes per Drive

Service Manual

1.59 MEG6.33 MEG

5 M (primary)5 M (Secondary)

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5-Meg Hard Disk

3/ Connections

Service Manual®

:::"""'!il ... ~~lL.I --------------

Connecting Your primary Drive to a Model III

Be sure aIl power is OFF.

Note: Master unit does not come with Data Out connectors.These are supplied with each secondary unit and requireinstallations.

Locate the hard disk expansion cable. Connect one end tothe 1/0 bus card edge of your Model III. Be sure the cableexits the rear of the computer so that it won't bind.

Connect the opposite end of this cable to the COMPUTER INconnector, located on the rear panel of the primary drive.

Connect the power cord to the primary drive. Plug the otherend into an appropriate AC power source.

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S-Meg Hard Disk Service Manual

®_-------------

Figure 1. Back Panel of Hard Disk Drive

1. Computer In (50-pin> Connect the Hard DiskExpansion Cable from the I/O bus card edge of theModel III to this jack.

2. Control Out (34-pin> Connect one end of aSecondary Hard Disk Expansion Cable to thisconnector. The other end connects to the firstsecondary drive.

3. Data Out A (20-pin> Connect one end of theData Cable from the first secondary drive to thisconnector.

4. Data Out B (20-pin> Connect one end of theData Cable from the second secondary drive to thisconnector.

5. Data Out C (20-pin> Connect one end of theData Cable from the third secondary drive to thisconnector.

6. Filter

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5-Meg Hard Disk Service Manual®_-------------connecting Secondary Drives

The secondary drives are connected to the computer via theprimary disk drive. The drives must be stacked with theprimary drive on top of the secondary drives.

Locate the secondary hard disk expansion cable. Connect oneend to the Control In jack of the secondary drive and theother end to the Control Out jack of the previous drive inthe chain. If you have only two hard disk drives, thisconnector connects to the primary drive.

If you have another secondary drive, connect the secondsecondary hard disk expansion cable to the Control Out jackand the other end to the Control In jack of the next drivein the chain.

Locate the data cable. Connect one end to the appropriatedata jack (A for the first secondary drive, B for thesecond, and C for the third). Connect the other end to theData In jack on the secondary drive.

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CONTROL. OUT

6t~!!!!!!n!'!n~f~]1D

Figure 2. Back Panel of Secondary Hard Disk Drive

1. Control In (34-pin) Connect one endof a Secondary Hard Disk ExpansionCable to this jack. The other endconnects to the previous Hard DiskDrive.

2. Control Out (34-pin) Connect oneend of a Secondary Hard Disk ExpansionCable to this jack. The other endconnects to the next secondary drive.

3. Data In (20-pin) Connect one end ofthe Data Cable from the the primarydrive to this jack.

4. Filter

Figure 3. A Fully Configured Hard Disk System

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5-Meg Hard Disk----------...........................- TICI!~ ..,8:[] ®

Service Manual

Connecting the Primary Hard Drive ta the Madel 1

To connect the hard disk drives to the Model I you need aModel I Kit <Catalog Number 26-1132>. Included in this kitare:

A Model I Adapter CableThree Diskettes:

HARD DISK OPERATING SYSTEMXTRAINI'rIALIZATION

Important Note: The Expansion Interface must be bufferedbefore the hard disk can be connected to your Model I.Instructions on how to determine whether the ExpansionInterface is buffered are given next.

There are two types of Buffered Expansion Interfaces. Thefirst type is recognized by its cables. The fIat ribboncable between the Expansion Interface and the Keyboard willhave a black box on it. There will also be a 3-wire cablewith a din plug type connector in the middle. See Figure 4.

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5-Meg Hard Disk

Buffered Cable Modification

®

Service Manual

- Din Plug Modification

Figure 4. Expansion Interface/Keyboard with Buffered Modification

If the computer does not have these cables, then you mustlook inside the Expansion Interface through the bottomcover.

Look through the vents on the bottom cover for two rows ofeight memory chip sockets. (The sockets may or may notcontain memory chips.>

If the ROWS of sockets run long ways in the interface -parallel to the keyboard -- then the computer is bufferedand is ready to be connected to the hard disk. See Figure5.

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5-Meg Hard Disk Service Manual.:"""l,.. ...,~IIl--lll ® -----................------........

Figure 50 Buffered Expansion Interface as Viewed From the Bottom

If the ROWS of sockets run perpendicular to the keyboard,the computer is not bufferedo See the illustration below:

Figure 60 Non-buffered Expansion Interface Viewed From the Bottom

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----------------- TRS-aO ® --------------

Figure 7. Connecting the Hard Disk to Your Model l

1. Locate the Model l Adapter Cable. One end has aconnector (40-pin>. The other end has a black boxwith a card edge exiting it.

2. Connect the 40-pin connector (the end with the cable>to the Bus Extension port (also called screen printerport> of your Expansion Interface. The cable shouldexit towards the bottom of the expansion interface.

3. Connect the card edge end to the card edge connector ofthe Hard Disk Expansion Cable (50-pin>. The Hard DiskExpansion Cable should exit the bottom of theconnector.

4. Connect the other end of the Hard Disk Expansion Cableto the COMPUTER IN connector of the primary hard drive.The cable should exit towards the bottom of theconnector.

The primary hard disk drive is now connected.

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5-Meg Hard Disk

-----------TRS..aO ®

4/Power-Up and Power-Down

Service Manual

Model III System Power-Up

1. Make sure aIl power is OFF and aIl floppy diskettedrives are empty.

2. Turn on aIl peripheral equipment (such as a printeror additional floppy diskette drives)

3. Turn on the primary hard drive by turning the POWER KEYclockwise. This also turns on aIl secondary drives.AlI secondary drives' power lights should come on.

4. Turn the computer ON.

s. Insert either the INITIALIZATION diskette or theSTART-UP diskette in floppy Drive O.

6. Press RESET. In a few seconds the screen shows alarge LDOS logo.

If the LDOS logo does not appear, repeat the abovesteps, making sure you inserted the diskette properly.

7. The screen then shows this prompt:

LDOS Ready

Since you've not yet initialized your Hard Disk System,the computer is now operating as a Floppy Disk System,the only way it can operate until you initialize it.

If you've initialized the Hard Disk System, you canremove the START-UP diskette. You only need it tostart up or reset.

To operate the system for floppy disk only, hold down the<CLEAR> key and press the RESET button. (You must keep the<CLEAR> key down until LDOS Ready appears.)

Model III System Power-Down

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®_-------------1. The LDOS Ready prompt shou1d be the 1ast 1ine on

your screen. If not, press <ENTER> or exit yourprogram so that it appears.

2. Remove aIl floppy diskettes from their drives.

3. Turn off any peripheral equipment.

4. Turn off the hard disk drive by turning the powerkey on the primary drive counterclockwise. Thisturns off aIl the drives.

5. Turn off the computer.

Model l System Power-Up

These are the steps to power-up and power-down the Model lHard Disk System. Please use these steps.

1. Make sure aIl floppy diskette drives are empty.

2. Turn on aIl peripheral equipment (such as printerand floppy diskette drives)

3. Turn on the primary hard drive by turning thePOWER KEY clockwise. This also turns on aIl existingsecondary drives. wait for the power lights on aIl thesecondary drives to come on.

4. Turn the Expansion Interface ON.

5. Turn the CPU/Keyboard ON. Wait until aIl floppy diskdrive motors stop, then carefully insert the HARDDISK OPERATING SYSTEM INITIALIZATION diskette or theSTART-UP diskette in Drive O.

The START-UP diskette is a modified copy of yourINITIALIZATION diskette created during initialization.Initialization procedures are described later in thissupplement.

6. Press RESET. In a few seconds the screen shows a largeLDOS logo.

If the LDOS logo does not appear, repeat the above

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5-Meg Hard oisk®

Service Manua1

steps, making sure you inserted the diskette proper1y.

7. At the bottom of the screen, LOOS asks you for thedate. Type today's date in the mm/dd/yy form andpress <ENTER>. For example, for June 17, 1982, type:

06/17/82 <ENTER>

8. LOOS then displays the name and date of the disketteabove the logo. It a1so displays the expanded datebe10w the logo.

9. The screen then shows this prompt:

LOOS Ready

Since you've not yet initialized your Hard oisk System,your computer is now operating as a Floppy Oisk System,the only way it can operate until you initialize it.

If you have already initialized your Hard oisk System,you can remove the START-UP diskette (created duringinitialization). You only need it to start up orreset.

To operate the system for f10ppy disk only, ho1d down the<CLEAR> key and press the RESET button. (You must keep the<CLEAR> key down until LOOS Ready appears.)

Model l System Power-Down

1. The LOOS Ready prompt should be the 1ast line on yourscreen. If not, press <ENTER> or exit your programso that it appears.

2. Remove aIl f10ppy diskettes from their drives.

3. Turn off any peripheral equipment.

4. Turn off the primary hard disk drive by turning thePOWER KEY counterclockwise. This also turns off aIlexisting secondary drives.

5. Turn off the Expansion Interface.

6. Turn off the CPU/Keyboard.

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5-Meg Hard Disk®

Service Manual

5/ Replacement Procedures

Replacement procedures contained in this manual are limitedto case disassembly, removal and replacement ofsubassemblies, and case assembly.

Before beginning repair, disconnect aIl external cables fromthe rear connector panel.

Disassembly

1. Remove the top row of screws (3) from the rear paneland lift off the case.

2. To remove the hard disk control1er board, remove aIlcables from the board (data cables, hard disk expansioncable, controller connecting cables, power harness, andlamp controller harness).

NOTE: At the time of disassembly, be sure that the nylonwasher on center stand-off is saved forreassembly.

3. To remove the hard disk power supply, remove the 4screws which secure the power supply mount-and-shieldto the bottom of the unit and lift off the cover.Loosen aIl cables. Disconnect the power harness fromthe drive unit. Remove the six screws which hold thepower supply board.

Reassembly

1. Fasten the power supply in the bottom of the unit byusing 4 #6 screws and 2 #10 screws. Reconnect the powercables.

2. Replace the power supply shield-and-mount and fasten itusing 4 #6 screws. Reconnect the power harness ondrive. position the clear insulating sheet on the powersupply mount-and-shield.

3. Be sure and replace nylon washer between the hard diskcontrol1er board and center stand-off. Fasten the board

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S-Meg Hard Disk®

Service Manual

using five #6 screws.

4. Reconnect all cables, the lamp driver harness, and thepower harness. (Make sure that the lamp driver harnessis toward the rear of the unit.) Be sure that the datacables are connected so that the cable cornes from theleft-hand side of the plug when looking from the frontof the unit.

5. Replace the case top and 3 #6 screws in the rear panel.

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5-Meg Hard Disk

6/ Maintenance

®Service Manual

The only regular maintenance the 5-Meg Disk Drive requiresis a periodic cleaning of the filter on the back of theunit. Clean this filter whenever it becomes filled with dustand particles.

To clean the filter, carefully remove the outer grill -- DONOT REMOVE THE SCREWS. Then remove the filter and rinsewith tap water. When the filter is completely dry, put itback in the drive.

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5-Meg Hard Disk®

Service Manual

7/ Theory of Operation

Hard Disk Controller Board

General

The hard disk controller board is a discrete implementationof aIl functions required to control the 5.25 inch diskdrive via a standard data and control bus. The controller isfabricated using a mix of high-speed bipolar and MNOSdevices contained on a single two-sided PC board. The designof the circuitry makes use of a high-speed microcontroller,the 8X300, newly developed NMOS support devices, Schottkyand low power Schottky devices. AlI 1/0 connections are madeusing standard ribbon cable connectors. Standard pin-outconfigurations for disk interface connectors permit directpin-for-pin connections to the drives. AlI host to disk datatransfers are buffered by onboard RAM to achieve totallyasynchronous transfers to and from the disk by the host.

The disk controller is built around five basic sections:

Processor Functions

AlI functions of the controller are ultimately disciplinedby the onboard processor. Due to the high data ratesassociated with hard disk drives, a processor capable ofextremely fast execution speed is required for processing ofdata and controlling machine functions within the circuitry.The processor used is the 8X300, a bipolar micro-controllerparticularly well-suited for handling data efficiently athigh rates.

The 8X300 operates at a basic clock rate of 8MHz andperforms aIl operations within two clock cycles giving it aspeed of 4 MIPSS (Million Instructions Per Second) or oneinstruction executed every 250 nanoseconds. The architectureof the processor is different from most popularmicroprocessors in that no common data or address bus isprovided to be shared by RAM, ROM, or peripheral devices.

Instructions are fetched from ROM via a dedicatedinstruction address and data bus. The Instruction Addressbus (IAO - IAI3) is capable of directly accessing 8K wordsof program storage, however, the controller uses only thefirst ten address lines, IAO through IA9, limiting onboardprogram storage to IK words.

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5-Meg Hard Disk

--------------- TIJ:1!S··S:D ®

Service Manual

Program data is input to the 8X300 (U30) on the InstructionData bus (IAO - IA130) which is capable of directlyaccessing 8K words of program storage; however, thecontroller uses only the first ten address lines, IAOthrough IA9, limiting onboard program storage to IK words.

Fast IO Select

An extension byte has been added ante the instruction datamemory to provide port access decoding on aninstruction-by-instruction basis. This "Fast IO Select" byteis not processed by the 8X300, but it is decoded byauxiliary hardware (U39, U44, U45) to provide eight readstrobes and eight write strobes which route data to thevarious devices distributed along the interface vector bus.

The Fast IO byte is latched into a 6-bit latch (U39)trailing edge of MCLK to ensure that the data remains stableduring the entire instruction. This data selects a readstrobe and eight write strobes which route data ta thevarious devices distributed along the interface vector bus.

The Fast IO byte is latched into a 6-bit latch (U39)trailing edge of MCLK to ensure that the data remains stableduring the entire instructions. This data selects a readstrobe and a write strobe through two l-of-8 decoders (U44and U45) which are alternately enabled by the WC* controlstrobe produced by the 8X300. THe read strobe decoder (U45)is always disqualified at the end of instructions by MCLK'(MCLK prime), a delayed copy of MCLK, to provide edges onread strobes during sequential read operations from variousports. This delay compensates for timing races through theFast IO latch (U39) and the control signaIs.

Because each decoder has a unique input, it is possible toselect any read port with any write port during eachinstruction. Data is transferred between the processor andits ports on a separate 8-bit bus called the IO bus. Thisbus is active low. It must be noted that this bus is in noway related to the instruction data bus and should bethought of as simply an 8-bit bidirectional IO bus of the8X300. In fact, it has been renamed as IOO - IO? to reflectthis distinction.

InternaI Bus Control

Several bus control signaIs are produced by the 8X300 toidentify and strobe the data on the IO bus. Write Control

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(WC) is a signal which determines the direction of the datato and from peripherals. When WC is false (during the firsthalf cycle), data is being input to the 8X300 from the 10bus. When WC is true (during the ~econd half cycle, data isbeing output to the 10 bus from the 8X300. Select Control(SC) becomes active during the second half cycle instead ofWC if the 10 bus contains an 8-bit 10 address. the WC and SCsignaIs are combined by a NOR gate (U33) to initiate aIlaccesses from the 8X300 to any output port within oneinstruction instead of the normal 5-bit immediate movesprovided for by the instruction set.

AlI instruction fetches occur late in the second cycle ofthe preceding instruction. This time is marked by thegeneration of a 65 ns (nominal) active high pulse calledMCLK which occurs every instruction. MCLK is used to latchdata prior to being input on the 10 bus to ensure stabilityduring reads. MCLK is also used to disqualify read strobeswhich would otherwise remain true into the second clockcycle of any instruction which does not write to a port.

There are two more bus control signaIs produced by the8X300, Left Bank select (LB*) and Right Bank select (RB*).However, due to the implementation of the Fast 10 Selectlogic, only RB*, which is used as the chief enable signalfor U17 and U18, is needed.

Reset Circuit

The 8X300 is held reset for approximately 40 millisecondsafter initial power-on. This is accomplished by an RCnetwork (R42 and C52). After this power-up sequence, thereare two ways to reset the processor, both of which arecontrolled by the host computer.

One method of resetting the processor is by resetting of thehost (i.e., reset switch) which drives the signal HDMR* low.The other method of resetting the processor is by softwarecontrol. This is accomplished by setting bit D4 of port ClHEX. This latches the signal (SFTRESET) which in turntriggers a one-shot U76 to drive RESET* low. The one-shotduration is set for approximately 100 u sec pulse width.RESET* is used to clear the drive control latches U62 andU52 and the host interface WAIT* (U43).

Processor Power Supply

Power is supplied to the 8X300 from the +5 volt (Vcc) powerbus. Due to the internaI operation of the 8X300, an on-chip

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5-Meg Hard Disk

--------------- '~CI!;;~-f3[:l ®

Service Manual

voltage reference is provided to produce bias to an externalpass transistor (Q2) which drops Vcc to the 8X300 toapproximately +3 volts. AlI signaIs into and out of the8X300 are internally level shifted to be TTL compatible.

Read and Write Ports

Throughout the circuit, output ports are formed by UlD UI typelatches using write strobes (WRO -WR7) to latch data intothe ports. Reading of ports is universally accomplished byusing read strobes (RDa, RD2, RD4 - RD6) that enableselected tri-state output devices on the lia bus.Additionally, two read strobes are used to clock the hostDRQ* and INTRQ* latches (U5) and one read strobe is leftunused as a UldummyUl port for glitch-free operation of theFast la port decoders.

Read/write Memory

Since the 8X300 does not permit data to be saved orretrieved from dedicated program storage, RAM must beinstalled on the la bus. RAM must be accessed just likeother port accesses via the ra bus by ra instructions. Toprovide for addressing the RAM, three latch/counters (U26,U27, U28) are connected to the ra bus to receive and storeaddresses required to access the RAM (U17,U18).

RAM Addressing

The RAM address bus (RAO - RA9) uniquely addresses one of1024 memory locations. As each counter chip reaches a countof 0, it will set a borrow condition to the next highercounter which will be decremented at the end of the nextaccess to RAM. When aIl bits of the address have been reset,the ROVF* bit on the last counter (U26) will be reset,providing overflow status which can be read by the processoron (U26). By setting v~rious beginning address values, ROVF*can be used to mark the end of any RAM access loop from 1 to1024 bytes in length. The controller board uses thisfunction to set sector buffer lengths of 128, 256, or 512bytes.

Sector Buffering

AlI data read from or written to the disk is passed throughthe RAM to provide buffering required for asynchronous datatransfer between the host and disk. The counters arepost-decremented, which means that the effective addressesare stable to the RAM by at least the instruction prior to

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--------------------- 'rlCl!;;~... i3[:l ® --------------

the actual access. This pre-selection feature effectivelyreduces Rfu~ access time to the output enable and propagationtime of the RAM for read operations. This feature alsoreduces the width of the minimum WR* strobe pulse for writeoperations.

RAM Accessing

RAM access is initiated by RCS* which is the logical or (byU59) of RDO* and WRO* which are generated by the Fast IDdecoders (U44 and U45). Data to bel read from RAM will beplaced on the ID bus whenever RCS* is low and WC* is high.Data is written into a selected RAM cell on the trailingedge of WC* if RCS* is low. During writes, both WC* and RCS*will be low for at least 120 nanoseconds so that data setuptime requirements are met.

Scratchpad Operations

Because the RAM address counters can be pre-set, directreads and writes to a specifie address are possible. Thisfunction is used for scratchpad storage during programexecution. This mode of RAM access requires two or threeinstruction cycles for each random access to the RAM asopposed to one for sequential access using thepost-decrement feature.

MAC Control Port

Basic control of the various functional sections of thecontrol1er is accomplished by a dedicated 6-bit control portcalled MAC CNTRL (U29). MAC CNTRL enables CRC generation(CRCIZ*), functions of the WAIT control circuitry (WAEN*),gating of read or write functions (WRITE*), control of CRCcheck word output (lBLA*), and AM detection (SRCH). MACCNTRL output states are latched into the port by a writestrobe (WR7). Additionally, any time MAC CNTRL is loadedwith a new byte, the lower two data bits (100 and 101) arestrobed into the upper two address counter/latch bits (RASand RA9). AlI remaining ports are distributed among thebasic functional sections of the controller and will bedescribed in detail within the discussion of thosefunctions.

SeriaI Data Separation

The controller board contains circuitry which processesincoming MFM data from the drive by a method called data

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5-Meg Hard Disk®

Service Manual

separation. Here, sorne background information may behelpful:

In order to provide maximum data recording densityand therefore maximum storage efficiency, data isrecorded on the disk using a Modified FrequencyModulation (MFM) technique. This technique requiresclock bits to be recorded only when two successive databits are missing in the seriaI data stream. Thisreduces the total number of bits required to recorda given amount of information on the disk. This resultsin an effective doubling of the amount of the datacapacity, hence the term "double density."

Because clock bits are not recorded with every data bitcell, circuitry that can remain in sync with data during theabsence of clock bits is required. Synchronous decoding ofMFM data streams requires the decoder circuitry tosynthesize clock bits when they are present. This isaccompli shed by using a phase-locked oscillator employing anerror amplifier/filter to sync ante and hold a specifiephase relationship at the data and clock bits in the datastream. The synthesized clock called RCLK can then be usedto separate data bits from clock bits and to shift theresultant seriaI data into registers for parallelizationinto bytes.

Incoming Data Selection

SeriaI data is input from up to four radially connecteddrives via a quad RS-422 differential receiver (U54). Thereceiver converts differential input data to TTL levels foruse by the controller. The data from the selected drive isthen routed to gate (U53). At this point, data and clocksare still combined and appear as 50 nanoseconds (nominal)active high pulses spaced at intervals of one, one and ahalf, or two times the RCLK periode This data is presentedto the input of another AND/OR/INVERT gate (U4) which willgate either MFM data or a reference clock into the firststage of the VCO error amplifier circuitry.

Reference Clock

The reference clock is derived from the write clock crystaloscillator (QI, UlO, and associated circuitry). Thisoscillator uses a fundamental cut crystal to oscillate atfour times the RCLK frequency. The 4X output is then dividedby UlO to produce both a 2X clock (2XDR*), which is used asa reference, and a IX clock (WCLK) which is used to produce

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®_-------------MFM write data for the disk. The crystal (YI) frequency is20.000 MHz for compatible drives.

Clock Gating

The gating of the reference and MFM data into the dataseparator is dependent upon the condition of the Read Gatesignal (RGATE) and the spacing of the data on the seriaIstream after RGATE is brought true. Due to the techniqueswhich are empIoyed to separate data from clocks, it isnecessary to run the VCO at a rate twice the data clock(RCLK) rate. The VCO is therefore set to an open-Ioopfrequency of 2 times RCLK. Any variations in this rate dueto variations in disk rotational speed must be compensatedfor by the VCO, but instantaneous shifts in data due to theeffects of adjacent bit cells on the disk and minor noisemust be ignored. AIso, the response of the VCO must beadjusted to effectively ride over missing clock bits whichoccur as a result of MFM recoding technique. The resultantcompromise between response and reject requirements of theVCO cause the VCO to have a tendency to become Iocked anteharmonics of the data rate rather easily. This is likely tooccur if the VCO is connected to a data stream over a fieldof data which has data bits spaced at one and a half or twotimes the actuai RCLK time intervals.

To provide protection against this undesirable condition,the VCO is always held Iocked ante a stable clock running attwo times the RCLK frequency whenever the controller is notactually reading data. Furthermore, great care is taken toswitch in read data to the VCO error detector only when itis known that the data stream frequency is equal to the RCLKfrequency. This can occur only when the data is a solidstream of aIl ones or aIl zeros.

High Frequency Detector

The switching function is initiated immediately after RGATEgoes true and will only switch read data into the VCO after16 consecutive ones or zeros (high frequency) are detectedby a one-shot (Ul) and counter (U2) connected directly tothe raw MFM data. The one-shot is adjusted for a pulse widthof one and one-fourth times the RCLK periode This is 250nanoseconds, +/- 10 ns. These adjustments of the DRUNone-shot (Ul) provide tolerances of up to one-fourth theRCLK period in jitter on the MFM data bits while still beingable to distinguish MFM zeros or ones from other datapatterns.

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5-Meg Hard Disk Service Manual® -------------_....

Each clock or data bit on the seriaI stream triggers theone-shot. If the time between successive triggers is lessthan the one-shot time constant, the one-shot remainsretriggered. As the one-shot is triggered by data streambits, so is the up/down counter (U2) whose count mode iscontrolled by the state of the one-shot outputs. While theone-shot is being retriggered, the counter counts up. Whenany data bit fails to reach the one-shot before its timeconstant is over, the one-shot resets and in turn clears thecounter. Only when 16 successive retriggers occur, can thecounter reach its terminal count. At this time, the counteroverflow goes true and sets the DRUN* latch output (U3, pin6) low which switches read data in and reference clock out.An AND-OR-INVERT gate (U4) performs the switching. DRUN* isread through (U74) by the aX300 to determine the conditionof the MFM data stream.

veo

The Hard Disk controller uses a single chip veo (U32) whichsimplifies circuitry and adjustments. The operating point ofthe veo is initially set by adjusting the variable capacitor(C33) for a 10 MHZ output at TP9 and the frequency controlvoltage input (TPa) to 2.5 V +/- .5 V. It should be notedhere that both of these adjustments are done using the sametrim cap (e33).

The output of the error amplifier and filter is fed to theveo and represents how far the veo frequency is from that ofthe incoming signal. The error signal, which is proportionalto the difference, allows the veo to shift from centerfrequency and become the same as the frequency of thefrequency of the input signal. When the loop is in lock, thedifference frequency component will be De and is passed bythe low pass filter.

Frequency control is actually a matter of frequency range.The difference component'may fall outside of the band edgeof the low-pass filter and be removed along with the SUffi

frequency component. If this is the case, then noinformation is transmitted around the loop and the veoremains at its initial free running frequency. As the inputfrequency approaches that of the veo, the frequency of thedifference component decreases and approaches the band edgeof the filter. Now part of this difference component ispassed which tends to drive the veo to the frequency of thedifference component more and allows more of it to be passedthrough the filter. This is a positive feedback, whichcauses the veo to snap into "lock" with the input signal.

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Service Manual

The term "capture range" can be described as the frequencyrange centered about the VCO free running frequency overwhich the loop can acquire lock with the incoming datasignal.

The free running frequency of the VCO is always twice thatof the RCLK rate. In fact, RCLK is produced by the VCOthrough a divide-by-two counter (U14).

Power for the VCO's internaI oscillator as weIl as for theerror amplification filter is supplied from a 78M05 +5 voltregulator. This insures good noise separation for thesestages from the power supply.

Error Amplifier

Control of the VCO is accomplished by the error amplifier,filter, and Data Separator chip. The error amplifier is abalanced current mirror whose output sources or sinkscurrent to the filter stage. Whenever the VCO is running tooslow, the error amplifier receives pulses from data bitsbefore pulses from the VCO clock. This causes the erroramplifier to produce pump-up pulses to the filter. Thefilter integrates these UP pulses and raises the overallvoltage of the voltage control input (TP8) to the VCo. Whenthe VCO is running too fast, the error amplifier producespump-down pulses to the filter. There will always be sorneerror present because without pulses of UP and DN the filterwould float causing the VCO to drift off center frequency.

Phase Detector

The circuitry which feeds the error amplifier is called thephase detector. This consists of several "D" latches (U20,U21) and a delay line (U31). The function of this circuit isto provide time windows during which the leading edges ofthe incoming MFM data can be compared to the leading edgesof the VCO clock. These windows are approximately 50nanoseconds in length and are initiated by the leading edgeof any data bit as it enters the detector. The windows areterminated by the same data bit, edge delayed by a net of 50nanoseconds (60 nanoseconds in the delay line minusapproximately la nanoseconds in propagation delays.) Whenboth the delayed data bit and the nearest VCO clock edgearrive at the detector, the detector is reset until the nextdata bit arrives on the MFM data stream. The delayed databit sets its half of the detector latches to produce the VP

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pulses. The VCO clock edge sets its half of the detector toproduce the DN pulse.

window Extension

Once the VCO has been locked cnte the phase of the incomingdata, the actual separation of data and clocks can occur.This is accompli shed by using a technique called windowextension. This technique causes data bits to first havetheir leading edges shifted into the center of the RCLK halfcycles then to have them latched or extended until the nextrising edge of the RCLK. The shift is accomplished bytapping the data of the Sample on Phase Detector delay lineat the 60 nanosecond tap, and inverting the VCO clock to theRCLK divider (U14). The delayed data clocks a pair oflatches (U12 and U13). The "data" latch has its "D" inputand CLEAR connected to RCLK* and the "clock" latch has its"D" input and CLEAR connected to RCLK*.

If an MFM data bit enters the latches while RCLK is high, itwill be extended as a data bit. If RCLK* is high, it will beextended as a clock bit. Due to this extension technique,bits can jitter approximately one-fourth the RCLK periodwithout being lost. The output of each latch is then furtherextended by being fed directly into the second half of thelatches and clocked on alternate edges of RCLK. The finaloutputs of the data extension/separation stage are twoseparate signals; one signal consists solely of NRZ(non-return to zero) data and the other of NRZ (non-returnto zero) clocks. The NRZ data and clocks are finally in aform suitable for processing by subsequent circuitry on theController board.

Clock Detection

Due to the nature of MFM data encoding, it is impossible toknow exactly if MFM bits are data or clocks. This ambiguityresults in having to create circuitry to assume that bits onRCLK* are actually data bits until the VCO is locked on anda unique data/clock pattern is detected. This isaccomplished by holding the VCO to RCLK divider (U14) resetuntil it is fairly certain that bits on the data stream areactually clocks belonging to a field of zero data.

Once this assessment has been made, the processor releasesthe AM detector (Ull) by raising the SRCH signal. Thissignal releases a latch (Ull) which will remove DHOLD fromthe RCLK divider (Ull) on the next rising edge of a MFM data

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®_-------------bit so that CLOCKS will be on the RCLK* phase and DATA willbe on the RCLK phaseo The processor makes its assessment ofthe state of the data stream solely on the occurrence of asignificant run of zeros which is detected by the one-shot(Ul) in the DRUN circuito Once released, the phase of RCLKvSo data and clocks will remain stable throughout the readof an ID field or data fieldo Whenever SRCH is dropped, thevco to RCLK divider is once again reset and no RCLKS areproducedo

Data Conversion and Checking

MFM data which has been separated to form NRZ data andclocks is processed through specialized circuitry to prepareit for parallel processing by the 8X3000 This processingconsists of three functional circuitso

1 0 AM detection (Ull)20 Serial-to-Parallel conversion (U9)30 CRC checking circuit (U6)

Each function will be discussed separately but bear in mindthat many interdependencies existo

AM Detection

As previously stated, it is impossible to know whetherseriaI data bits are actually data or clock bits by justlooking at the data streamo Furthermore, it is equallyimpossible to determine byte boundarieso The problem issolved by a uniquely recorded data/clock pattern called anAddress Mark (AM)o The AM consists of a data pattern of HEX'Al' with a missing clock pattern of HEX 'OA'o Normally adata byte of of HEX 'Al' requires a clocking pattern of HEX'OE'o In fact, due to the rules of MFM data encoding, analternating clock pattern such as HEX 'A' or HEX '5' cannotexist legallyo

The AM is used to uniquely identify the start of a field ofinformation (data or ID field) within each sectoro A longrun of zero data always precedes each AM on the disko Zeroshave a clock bit for every RCLKo When attempting to readinformation from the disk, the Controller first acquiresphase lock over a field of zeros o When this acquisition isachieved, the processor releases the AM detector (Ull) byraising the Search control line (SRCH) on the MAC CNTRL port(U29) 0

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~·"4Il::II11IL.I

Service Manual

Due to the circuitry associated with the VCO to RCLKdivider, the RDAT* output of the data separator (U13 - 8)will be high and the CLKS* output (U12 - 8) will be low.RCLK* will be the shifting clock for RDAT* and RCLK will bethe shifting clock for CLKS*. These four signaIs are routedinto the AM detector. Inside the AM detector, RDAT* isshifted into an 8-bit synchronous seriaI shift register andclocked on the falling edge of RCLK*. CLKS* is shifted intoa similar shi ft register on the falling edge of RCLK. Theoutput stage of the RDAT* register is dumped into an 'Al'comparator and the output stage of the CLKS* register isdumped into a 'OA D comparator. AM detection occurs when bothdetectors are true, thereby setting the AMDET* latch. At theinstant AM occurs, the exact relationship between data andclocks is known. It is also known that data is being clockedby RCLK* so CLKS* can actually be discarded; their purposewas in detecting AM. The AMDET* signal is used as asynchronization signal to start subsequent conversioncircuitry. The AMDET* signal remains true until theprocessor again de-asserts the Search control line.

SeriaI to Parallel Conversion

After.an AM has been detected, the serial-to-parallelconvertor (U9) takes over. NRZ data and RCLK are used toshift data bits into an 8-bit serial-to-parallel shiftregister. As each bit is shifted, a divide-by-8 countercircuit is incremented. After every eighth bit of data isshifted, the counter produces an overflow pulse marking byteboundaries in the seriaI data stream. The overflow bit fromthe counter resets the counter, clocks the data from theshift register into an 8-bit parallel Iatch, and sets atri-state flag register called BDONE. The flag can be readby the processo~ to see if any converted data is ready to beread from the latches.

When the processor sees BDONE in the true state, it servicesthe device by gating data onto the 10 bus using read strobe4 (RD4*) in conjunction with a tri-state buffer (U8). Theact of reading the latches also clears off the pending BDONEflag. As successive bytes are processed, the BDONE isserviced by the processor as data becomes available.

outputs from the serial-to-parallel device also includeSHFTCLK* and DOUT. SHFTCLK* is actually RCLK* propagatedthrough the device. DOUT is the Q output of the last stageof the shift register string. DOUT and SHFTCLK* are routedto the CRC generator checker device and also are tri-stated

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along with BDONE. These signaIs are active only when WRITE*is high which indicates a read mode of operation.

CRC Checking Circuit

Data recorded on magnetic media is prone to several types oferrors which could render data unusable if sorne form oferror detection were not employed. Therefore, a cyclicredundancy check (CRC) is performed on aIl data transfersfrom the disk. The CRC is an error detection code consistingof 16 additional bits which are appended to every ID fieldand data field on the disk. These bits are produced bydividing the data stream serially with a large polynomial.This division produces a unique l6-bit value for anyinformation passed through the CRC generator.

As data is being read from the disk, the CRC generator (06)re-computes the original CRC bits. The value in the CRCgenerator must always be zero after the last two bytes(which contain the orginal recorded CRC) are read. When thishappens, the data was correctly read and the controller willnot flag an error. If, however, the CRC generator is notzeroed after it has checked aIl bytes of the recorded data,the controller will flag the data as erroneous and enterinto a re-try condition. If the control1er cannot getcorrect data after attempting to read it 16 times, the readwill be aborted and the host informed that the data in thebuffer is questionable.

The Control1er board uses the same device to generate andcheck CRC's for data being written to or read from the disk.The polynomial used is:

16 12 5X + X + X + 1 (commonly called the CRC-CCITT

polynomial)

The processor polIs the condition of the DRON circuitryduring read operations. When DRON is true, it begins tosearch for an address mark. Once the AM is located, theprocessor will start to read paraI leI data which has beenconverted from NRZ data by the serial-to-parallel device.The processor will terminate this activity when it hasreceived the information it is looking for or if an error isdetected.

While the processor is reading the parallel data, the CRCgenerator is reconstructing the CRC check value. The CRCgenerator is initialized by the processor setting CRCIZ* low

----------Itadle/haell---------

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Service Manual

for at least 250 nanoseconds during the search for the AM.CRCIZ* is originated on the MAC CNTRL port (U29). Uponreceiving the CRCIZ* signal, the CRC generator/checker willpreset aIl 16 of its internaI polynomial division shiftregisters to logic ones and arm an internaI latch which willenable the checking function on the leading edge of thefirst non-zero data to enter the device. It should beremembered that prior to an AM there is always a field ofzeros (aIl data bits low) so the first non-zero data bitinto the device will always be the most significant bit ofthe AM (HEX Al).

The CRC device, when enabled by the first non-zero data bit,will shift succeeding data bits into a feedback shiftregister string with Exclusive or gates tied to the feedbacknodes on the first, fifth, twelfth, and sixteenth registers.As each RCLK occurs, the registers will divide the incomingdata and a unique pattern of ones and zeros will appearacross the registers.

When the last bit of an ID or data field is processed, thepattern in the registers should be equivalent to the 16 bitsappended to the fields during original recording. Theappended bits are also entered into the CRC device. If aIlof the bits in the appended field are identical to the bitsin the registers, then the Exclusive-or-Gates in theregister string will have flipped aIl of the ones to zerosand the CRC will have been satisfied.

The output of each register stage is tied to a 16-bitcomparator which goes true when aIl of its inputs are zeros.The output of the comparator is retimed to remove anydecoding slivers and is output as CRCOK. The processor canread CRCOK through U61 to see if a CRC error has occurred.

After the CRe bits are processed, the data stream willcontain at least one more byte of zeros. It is the nature ofthe CRC polynomial that if no bits are set to ones in theregisters and if a constant input of zeros is shifted intothe registers, no bits will be flipped. This provides aconvenient latching function for the CRCOK flag which willremain true for at least one byte after the last CRC checkbyte, giving the processor time to read the flag.

The data, clock, and BDONE are supplied to the CRC device ona 3-bit mini bus. During read operations, theserial-to-parallel device (U9) will be sourcing these linessince the WRITE control line from MAC CNTRL (U29) is lowandthis enables tri-state drivers on these lines. The

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-------------- TIQ!~œIB:['] ® --------------

Parallel-to-Serial device (U7) will have its tri-statedrivers disabled.

SeriaI Data Generation

The Control1er records data on the disk in MFM format. Inorder to produce the proper data format, the Controller usesseveral specialized devices to process the parallel datasupplied by the host into a seriaI MFM data stream. The datasupplied by the host is temporarily stored in the buffer RAMuntil the correct sector is located for the data to bewritten.

The process of writing is essentially the opposite ofreading except that the data separator circuitry is notrequired and the generation of the MFM data stream isproduced by synchronous clocking techniques.

The functional sections of the seriaI data generationsection are listed below:

1. Parallel-to-Serial conversion (U7)2. CRC generation (U6)3. MFM and precompensation (US)

Parallel to SeriaI Conversion

Parallel data is converted into a seriaI NRZ data stream bythe parallel-to-serial device (U7). The processor enablesthis conversion by lowering the WRITE* signal on MAC CNTRL(U29). WRITE* causes the tri-state buffers present on theparallel-to-serial device to become active, supplying theCRC device with data, clocks, and BDONE strobes.

The processor presents paraI leI data on the 10 bus alongwith the WR4* write strobe which latches the data into theparallel port on the BDONE. lnside the parallel-to-serialdevice, the paraI leI latches are loaded into a seriaI shi ftregister on every eighth WCLK transition. As the data istransferred to the shift registers, the BDONE status flag isset. The processor reads this flag through U61 to determinewhen to write the next paraI leI byte to the device. Thetiming of the parallel accesses is at a rate one-eighth thatthe bit rate of the NRZ data stream.

The output of the last register in the shift string isbrought out of the device as a NRZ seriaI data stream. Theshifting clock is also brought out as SHFTCLK to be used asthe clock for the CRC device.

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5-Meg Hard Disk Service Manual®_-------------Whenever it is desired to write a repetitive string ofidentical data bytes, the processor can simply ignore theBDONE flag and permit the device to reload the data from itslatches over and over again for as long as required togenerate the field. This feature of the device is used inwriting certain fields used in formatting.

CRC Generation

The CRC generator/checker (U6) is used to generate the CRCbits and to append them to the end of the data being writtento the disk. This is the complementary function to thatperformed during reads. The operation of the polynomialgenerator is identical to read operations except that at theend of the data field, the processor sets a signal whichcauses the device to output the computed CRC after the datainstead of reading the CRC and checking it.

The initial state of the shift registers within the deviceis forced to aIl ones by the processor pulsing CRCIZ* forapproximately 250 nanoseconds while the parallel-to-serialdevice is outputting aIl zeros on the NRZ data line. At thattime, a latch is set which holds the registers at ones untilthe "first non-zero bit enters the device. The first non-zerobit will be the MSB of the AM (HEX Al) of the data field tobe written. When the processor decides that enough zeroshave been written to satisfy the sync field requirements, itwill store a REX Al in the parallel-to-serial device. At theproper time (in sync with BDONE) the parallel-to-serialdevice will begin to send the MSB of the AM to the CRCdevice. This will start the CRC polynomial generator and theCRC will be computed.

As the processor writes the last byte of data to theparallel-to-serial device, it will drop the IBLA* (1 ByteLook Ahead) signal on MAC CNTRL port (U29). This signal willcause the CRC generator (U6) to begin dumping the computedCRC onto the NRZ data stream at the conclusion of the lastdata byte (synchronized with the BDONE signal). In thisfashion, the device is able to append the proper CRCinformation to the end of a field of data. IBLA* ismaintained at a low state for the duration of the unloadingprocess which lasts for 16 bit times.

During the unloading process, the CRC registers back-fillwith zeros. This feature is handy because by leaving IBLA*10Wi for additional time, zeros will always be written afterthe CRC which is a requirement for the proper operation of

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the CRC device during read operations. The NRZ data with CRCappended is then sent to the MFM generator device (US).

MFM Generation

The conversion from NRZ write data to MFM write data takesplace in the MFM/Precompensation device (US). This deviceaccepts NRZ data and a complimentary WCLK and produces MFMdata and clocks by sending the data through circuitry whichdecides when and where to write clocks on the data streamunder the MFM encoding rules. The proper encoding of thedata into MFM requires the device to apply three rules tothe data.

1. If the current data cell contains a data bit, noclock bit will be generated.

2. If the previous data cell contained a data bit, noclock bit will be generated.

3. If the previous data cell and the present data cellare vacant, a clock bit will be produced in thecurrent clock celle

The terms "data cell" and "clock cell" are defined by thestate of WCLK. While WCLK is low, it is a data cell andwhile high, it is a clock celle It can be seen then thatboth clock and data cells are one-half the period of WCLK or100 nanoseconds. Also note that by the rules started above,a clock and data bit can never occur within the same WCLKperiod and legal spacings for bits can be one, one and ahalf, or two times the WCLK period only. The rules areimplemented within the device by shift registers that holdthe next two, last, and present data bits and combinationallogic. The state of WCLK is considered and the appropriatebit cells are filled and combined on the MFMW output line ofthe device. This line is subject to decoding slivers, so itis run through a re-timing latch (U16) to clean it up.

Write Precompensation

The MFM data stream is now totally compatible with therecording rules and may be sent to suitable line drivers fortransmission to the drive except for one modification. Dueto the decreasing radius on the physical surface of thedisk, the inside tracks have less circumference andtherefore exhibit an increase in recording flux density overthe outside tracks. This increase in flux density aggravatesa problem in magnetic recording known as dynamic bit shift.

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5-Meg Hard Disk Service Manual® --------------

Dynamic bit shift occurs as the result of one bit on thedisk (a flux reversaI) influencing an adjacent bit. Theeffect is to shift the leading edge of both bits closertogether or further apart than recorded. The net result isthat enough jitter is added to the data recorded on theinside tracks to make them harder to recover without error.In any event, there is a method called write precompensationwhich can be applied to reduce the effect of this shi ft onthe data.

Write precompensation is a way of predicting which directiona particular bit will be shifted and intentionally writingthat bit out of position in the opposite direction to theexpected shift. This is done by examining the next two databits, the last bits, and the present bits to be written andproducing three signaIs depending on what these bits are.The three signaIs are EARLY, LATE, and NOM. They are used inconjunction with a delay line to cause the leading edge of adata/clock bit to be written early, late, or on time. Aswith MFMW, these signaIs are subject to decoding slivers andmust be retimed by U16.

The processor can enable or disable the generation of thesesignaIs by controlling the RWC (Reduce write Current) linefrom U52. When RWC is high, precompensation is in effect.When RWC is low, no precompensation is generated and the NOMoutput of the device is held true.

The delay line, U3l, actually performs the precompensationwith the help of an AND-OR-INVERT gate (U37). The MFMWpulses are applied to the input of the delay line and,depending on which of the three precompensation signaIs ispresent, the U37 selects a different tap on the delay line.Nominal data is actually tapped from the second tap, earlydata from the first, and late data from the third. From U37,the MFMW data is sent to the input of a quad driver (U35 orU36) where it is converted to a differential form and thensent to the disk drive. The AND-OR-INVERT gate (U37) has oneother function. If the controller is not writing, the WGI(Write Gate InternaI) signal will be low. This is invertedby U19 and applied to the fourth section of U37. Thisresulting high input effectively inhibits the gate fromaccepting MFMW data.

Host Interface

The interface bus to the controller is pin-for-pincompatible with the standard Model III r/o port. This

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®_-------------includes an 8-bit bidirectional data bus (U70) and 8 addresslines (U71). For systems using interrupts and/or DMA, thecontroller also provides Interrupt Request (HDBINTRQ*) andData Request (HDBDRQ*).

Accessing the controller is like other 1/0 devices. Addressdecoding is done on the control1er board by U69. This decodecan be jumpered to recognize four different address ranges.Standard setting is jumpered from 17 to 19, which utilizesport locations CO to CF HEX. Further decoding to allowaccess of specific ports is done by U66, U67, and U68. Databus direction is determined by U56, using standard bus asweIl as decoded signaIs.

wait Enable

The generation of the WAIT* signal is controlled by a bit inthe MAC latch (U29) called Wait Enable (WAEN*). If thecontrol1er is ready to accept random access to its taskfile, WAEN* will be asserted. After WAEN* is clocked througha latch (U43) to insure WAIT* is not asserted during a busaccess in progress, DCRCS* (BIC or BaC in sorne applications)causes WAIT* to be asserted to the bus.

The WAIT* line is released on the trailing edge of any Reador Write Strobe to the communications latch, U60. Thisrelease is caused by the logical OR of RDG* and WRG* on U38which presets the wait latch, U43, to a non-wait requestcondition.

Interrupts and DRQ's

The controller produces INTRQ* to signal the end of aIl diskoperations and DRQ's to signal data ready to DMAcontrollers. INTRQ* and DRQ* originate on the MFM generator(U5) as an auxiliary function of that chip. The INTRQ*signal is set using INTCLK and the the DRQ signal is setusing DRQCLK, both of which are produced by U44. Interruptsare cleared by CSAC'* (a 200 nanosecond version of the CSACsignal) and AO, Al whenever the host reads the statusregister, issues a command or accesses the sector numberregister. Data requests (DRQ's) are cleared when the hostaccesses the data or cylinder low registers DRQ's will bereissued for each byte to be transferred. During power on orMaster Resets (MR*), INTRQ* is set and DRQ is reset.

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5-Meg Hard Disk ® Service Manual

8/ Troubleshooting the Power Supply (Secondary Drive Only)

Section l

Equipment for Test Set-Up

1. Isolation Transformer (minimum of 500 VA rating)-

***CAUTION***

Dangerously high voltages are present in this power supply.For the safety of the individual doing the testing, pleaseuse an isolation transformer. The 500 VA rating is needed tokeep the AC waveform from being clipped off at the peaks.These power supplies have peak charging capacitors and drawfull power at the peak of the AC waveforrn.

2. 0-140 Variable Transformer (Variac)-Used to vary input voltage. Recommend 10 Amp, 1.4 KVArating minimum.

3. Voltmeter-Needed to measure DC voltages to 50 VDC and AC voltagesto 200 VAC. Recommend two digital multimeters.

4. Oscilloscope-Need XIO and XIOO probes.

5. Load Board with Connectors-See Table l for values of loads required. The entry onthe table for Safe Load Power is the minimum powerratings for the load resistors used.

6. Ohmmeter

Set-Up Procedure

Set-up as shown in Figure 8. You will want to monitor thein~ut voltage and the out~ut voltage of the regulated bus,wh1ch is the +5 output, w1th DVM's. Also monitor the +5output with the oscilloscope using 50mv/div sensitivity. TheDVM monitoring the +5 output can also be used to check theother outputs. See text of Section III for test pointswithin power supply.

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--........--........---------........................- .,rCR~~ ...f;)[] ® ---........---------------..

POWER SUPPLV

+sv 1---_12V

ocOUTPUT

Figure 8. Test Set-up

Section II

Visual Inspection

Check power supply for any broken, burned, or obviouslydamaged components. Visually check fuse resistor, if anyquestion check with ohmmeter.

LOAD BOARD VALUES

SAFE MAX SAFE

OUTPUT MIN LOAD LOAD R LOAD POWER LOAD LOAD R LOAD POWER

+5 0.45A 11.11 ohm 5W 2.5A 20hm 25W

+12 1.3A 0.40 ohm 8W 2.02A 24.24 ohm 50W-12 0 0 0 0 120 ohm 2W

Table 1. Load Board Values

Start-up

Load power supply with minimum load as specified om Table 1.Bring power up slowly with Variable Transformer whilemonitoring +5 output with scope and DVM. Supply should startwith approximately 40-60 VAC applied and should regulatewhen 95 VAC is reached. If output has reached +5 volts, do a

---------rtadle/haell---------

- 48 -

5-Meg Hard Disk®

Service Manual

performance test as shown in Section IV. If there is nooutput, refer to Section III.

Section III

NO OUTPUT

A. Check Fusable ResistorIf fusable resistor is blown, replace it, but do notapply power until cause of failure is found.

B. Preliminary Check on Major Primary ComponentsCheck diode bridge (BRl), power transistor (T2), andcatch diode (D3) for shorted junctions. If anycomponent is founded shorted, replace it.

C. primary Check on Major Secondary Components.Using ohmmeter from output commmon to each output, withoutput loads disconnected, check for shorted rectifiersor capacitors. If +5 output is shorted, also checkcrowbar SCR (SCRl) and zener (Zl).

D. Check for B+Set power supply and attach XIOO scope probe ground toend of RIO nearest DBl. Slowly turn up power and checkfor B+ on end of R9 nearest mounting hole. with inputat 95 VAC, this point should be between 120-140 VDC. Ifthis is not correct, check BRI and if necessary, checkR2l, D2, and finally input capacitors C5 and CG.

E. Check Q2 WaveformsUsing XIOO probe on heatsink of Q2, check collectorwaveform. The collector of Q2 is the pin closest to thelarge capacitors C5 and CG. Transistor should beswitching, correct waveform is shown in Figure 12. Ifthis is not present, check for shorted junction on Q2.If OK check the base waveform. Base of Q2 is pin oftransistor nearest the edge of PCB. The correctwaveform is shown in Figure 12. If this waveform is notpresent, check L2, QI, and Dl, and secondary componentsQ3, D8, D9, DIO, and L3. If any of the semiconductorsare found shorted, or inductors open, replace them.

- 49 -

5 Hard Disk ® Service Manual

1- cft"--

~ llJ

50 V/DIV5psec/DIV

Input - 120VACLoads +5 @ 2A

+12 @ [email protected]

Figure 9. Q2 Collector Waveform

1.0 V/DIV5psec/DIV

Input and Loadssame as above.

"". 1

<il~JI

Figure 10. Q2 Base Waveform

Section IV

Performance Test

Each of these test conditions should be set-up and noted tobe within the limits.

Test Input +5 Load +12 Load ·12 Load VOL TAGE AND RIPPLE SPECIFICATION

1 95VAC Max Max Max OUTPUT MIN MAX NO LOAD R IPPLE

2 128VAC Max Max Max

3 120VAC Max Min Min ,5 475V 525V 50mV p.p

4 128VAC Min Min Min +12 1140V 1260V 150mV p.p

5 95VAC Min Min Min ·12 1100V 15.00V 150mV p.p

* Applies to resistive load only. Not under system operating

conditions.

®

- 50 -

5-Meg Hard Oisk Service MJ: anual

•

0-: :(S: : ..... U4• •

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Circuit Boards

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~ 111111I11I11I 1111111 • ••••••••••• o· 0 •••••••••••••••••

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111I 11111111II111 Il,.11111 ••• ....:. 1111111.11 • 11111II111I11111 ••• -111111••• •• • ••• • 0 ; ••

111111111111111 1IIIIIiftlII • '11111111'111 •• Il''11111 :::.. • •••• • • • •• •• ••• •• .:•• ::: @

@ 1IIIIIIIIJIlllI 111111111 1 ••• •• • • :. ••• tllllll •• :1• • ••• • ~ • •• N

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5-Meg Hard Disk

-----------TRs..ao ®

10/ Wiring Diagrams

Service Manual

BLAC!', 5'

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BPlOYV/J rj

~GF!,EEIJl»'~CHl>5SI',)GPDUUD MAP # 350981-f,

AlAP#,3-350615-e .18'i'(F"A5TOO8E.AU '7lDOO SERIES

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WHITE 5'

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Il.LI'-c.K 1"

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WI-\I1E 7"

AC Wiring Harness (SecondarY/Slave>

ftadle/ha

53

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5-Meg Hard Disk

131eH1Da

®Service Manual

ALL 15'

AUP 1-480 4ê4 -O-HOU5IU6CE U5E.DI101314-4 PIUS(8USED)

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4L.L. WIPlE lB 64. STFlAUDE.DUl.. TYPE 40(,,0 ac.EPTRED WIP.ES WiJlCII ARE.ICO GA

DC Power Harness (primary/Master>

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_5.....-.....M.....e...g_H...a.....r_d.........D...i .....s.....k......... TRS-SO ® Service Manual

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DC Power Harness (Secondary/Slave)

.arr.,~~~i~AR~PNb'~~'~~2~ie HO~I~" (I)

Oe-'~'Oll" PlN:,t (0})

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l'IadleIhaell---------

55

5-Meg Hard Disk

CABLE '1t 1PIN 1, BlUE /0PIN Z, N;tPIN J, or(ANGE 14PIN 4 BROWN /5

effilE "fMOLEX

®Service Manual

CABLL "'2PIN 1, BLACK 2.0' LGPIN 2., YELJ..DN

~:~ l', ~~,~EJPIN 5, N/CPIN G, RED

2S

LED Driver Board Harness (Secondary)

----------ltadI8/haell-----------

- 56 -


------------- TI:I~;...~B[:J ® -------------

11/ Parts Lists

PROOUCT DESCRIPTIONHARD DISK 5 1/4"CAT. NO .. 26-1130

QTY DESCRIPTION PART NUMBER

1111111111

1111111

1111l444

36112222

MANUAL, START-UPREFERENCE, MANUALADDENDUMBINDER, MANUALSPLINE, INSERTDISKETTE, SYS1EM 5M F/ADISKETTE, BOOT 5M F/AHOLDER, VINYL 5 1/4 DISKETTECARO, SOFTWARE REGMANUAL ASSY

LABEL, TOP H.D. CONNCORD, 8' POWER*CABLE, EXTBAG, 4 1/2 X 4 X 2 MIL(KEY)BOX, ACCESSORIESLABEL, ACCESSORYKIT, ACCESSORY HDM

CASE, BOTTOM*PLUG, 2 1/2" DIA.LABEL, FCC PART 15LABEL, FCC ID HDMLABEL, SiN 26-1130FOOTWASHER, 1/2 0.0FASTENER, #10 X 1/2"*

PLATE, COVERSCREW, #4X1/4 PPHCABLE, INT. CNTRLCABLE, INT.CNTRLRSCREW, #6 X 5/16SCREW, #4-40 X 3/4"PPHNUlr, LOCK # 4-40WASHER, STAR #4

8749389874939487591918754082878978588966218896907871908287591778896613

8789613870905787093418590056876916487898178896612

87291248729148878928787897728789775859012385890748569062

87291478569120870933087093318569130856905985790038589075

---------- rtadlft ell------.............- ........................

- 57 -

5-Meg Hard Disk Service Manua1®_------------1122

121

l1111

112441

HARNESS, AC MSTRSCREW, #6-32 X 1/4 (GRD)SCREW, #4-40 X 1/2"PPHNUT, LOCK #4-40

FAN, COOLING*TAB, FASTONFAN, 5M S/A

BEZEL, SWITCH*SWITCH, KEYLOCK*SWITCH, ON/OFF*INDICATOR LIGHT*BEZEL ASSY

DRIVE, 5 1/4 HARDHARNESS, LAMPMOUNT, DRIVEWASHER, LOCK #6SCREW, #6-32 X 1/4 PPHDRIVE, S/A

8709332856909885690338579003

879040185290088896620

87192308489047848904884690098896610

879020287093478729131858901885690988896609

1 FILTER 87390104 NUT,LOCK #6-32 85790044 SCREW, #6-32 X 2 F .. CNTSK 85691552 SCREW, #6-32 X 1/2 85691262 SCREW, #6-32 X 1/4 THD FM 85690404 SCREW #6-32 X 1/4"PPH 85690984 WASHER, #6 8589018

27

121

11

11

11

111

CLIP, CORD .. 38" DIA ..TUBING 1/8DX1/2

PCB ASSY, CONTROLLER*IC P2114 U17, U18IC, 8X300 'MICRO-CONT

IC 28s86 BPROMIC 28s86 BPROM (U34)PRGMD

IC, 28s86 BPROMIC, 28S86 BPROM (U40)PRGMD

IC, 28S86 BPROMIC, 28S86 BPROM (U41)PRGMD

IC, WD 1100-01 (U9)IC, WD 1100-12 (U5)IC, WD 1100-03 (U11)

85590108539025

889613080421148040300

80400868896603

80400868896602

80400868896604

804011180411128040113

--------- ftadlo/h®

- 58 -

5-Meg Hard Disk Service Manual® -------------

11111111

111442151

144111

IC, WD 1100-04 (U6)IC, WD 1100-05 (U7)LABEL, CONTROL SiNASSEMBLYVISUALTESTINGREPAIRPCB, CONTROLLER 5M F/A

SHIELD, POWER SUPPLY*INSULATORPOWER, SUPPLYSCREW, #6-32 X 1/4"PPHWASHER, LOCKSCREW, #10 X 1/4"PHWASHER, .141 IDX .167 ODSCREW, #6-32X3/8"PPHSHIELD, PCB S/A

HARNESS DC MSTRSCREW, #6-32Xl/4 PPHWASHER, #6 LOCKMAP, MEDIA ERRORHOLDER, PLASTIC MAPCABLE, INT. DATA MSTR

80401148040115878973288966008896600889660088966008896600

872913285390268790043856909885890188569153858907285690038896608

870933485690988589018875913185901098709324

1 COVER, TOP 87291232 CLIP, GRD. 85590405 SCREW, #8-32X3/8" 85691075 WASHER, #8 FLAT 8589027

1 LOGO STRIP* 87192211 BEZEL* 87192091 COVER, TOP S/A 8898403

3

111

1

1

SCREW, #6-32X3/8" PPH

LABEL, WARRANTY NOT.BAG 6X15X22LABEL, LINE TERMINATOR

CARTON, 5M HDM F/A

MANUAL, SERVICE

8569026

878909085901248789597

8896616

8749403

PRODUCT DESCRIPTION -- MODEL l HARD DISK ADAPTER

----------- rladlft ell----------

- 59 -

5-Meg Hard Disk

QTY DESCRIPTION

Service Manual® -------------

PART NUMBER

1 PCB M l HD ADAPTER2 RESISTOR lK OHM 1/4 WATT 5%2 TRANSISTOR 2N2222

889650382072108110222

11

2211

1111211

1111111

CABLE, M l HDPC BOARD Ml ADPTR W/CABLE

TAPE, FOAM 1/4XIXIENCLOSURELABEL, ADAPTERADAPTER F/A

SUPPLEMENT, MODEL lDISKETTE, INTLATN SYS. S/ADISKETTE, XTRA S/ADISKETTE, OPRTR SYS S/AFOAMFOAM,DIE CUT 26-1132CARTON, INDIVIDUAL

CABLE, EXT. DATA 20POS.CABLE, EXT. CNTRL 34POS.CORD, 8 1 POWER*CABLE, INT. DATA 20 POSBOX, ACCESSORIESLABEL, ACCESSORYKIT, ACCESSORY HDS

87090218896650

8690002871902787898108898428

8749411889665388966528896651877903187791188769172

8709252870932987090578709326876916487898208896904

PRODUCT DESCRIPTION5 1/4" HARD DISKCAT. NO. 26-1131

111444111

11222

CASE BOTTOM*LABEL, FCC PART 15LABEL, FCC ID HDSFOOTFASTENER, 110 X 1/2"WASHER, 1/2 O.D.LABEL, SiN 26-1131PLUG, 2 1/2" DIA.OPOI0 5M HDS

CABLE, INT CNTRLRCABLE, INT. CNTRL/SLVSCREW, 16 X 5/16 BRICO IND.SCREW, 14-40X3/4 PPHNUT,14-40 KEPS LOCK

872912987892878789773859012385690628589074878978387291488896901

87093258709328856913085690598579003

---------Itadle/haell---------

- 60 -


-----------TRS-SO ® -----------

21

121

4141221

11111

11422221

271

1112441

WASHER, #4 STAROP020 5M HDS

FAN, COOLINGTAB, FASTONFAN, 5M S/A

SCREW, #6-32 X 2" FCNTRFILTERNUT, #6-32 LOCK*HARNESS, AC SLVSCREW, #4-40 X 1/2"PPHNUT, LOCK #4-40OP030 5M HDS

BEZEL, 8WITCH*INDICATOR, PWR ONSWITCH, ON/OFF*INDICATOR LIGHT*BEZEL ASSY

HARNESS DC ASSYRELAY, 12V 70MASCREW, #6-32 X 1/2SCREW, #6-32 X 1/4SCREW, #6-32 X 1/4 THD FMWASHER #6 LOCKSCREW, #6-32 X 3/8OP040 5M HDS

CLIP CORD .38 DIA.TUBING 1/8 DIA. X 1/2OP050 5M HDS SOLDER

DRIVE, 5 1/4 HARDHARNESS, LED DRIVERHARNESS, RELAYMOUNT, DRIVEWASHER, #6 LOCKSCREW, #6-32 X 1/4 PPHDRIVE, 5M HDS S/A

85890758896900

879040185290088896620

8569155873901085790048709333856903385790038896902

87192308469011848904884690098896611

87093358429104856912685690988569040858901885690268896905

855901085390258896906

8790202870934887093558729131858901885690988896909

1 POWER SUPPLY 87900259 SCREW. #6-32 X 1/4 PPH 85690989 WASHER, #6 LOCK 85890181 SCREW, #6-32Xl PPH ZINC 85691592 NUT, #6-32 KEPS 85790041 PCB DRIVER F/A 5M 88966151 MAP, MEDIA ERROR 8759131

---------Itadle/haell---------

- 61 -

5-Meg Hard oisk Service Manua1

------------- '1..g!~-8l0 ® ------------

1111

HOLDER, PLASTIC MAPOP060 5M HOSOP075 TESTING 5MOP085 BURN-IN 5M

8590109889690888969088896908

1 COVER, TOP 87291232 CLIP, GRD .. 85590403 SCREW, #6-32 X 3/8 PPH 85690265 SCREW, #8-32 X 3/8 85691075 WASHER, # 8 FLA'r 85890271 LOGO, STRIP 87192211 BEZEL 87192091 OP090 5M HOS 88969101 OP095 Q.C. 5M HOS 88969101 OP105 Q.A. 5M HOS 8896910

111

LABEL, WARRANTY NOT.BAG, 6X15X22LABEL, LINE TERMINATOR

878909085901248789597

1 CARTON, SECONOARY.. 005 COMPONENT A.005 COMPONENT B.005 FILM, p-180 PACKAGING1 CARTON, 5M HOS FIA

87691668669001866900286590148896903

----------Itadle/haell---------

- 62 -

Service ManualD' k ® ___....:S_-......M_eg_H_a......r_d__.lS TRs-ao

11/ Schematics

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POWER SUPPLY SCHEMATIC DIAGRAM

--------ftadle/llaell--------

- 63 -


-----------TRS-SO ® -----------

----------rtadle/haell----------

- 64 -

DATE APPROVEO

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-----------TRS-aO ® ---------------

13/Supplement

This supplement to the Hard Disk Drive Service Manualwas reproduced by permission of:

Tandon20320 Prairie StreetChatworth, CA 91311

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CUSTOM MANUfACTURED IN U.S.A. BV RADIO SHACK, … · 5-Meg Hard Disk ®_-----Service Manual Ripple Voltages +5 12V-12V Efficiency 65 50 150 150 mV mV mV % Over-voltage Protection