Proceedings of the

IEEE 1988

CUSTOM INTEGRATED CIRCUITS

CONFERENCE

universitAtsbibliothekHANNOVEK

TI*CMN!PCHFINFQRMAriONtJDiaLIOTHEK

Rochester Plaza May 16-19, 1988

Holiday Inn-Genesee Plaza

Rochester Riverside Convention Center

Rochester, New York

The CICC '88 is sponsored by the IEEE Electron Devices Society, the IEEE Solid-State Circuits

Council, and co-sponsored by the IEEE Rochester Section. Its aim is to bring together designers,producers and users of custom ICs to discuss recent developments and future directions in custom

integrated circuits.

88CH2584-1

CONTENTS

MONDAY EVENING Ballroom—Rochester Plaza Session 1 PAPER

7:00 NEWPRODUCT ANNOUNCEMENTS

Chairman: L Fuller

Co-Chairman: R.A. Milano

TUESDAY MORNING Holiday Hall—Holiday Inn Session 2 PAPER

8:30 WELCOME/OPENING REMARKS

D. Bryant, General Chairman

R. Milano, Conference Chairman

8:50 CICC'88-TECHNICAL PROGRAM

M. Hartranft, Technical Program Chairman

9:00 KEYNOTE ADDRESS

"From Childhood to Adolescence—The ASIC Industry Comes of Age"D. Fairbairn

VLSI Technology

VLSI DESIGN ENVIRONMENTS & SYNTHESIS

Chairman: S. N. Stevens

Co-Chairman: R. T. Jerdonek

9:45 A Highly Automated Design System for Rapid Product Development from Architecture to ASICs 2.1

D.A. Pierce, C.E. Stroud, AT&T Bell Labs, Naperville, IL

10:10 A Hierarchial Cell Based Engineering System for the Design of Semi-Custom Analog IntegratedCircuits 2.2

M. Gerbershagen, S. Huss, M. Laage, I. Rublen, AEG Aktiengesellschaft, Ulm, West Germany

10:35 Constraint Propagation and Design Interactions in an Object-Oriented IC Design Environment 2.3

T.A. Ly, E.F. Girczyc, University of Alberta, Edmonton, Canada

11:00 Integration of Algorithmic VLSI Synthesis with Testability Incorporation 2.4

C.H. Gebotys, M.I. Elmasry, University of Waterloo, Waterloo, Canada

11:25 Boolean Decomposition of Programmable Logic Arrays 2.5

S. Devadas, A.R. Wang, A.R. Newton, A. Sangiovanni-Vincentelli, University of California, Berkeley, CA

11:50 Bridge: A Behavioral Synthesis System for VLSI 2.6

C-J. Tseng, R-S. Wei, S.G. Rottweiler, M.M. Tong, A.K. Bose, AT&T Bell Laboratories, Murray Hill, NJ

TUESDAY MORNING 101 Meeting Rooms—Convention Center Session 3 PAPER

ADVANCES IN SIMULATION METHODS & TOOLS

Chairman: G.W. Ledenbach

Co-Chairman: J. Barnes

9:45 A Knowledge-Based SPICE Environment for Improved Convergence and User Friendliness 3.1

T.M. Kelessoglou, D.O. Pederson, Univ. of California, Berkeley, CA

10:10 ADOPT-ACAD System for Analog Circuit Design 3.2

J.C. Lai*, J.S. Kueng, H.J. Chen*, F.J. Fernandez**, Honeywell, Plymouth, MN*, Universityof Minnesota,

Minneapolis, MN**

10:35 Automatic Generation of Behavioral Simulation Models Using Functional Abstraction 3.3

K.M. Alexander*, R.S. Kirk*, R.H. Lathrop**, R.J. Hall**, G. Duffy***, Gould SCD, Santa Clara, CA*, MIT,Cambridge, MA**, University of Texas, Austin, TX***

11:00 Evaluation of Macro Models for Mixed Analog/Digital Circuits 3.4

R. Sparkes, G. Boyle, R. Woolhiser, Tektronix, Beaverton, OR

11:25 A Mixed-Mode Analog-Digital Simulation Methodology for Full Custom Designs 3.5

E.S. Lee, T-F. Fang, AT&T Bell Labs, Murray Hill, NJ

CONTENTS

TUESDAY MORNING Lilac Ballroom North—Convention Center Session 4 PAPER

APPLICATION SPECIFIC MEMORIES

Chairman: K. Venkateswaran

Co-Chairman: K.Au

9:45 A Wide Operating Voltage Range and Low Power Coinsumption EPROM Structure for Consumer

Oriented ASIC ApplicationsT. Maruyama, Y. Kawamura, N. Kitagawa, K. Shinada, N. Hanada, Y. Suzuki, Toshiba Corp., Kawasaki, Japan

10:10 Configurable EEPROMsfor ASICs

B. Carney, E. Lucero, R. Mendel, H. Reiter, National SemiconductorCorp., SantaClara, CA

10:35 Transparent-Refresh DRAM (TReD) using Dual-Port DRAM Cell

T. Sakurai, K. Nogami, K. Sawada, T. lizuka, Toshiba Corp., Kawasaki, Japan

11:00 An Experimental 2-Bit/Cell Storage Dram for MACRO Cell or Memory-on-Logic ApplicationT. Furuyama*, T. Ohsawa*, Y. Nagahama**, H. Tanaka*, Y. Watanabe*, T. Kimura**, K. Muraoka*, K. Natori*,Toshiba Corp., Kawasaki, Japan*, Toshiba Microcomputer Engineering Corp., Kawasaki, Japan

11:25 A185K x 16 Field Memory forTV/VTR Pictures

Y. Murakami, T. Imai, K. Inoue, K. Hattori, Y. Matsuura, M. Hayashi, K. Miki, Y. Torimaru, Sharp Corp., Tenri-City,Japan

11:50 An 8 Bit Microcomputer with Analog Subsystems for Implantable Biomedical ApplicationsL.J. Stotts, K.R. Infinger, Intermedics, Inc., Freeport.TX

12:15 LATE PAPER

A 4nsec. 4Kx2lbit Two-Port BiCMOSSRAM

T.S. Yang, M, Horowitz, B.A. Wooley, Stanford University, Stanford, CA

4.1

4.2

4.3

4.4

4.5

4.6

4.7

TUESDAY MORNING Lilac Ballroom South—Convention Center Session 5 PAPER

DRIVERS & INTERFACES

Chairman: J.C. Tandon

Co-Chairman: W.A. Vincent

9:45 1.7 Gb/sNMOS Laser Driver

K.R. Shastri*, K.N. Wong**, K.A. Yanushefski*, AT&T Bell Labs, Allentown, PA*, AT&T Bell Labs, Murray Hill, NJ**

10:10 A Smart BiCMOS Driver for 400 DPI Therman Printing Heads

K. Tsubone, T. Osumi, T. Ishizaki, M. Shinohara, M. Suzuki, K. Matsumi, K. Akahane, OKI Electric Industry, Co.,

Tokyo, Japan

10:35 High Frequency Oscillations in High-Pin Count ECL Devices

L. Gal, Unysis Corporation, San Diego, CA

11:00 Negative Feedback Influence on Simultaneously Switching CMOS OutputsR. Senthinathan, G. Tubbs, M. Schuelein, Intel Corp., Chandler, AZ

11:25 Controlled Slew Rate Output Buffer

K. Leung, Gould Semiconductor, Pocatello, ID

11:50 LATE PAPER

A Fast Offset-Free Sample-and-Hold Circuit

F.J. Wang, G.C.Temes, University of California, Los Angeles, CA

12:05 LATE PAPER

All MDS On-Chip Power Supply ConversionM. Paul*, R. Kraus*, K. Hoffman*, J. Harter**, Bundeswehr University, Munich, West Germany*, Siemens

Semiconductor Corp. Div., Munich, West Germany**

5.1

5.2

5.3

5.4

5.5

5.6

5.7

CONTENTS

TUESDAYAFTERNOON Holiday Hall—Holiday Inn Session 6 PAPER

CIRCUITS LOGIC SIMULATION

Chairman: R. Saleh

Co-Chairman: L. Bashaw

1:35 INVITED TUTORIAL

Finding the Steady-State Response of Analog and Microwave Circuits

K. Kundertand A. Sangiovanni-Vincentelli, MIT, Cambridge, MA

2:25 A Mixed FrequencyTime Approach for Findingthe Steady-State Solution of Clocked AnalogCircuits

K. Kundert*, A. Sangiovanni-Vincentelli*, J. White**, University of California, Berkeley, CA*, MIT, Cambridge, MA

2:50 Mixed-Mode Simulation Tools for Custom VLSI Designs

R. Salama, W. Liu, R.S. Gyurcsik, North Carolina State University, Raleigh, NC

3:15 Simulation of Mixed Analog/Digital Circuits in Time-Domain by PWL Macromodel ApproachX. Wang, J. Hu, Beijing University of Posts and Telecom, Beijing, China

3:40 Parallel Electronic Circuit Simulation on iPSC® SystemC-P. Yuan*, R. Lucas**, P. Chan*, R. Dutton**, Intel Co, Santa Clara, CA*, Stanford Univ., Stanford, CA**

4:05 ADMIT-ADVICE Modeling Interface Tool

S. Liu, K.C. Hsu, P. Subramaniam, AT&T Bell Laboratories, Murray Hill, NJ

4:30 RC Trees Revisited

M.A. Cirit, Silicon Compiler Systems, Liberty Corner, NJ

6.1

6.2

6.3

6.4

6.5

6.6

6.7

TUESDAYAFTERNOON 101 Meeting Rooms—Convention Center Session 7 PAPER

LAYOUT ANALYSIS & GENERATION

Chairman: H-F. Law

Co-Chairman: C. Anagnostopoulos

2:00 Floorplanning of Hierarchial Layout in ASIC Environment

H. Modarres, S. Raam, J. Lai, LSI Logic Corp, Milpitas, CA

2:25 Comparison of Floorplanning Algorithms for Full Custom ICs

H. Cai, J.J.A. Hegge, Delft University ofTechnology, Delft, The Netherlands

2:50 Symbolic Design Methodology for High-Density Macro-CellN. Matsumoto, Y. Watanabe, S. Mori, Toshiba Corp, Kawasaki, Japan

3:15 RISCE-A Reduced Instruction Set Circuit Extractorfor Hierarchial VLSI Layout Verification

Based on Interaction Rules

V. Henkel, U. Golze, Technical University of Braunschweig, Braunschweig, West Germany

3:40 SALIM: A LayoutGeneration Toolfor Analog ICs

M. Kayal, S. Piguet, M. Declercq, B. Hochet, Swiss Federal Institute ofTechnology, Lausanne, Switzerland

4:05 ILAC: An Automated Layout Tool for AnalogCMOS Circuits

J. Rijmenants, T. Schwarz, J. Litsios, R. Zinszner, CSEM, Neuchatel, Switzerland

7.1

7.2

7.3

7.4

7.5

7.6

CONTENTS

TUESDAYAFTERNOON Lilac Ballroom North—Convention Center Session 8 PAPER

MULTIDIMENSIONALSIGNAL PROCESSING

Chairman: L. ChristopherCo-Chairman: D. Brown

2:00 A VLSI Implementation of a Cellular Rotator Array 8.1

W.P. Burleson, L.L. Scharf, University ofColorado, Boulder, CO

2:25 A Video Rate 16x16 Discrete Cosine Transform IC 8.2

A.M. Gottlieb*, M.T. Sun**, T.C. Chen**, Bell Communications Research Inc., Morristown, NJ*, Bell Communica¬

tions Research Inc., Red Bank, NJ**

2:50 A 50 MIPS Multiprocessor Chipfor Image Processing 8.3

T. Denayer, E. Vanzieleghem, P.G.A. Jespers,Universite Catholique de Louvain, Louvain-ia-Neuve, Belgium

3:15 Design and Implementation of a Two Dimensional Fast FourierTransform Chip 8.4

W.T. Krakow*, W.E. Batchelor*, W-T. Liu**, T. Hildebrandt**, T. Hughes**, T-F. Yeh**, R. Salama**, G. Mei**,Microelectronics Center of NC, Research Triangle Park, NC*, North Carolina State University, Raleigh, NC**

3:40 The Architectures and Design of20 MHz Real-Time DSP Chip Set 8.5

P.A. Ruetz, P.H. Ang, LSI Logic Corp, Palo Alto, CA

4:05 Bit Map Control Processor (BCMP) Design 8.6

M. Sumi, N. Kai, S. Tanaka, T. Minagawa, I. Nagashima, Toshiba Corp, Kawasaki, Japan

4:30 A Custom DSP Chip to Implementa Robot Motion Controller 8.7

S.K. Azim, R.W. Brodersen, University of California, Berkeley, CA

4:55 LATE PAPER

A Reconfigurable 64-Tap Transversal Filter 8.8

CA. Stearns, D. Luthi, P. Ruetz, P. Ang, LSI Logic Corp, Palo Alto, CA

TUESDAYAFTERNOON Lilac Ballroom South—Convention Center Session 9 PAPER

DATAACQUISITION & PHASE-LOCKTECHNIQUES

Chairman: D.M.Lewis

Co-Chairman: D. Barber

2:00 1 GHz GaAs ADC Building Blocks 9.1

F. Thomas, M. Gloanec, P. Martin, S. Rugeri,J.M. Uro, F. Debrie, Thomson Hybrides & Microndes, Orsay, France

2:25 A CMOS 10Bit Accuracy and 5us Speed A/D Converter 9.2

T. lida, J. Gotch, A. Nishizuka, H. Hara, Toshiba Corp, Kawasaki, Japan

2:50 Multichannel Data Acquisition System with On-Chip Digital Signal Processing 9.3

S.E. Noujaim, J.A. Mallick, M. Wu, General Electric Co, Schenectady, NY

3:15 A Programmable Medical Data Acquisition System Chip 9.4

G. McGlinchey*, S. Pietkiewicz*, R. Frank*, P. Schmidt-Anderson**, F. Hansen**, Analog Devices, Cupertino,

CA*,S&W Medico TeknikA/S, Copenhagen, Denmark**

3:40 Jitter Attenuation Phase Locked Loop Using Switched Capacitor Controlled Crystal Oscillator 9.5

C-C. Shih, Y. Sun, Rockwell International, Newport Beach, CA

4:05 A 350 MHz Bipolar Monolithic Phase-Locked Loop 9-6

M. Soyuer, R.G. Meyer, University of California, Berkeley, CA

4:30 A PLL Based Clock and Data Recovery Circuit with High Input JitterTolerance 9.7

S.Y. Sun, Rockwell International, Newport Beach, CA

CONTENTS

WEDNESDAY MORNING Holiday Hall—Holiday Inn Session 10 PAPER

NEURAL NETWORKS& SPEECH RECOGNITION

Chairman: F.Yassa

Co-Chairman: D. Brown

8:20 INVITED TUTORIAL

Electronic Implementation of Neuromorphic SystemsJ. Raffel, MIT Lincoln Lab, Lexington, MA

9:10 A Programmable Analog Neural Network Chip

D.B. Schwartz, R.E. Howard, AT&T Bell Labs, Holmdel, NJ

9:35 A Self-Organizing Neural Net ChipJ. Mann, R. Lippmann, R. Berger, J. Raffel, MIT Lincoln Lab, Lexington, MA

10:00 A Digital Implementation of a Best Match Classifier

S. Mackie, J.S. Denker, AT&T Bell Labs, Holmdel, NJ

10:25 A Dynamic Programming Processorfor Speech RecognitionG. Quenot, J-L. Gauvain, J-J. Gangolf, J. Mariani, LIMSI-CNRS, Orsay, France

10:50 Speech Recognition Processors Using Fuzzy Pattern Matching

T. Ariyoshi, S. Kuriki, T. Kawamoto, S. Yasuda, RICOH Co, Ltc, Yokohama, Japan

11:15 LATE PAPER

A New Multialgorithm Multichannel, Cascadable Digital Filter Processor

J. Lin, K. Lewis, K. Lee, Fujitsu Microelectronics Inc., Santa Clara, CA

10.1

10.2

10.3

10.4

10.5

10.6

10.7

WEDNESDAY MORNING 101 Meeting Rooms—Convention Center Session 11 PAPER

AUTOMATICPLACEAND ROUTE

Chairman: D.DalyCo-Chairman: G. Buurma

8:45 Dense, Performance Directed, Auto Place and Route

M. Rose, M. Wiesel, D. Kirkpatrick, N. Nettleton, Intel, Santa Clara, CA

9:10 Building Block Routing - A Symbolic ApproachN-P. Chen, ECAD Inc., Santa Clara, CA

9:35 An Efficient Method for Custom Integrated Circuit Global RoutingE. Rosenberg*, S. Chopra**,AT&T Bell Labs, Holmdel, NJ*, Columbia University, New York, NY**

10:00 A Heuristic Global Router for Polycell LayoutV.K. De, G. Kedem, K. Kozminski, Renssalaer Polytechnic Institute, Troy, NY

10:25 A Two-Layer Channel Routing Algorithm for Mixed Analog and Digital Signal Nets

R.S. Gyurcsik, J-C. Jeen, W.T. Liu, North Carolina State University, Raleigh, NC

10:50 A Power Bus Channel Router

R.Y. Tsui, AT&T Bell Labs, Murray Hill, NJ

11.1

11.2

11.3

11.4

11.5

11.6

CONTENTS

WEDNESDAY MORNING Lilac Ballroom North—Convention Center Session 12 PAPER

ANALOG CIRCUIT TECHNIQUES

Chairman: D.WayneCo-Chairman: A.B. Grebene

8:45 Noise, Crosstalk and Distortion in Mixed Analog/Digital Integrated Circuits

C. Jungo, G.H. Warren, IMP, San Jose, CA

9:10 Design Techniques for Fully Differential AmplifiersJ. Haspeslagh, W. Sansen, Katholieke Universiteit Leuven, Heverlee, Belgium

9:35 A10.7-MHz Switched-Capacitor Bandpass Filter

B-S. Song, University of Illinois, Urbana, IL

10:00 A Novel Parasitic Insensitive Switched-CapacitorTechnique for Realizing Very Large TimeConstants

K. Nagaraj, AT&T Bell Laboratories, Murray Hill, NJ

10:25 Variable Scale Edge Detection of ImagesB.P. Mathur, H.T. Wang, C.T. Tsen, E. Walton, Rockwell Intl. Science Center, Thousand Oaks, CA

10:50 A Set of 4 ICs in CMOS Technologyfor a Programmable Hearing Aid

F. Callias, F. Salchli, D. Girard, M. Perrin, Ph. Aubert, CSEM S.A, Neuchatel, Switzerland

11:15 Bi-CMOS Tracking Servo LSI for 8mmVCR

S. Mizoguchi*, Y. Sugimoto*, M. Taguchi*, H. Sadamatsu*, T. Hirota*, K. Nishitani**, Y. Tanii*, Toshiba Corp,Kawasaki, Japan*, Sony Corp, Tokyo, Japan**

12.1

12.2

12.3

12.4

12.5

12.6

12.7

WEDNESDAY MORNING Lilac Ballroom South—Convention Center Session 13 PAPER

DEVICE, PROCESS & STATISTICAL MODELING

Chairman: P.M. Zeitzoff

Co-Chairman: H. Abdel-Aty-Zohdy

8:45 Accurate Analog Modeling of Short Channel FETs Based on Table Lookup 13.1

A.R. Rofougaran, B. Furman, A.A. Abidi, University of California, Los Angeles, CA

9:10 An Accurate Two-Dimensional Intrinsic Capacitance Model of Short Channel MOSFETs 13.2

S.S. Chung, National Chiao Tung University, Taiwan, R.O.C.

9:35 A Simple GaAs MESFET Model for Circuit Simulation Reflecting the Dependence on Device

Geometry and Process 13.3

S.W. Tarasewicz, Northern Telecom Electronics Ltd, Ottawa Canada

10:00 Response Surface Methodology; A Modeling Tool for Integrated Circuit Designers 13.4

J. McDonald, R. Maini, L. Spangler, H. Weed, Motorola Inc., Mesa, AZ

10:25 Statistical Process Simulation for CAD/CAM 13.5

P.K. Mozumder*, A.J. Strojwas*, D. Bell**, Carnegie Mellon Univ., Pittsburgh, PA*, Texas Instruments Inc., Dallas,

TX**

10:50 Modeling Modern Bipolar Technologies to Insure Design for Manufacturability 13.6

J.L. Bouknight, S.M. Leibiger, S.K. Yakabu, H.K. Hingarh, National Semiconductor, Puyallup, WA

11:15 The Effect of Contact Placement on Drive Currents in 1,25nm Gate Arrays: Measured and

Simulated 13-7

W.R. Richards, J.C. Tsang, R.T. Fuller, General Electric Co, Research Triangle Park, NC

CONTENTS

WEDNESDAY AFTERNOON Holiday Hall—Holiday Inn Session 14 PAPER

TARGETED SILICON COMPILERS

Chairman: J. LipmanCo-Chairman: R.W. Bryant

2:25 Module Generators for Both Sea of Gates and Full Custom ICs 14.1

C. Piguet, E. Dijkstra, G. Berweiler, C. Voirol, M. Stauffer, M. Joss, CSEM, Neuchatel, Switzerland

2:50 Measurements of Switched Capacitor Filters Generated with a Silicon Compiler 14.2

W.J. Helms, University ofWashington, Seattle, WA

3:15 Physical Assembly for Analog Compilation of High Voltage ICs 14.3

E. Berkcan, M. d'Abreu, General Electric Co, Schenectady, NY

3:40 SPAID: An Architectural Synthesis Tool for DSP Custom Applications 14.4

B,S. Haroun, M.I. Elmasry, Univ. of Waterloo, Waterloo, Ont, Canada

4:05 Efficient Controller Architectures for DSP Compilers 14.5

J.v. Meerbergen, Phillips Research Labs, Eindhoven, The Netherlands

4:30 SPEED - A Highly Flexible Slice Structure and Datapath Generator 14.6

P. Duzy, Siemens AG, Munich, West Germany

4:55 Automatic Synthesis of Signal Processing Benchmark using the CATHEDRAL Silicon Compilers 14.7

L. Claesen*, F. Catthoor*, D. Lanneer*, S. Note*, G. Goossens*, J. Van Meerbergen**, H. DeMan*, IMEC, Leuven,

Belgium*, Philips Res. Labs. Eindhoven, The Netherlands**

WEDNESDAYAFTERNOON 101 Meeting Rooms—Convention Center Session 15 PAPER

USER PROGRAMMABLE LOGIC DEVICES

Chairman: W.S.Carter

Co-Chairman: S.H. Chiao

2:25 A 20 ns CMOS Programmable Logic Device for Asynchronous Applications 15.1

J. Pathak, S. Douglass, D-A. Vider, T. Muler, J. Arreola, S. Mehta, Cypress Semiconductor Corp, San Jose, CA

2:50 A 2500 gate Programmable Logic Device with Subdivisable Macrocells 15.2

K.H. Gudger, G.S. Gongwer, Atmel Corp, San Jose, CA

3:15 A 9000-Gate User-Programmable Gate Array 15.3

H-C. Hsieh, K. Duong, J.Y. Ja, R. Kanazawa, L.T. Ngo, LG. Tinkey, W.S. Carter, R.H. Freeman, Xilinx, San Jose, CA

3:40 An Architecture for Electrically Configurable Gate Arrays 15.4

A. El Gamal, J. Greene, J. Reyneri, E. Rogoyski, K. El-Ayat, A. Moshen, Actel Corp, Sunnyvale, CA

4:05 Bus I/O Register Intensive User-Configurable Microprocessor Peripheral 15.5

C-Y. Hung, Y-F. Chan, Altera Corp, Santa Clara, CA

4:30 The EBS-1, An EPROM-Based Sequencer ASIC 15.6

M.D. Brown, J.A. Small, J.A.Vincent, Eastman Kodak Company, Rochester, NY

4:55 Gate Array Design Productivity: An Empirical Investigation 15.7

C.F. Fey, D. Paraskevopoulos, Xerox Corp, El Segundo, CA

CONTENTS

WEDNESDAY AFTERNOON Lilac Ballroom North—Convention Center Session 16 PAPER

TESTING AND TESTABILITY

Chairman: A.L. Goodman

Co-Chairman: D.L. Black

2:00 TUTORIAL

BIST Using Pseudorandom Test Vectors and Signature Analysis 16.1

F. Wang,Tektronix, Inc., Beaverton, OR

2:50 Integrated Pin Electronics for VLSI Functional Testers 16.2

J.A. Gasbarro*, M.A. Horowitz**, Xerox Corp, Palo Alto, CA*, Stanford University, Stanford, CA**

3:15 A Test System for High Speed VLSI Array Qualifications 16.3

T.J. Rolfes, E.F.Hahn, P.J. Zajkowski, IBM Corp, Hopewell Junction, NY

3:40 The Loophole in Logic Test: Mixed Signal ASIC 16.4

R. Prilik, J. VanHorn, D. Leet, IBM Corp, EssexJunction, VT

4:05 Design for Testability for Mixed Analog/Digital ASICs 16.5

P.P. Fasang, D. Mullins, T. Wong, National Semiconductor Corp, Santa Clara, CA

4:30 Bottom-Up Testing Methodology for VLSI 16.6

J.P. Teixeira, C.F.B. Almeida, J.A. Gracio, P.A. Bicudo, A.L. Oliveira, N. Rua, INESC, CEAUTL(INIC), 1 ST, Lisboa,

Portugal

4:55 LATE PAPER

A MethodologyfortheTest of Embedded Compiled Cells 16.7

M. Samad, T. Butzerin, VLSI Technology, San Jose, CA

WEDNESDAY AFTERNOON Lilac Ballroom South—Convention Center Session 17 PAPER

HIGH SPEED CIRCUITS

Chairman: M. Horowitz

Co-Chairman: T. Sideris

2:25 GaAs Low-Power Shift Register and Arithmetic Logic Unitfor a High-Speed Digital SignalProcessor 17.1

H.P. Singh*, R.A. Sadler*, J.A. Irvine**, G.E. Gorder**, ITT Roanoke, VA*, ITT, Nutley, NJ**

2:50 Design and Testof a 2 Gb/s GaAs 16/8 Bit MUX/DEMUX Pair 17.2

B.W. Cheney, P. Hamilton, TriQuint Semiconductor, Beaverton, OR

3:15 A 200 Mbps, 60x16 CMOS Crosspoint Switch 17.3

J.A. CarellP, R.A. Johns**, P.C. Metz*, AT&T Bell Laboratories, Allentown, PA*, AT&T Bell Laboratories, Naperville,IL**

3:40 A100 MEGA-FLOP Double Precision IEEE Multiplier Block for Advanced Bipolar VLSI 17.4

S. Tibbitts, W.S. Snyder, W. Keshlear, National Semiconductor, Puyallup, WA

4:05 A High-Speed Dynamically Reconfigurable 32-Bit CMOS Adder 17.5

I.S. Hwang, P.S. Magarshack, AT&T Bell Laboratories, Allentown, PA

4:30 A10 MHz (255,223) Reed-Solomon Decoder 17.6

N. Demassieux*, F. Jutland*, M. Muller**, ENST, Paris, France*, Schlumberger Industries, Montrouge, France**

CONTENTS

WEDNESDAYAFTERNOON Windsor Room—Holiday Inn Session 18 PAPER

DATA CONVERSION CIRCUITS

Chairman: D.Barber

Co-Chairman: H.S. Lee

2:25 A Quasi-Passive CMOS Pipeline D/A Converter 18.1

F-J. Wang*, G.C. Temes*, S. Law**, UCLA, LosAngeles, CA*, Xerox Corp, El Segundo, CA**

2:50 A Quad 12 Bit DAC with Readback and Software Mode Control 18.2

S. Lewis, S. Lefton, Analog Devices, Wilmington, MA

3:15 A100 MHz Pipelined CMOS Copmparatorfor Flash A/D Conversion 18.3

J-T. Wu, B.A. Wooley, Stanford University, Stanford, CA

3:40 ANovelTechnjquefor12-BitFlashA/DConversion 18.4

A.S. Trfpathi, K. Sridhar, IMP, San Jose, CA

4:05 A 667ns, 12-Bit Two-Step Flash ADC 18.5

D.A. Kerth, N.S. Sooch, E.J. Swanson, Crystal Semiconductor Corp, Austin, TX

4:30 A 10-bit 5 Msample/sec CMOS 2-Step Flash ADC 18.6

J. Doemberg, D.A. Hodges, University of California, Berkeley, CA

4:55 LATE PAPER

A 4-Bit, 1 GHz Sub-Half Micrometer CMOS/SOS Flash Analog-to-Digital Converter using FocusedIon Beam Implants 18.7

R. Walden, A. Schmitz, L. Larson, A. Kramer, J. Pasiecznik, Hughes Research Laboratories, Malibu, CA

WEDNESDAYEVENING Holiday Hall—Holiday Inn Session 19 PAPER

8:00 LARGE MERCHANTVENDORS vs. THE LITTLE GUYS

Who will win the ASIC Business?

Moderator: D.E. Brown

Mitel Corporation

19.1

WEDNESDAY EVENING 101 Meeting Rooms—Convention Center Session 19 PAPER

8:00 FAST TURNAROUND: DESIGN TO SYSTEM

If It Can't Be Done In A Timely Fashion, Then Don't Bother Doing It At All

Moderator: J. LipmanVLSI Technology, Inc.

19.2

WEDNESDAY EVENING Lilac Ballroom North—Convention Center Session 19 PAPER

8:00 RESEARCH CONSORTIUMS, COOPERATIVES, AND INDUSTRY ASSOCIATIONS

Moderator: T.M. KelleyEastman Kodak Company

19.3

CONTENTS

WEDNESDAYEVENING Lilac Ballroom South—Convention Center Session 19 PAPER

8:00 CMOS, BiCMOS, BIPOLAR—THE ASIC TECHNOLOGY PUZZLE

Moderator: M. HollabaughAMCC

Co-Moderator: M. KingBell Northern Research

19.4

THURSDAY MORNING Holiday Hall—Holiday Inn Session 20 PAPER

HIGH DENSITY, HIGH PERFORMANCE GATE ARRAYSChairman: R. Rasmussen

Co-Chairman: H.Scalf

8:45 A13,000 Gate 3 Layer Metal BiPolar Gate ArrayB. Coy, R. Yuen, Applied MicroCircuits Corp, San Diego, CA

9:10 SH100E10000 Gate ECL/CMLGate Array Family with ECL/TTL I/O CompatibilityM. Franz*, K. Delker**, T.C. Whang*, W. Wilhelm**, Siemens Components, Inc., Santa Clara, CA*, Siemens AG,Munich, West Germany**

9:35 A 72K CMOS Channelless Gate Array with Embedded 1 Mbit Dynamic RAMK. Sawada, T. Sakurai, K. Nogami, T. lizuka, Y. Uchino, Y. Tanaka, T. Kobayashi, K. Kawagai, Y. Shiotari, Y.Itabashi, S. Kohyama, Toshiba Corp, Kawasaki, Japan

10:00 A Sub Half-ns 237K Gate CMOS Compacted ArrayA. Hui, T. Wong, R. Szeto, S. Yeh, C-Y. Kao, D. Wong, Y. Tse, LSI Logic Corp, Santa Clara, CA

10:25 A120K-Gate Usable CMOS Sea of Gates Packing 1.3M Transistors

Y. Suehiro, D. Miura, M. Naitoh, S,Tsutsumi, T. Shirato, Fujitsu Ltd, Kawasaki, Japan

10:50 A High-Density BiCMOS Direct Drive ArrayW. Carney, T. Wong, A. Hui, C. Wang, E. Chan, D. Wong, S. Chan, LSI Logic Corp, Milpitas, CA

11:15 LATE PAPER

1.5 Gb/Sec. Data Rate Communications Gate Array in GaAs

T. Coe, R. Cates, W. Larkins, R. Deming, N. Hendrickson, I. Deyhimy, Vitesse Semiconductor Corp, Camarillo, CA

11:30 LATE PAPER

An Ultra-High Speed Gate Array Based on 0.6um Silicon Bipolar TechnologyM.P. Cooke, M.J. Golder, D.G. Taylor, Plessey Research & TechnologyLtds, Caswell, England

11:45 LATE PAPER

DLM/TLM Compatible 1 .Oum GateArray with Over 100K Usable Gates

T. Kobayashi, T. Aoki, Y. Tanaka, M. Nakahara, Y. Itabashi, E. Hamada, S. Kohyama, Toshiba Corp, Kawasaki,Japan

20.1

20.2

20.3

20.4

20.5

20.6

20.7

20.8

20.9

CONTENTS

THURSDAYMORNING 101 Meeting Rooms—Convention Center Session 21 PAPER

TELECOMMUNICATION NETWORK IC APPLICATIONS

Chairman: D. Embree

Co-Chairman: S. Hao

8:20 INVITEDTUTORIAL

Overview of ISDN User-Network Interface 21.1

D.P.G. Schenkel, Mitel Corp, Kanata, Canada

9:10 A13 Bit ISDN-Band Oversampled ADC Using Two-StageThird Order Noise Shaping 21.2

L. Longo*, M. Copeland**, Bell Northern Research, Ottawa, Ont, Canada*, Carleton Univ., Ottawa, Ont, Canada**

9:35 A13-Bit, 160kHz Sigma-Delta A/D Converter for ISDN 21.3

S.R. Norsworthy, I.G. Post, AT&T Bell Laboratories, Reading, PA

10:00 A Dual-Channel &A Voiceband PCM Codec 21.4

V. Friedman*, D.M. Bringhaupt*, D-P. Chen*, T.W. Deppa*, J P. Elward, Jr.*, E.M. Fields*, J.W. Scott**, T.R.

Viswanathan**, AT&T Bell Labs, Murray Hill, NJ*, AT&T Bell Labs, Reading, PA**

10:25 Echo Canceller Design for High Speed Modems 21.5

R.J. Corder, C.C. Perkins, Rockwell International, Newport Beach, CA

10:50 Real-Time String Search Engine LSI for 800-Mbit/sec. LANs 21.6

H. Yamada*, Y. Murata**, T. Maeda***, R. Ikeda***, K. Motohashi***, K. Takahashi*, NEC Corp., Kanagawa,Japan*, NEC Corp, Abiko, Japan**, NEC Corp, Kawasaki, Japan***

11:15 LATE PAPER

A16-Bit Fourth Order Noise Shaping D/A Converter 21.7

L.R. Carley, J. Kenney, Carnegie-Mellon University, Pittsburgh, PA

THURSDAY MORNING Lilac Ballroom North—Convention Center Session 22 PAPER

HIGH PERFORMANCE FABRICATION TECHNOLOGY

Chairman: M.PopeCo-Chairman: M. Hartranft

8:45 INVITED

Bi-CMOS Technology for Semi-Custom IntegratedCircuitsA.R. Alvarez*, D.W. Schucker**, Cypress Semiconductor, SanJose, CA*, Motorola Inc., Mesa, AZ**

9:10 Process HE: A Highly Advanced Trench Isolated Bipolar Technologyfor Analogue and DigitalApplicationsP.C. Hunt, M.P. Cooke, Plessey Research and TechnologyLtd,Caswell, England

9:35 70 ps ECL-Gate Si-Bipolar Technology using Borosenic-Poly Process with Coupling-BaseImplantT. Yamaguchi, S. Yu, E. Lane, J. Lee, V. Garuts, E. Patton, R. Herman, D. Ahrendt, V. Drobny, Tektronix, Inc.,Beaverton, OR

10:00 A Novel Base-Emitter Self-Alignment Process for High Speed Bipolar LSIs

Y. Okita, M. Shinozawa, A Kawakatsu, Y. Umemura, K. Yamaguchi, K. Akahane, OKI Electric Industry Co, Ltd,Tokyo, Japan

10:25 Laser Customization by DirectWriting of Aluminum Interconnects

T. Cacouris, R.R. Krchnavek, G. Scelsi, R. Scarmozzino, R.M. Osgood Jr., Columbia University, New York, NY

10:50 Laser Processing for Quick-Turn Semiconductor Devices i, ,,, t

v

L.L. Burns, A R. Else'a, Lasa Industries, SariJdse,'CA ' ' <f

11:15 ULSI System Models

V.K. De, M. Berger, J.D. Meindl, Rensselaer Polytechnic Institute, Troy, NY

22.1

22.2

22.3

22.4

22.5

3 22i6f

22.7

CONTENTS

THURSDAY MORNING Lilac Ballroom South—Convention Center Session 23 PAPER

PACKAGING & SYSTEM INTERCONNECT

Chairman: A.I. Lakatos

Co-Chairman: A.K. Silzars

8:20 TUTORIAL

High Performance Integrated Circuit Packaging 23.1

B.C. Johnson, Univ. of Arizona, Tucson, AZ

9:10 INVITED

Trends in Semiconductor Packaging A Merchant House View 23.2

H. Test, Texas Instruments, Inc., Dallas, TX

9:35 Accurate Measurement of High Speed Package and Interconnect Parasitics 23.3

D.E. Carlton, K.R. Gleason, K. Jones, A. Hopkins, K. Noonan, E.W. Strid, Cascade Microtech Inc., Beaverton, OR

10:00 Generalized Wiring Rules for CMOS Circuits 23.4

J.Tomczak, IBM, Essex Junction, VT

10:25 Analysis and Guidelines for High-Speed VLSI System Interconnections 23.5

C. Reynolds, IBM Corp, Essex Junction, VT

10:50 Investigation of Power Distribution Strategies for Wafer Scale Integration (WSI) 23.6

T.A. York, UMIST, Manchester, U.K.

THURSDAYAFTERNOON Holiday Hall—Holiday Inn Session 24 PAPER

CELL-BASED DESIGNS

Chairman: G. SporzynskiCo-Chairman: T. Sideris

1:00 A CMOS-Based Mixed Analog-Logic Standard Cell Product FamilyM. Gruver*, R. Hedman*, M. Russell*, B. Owens*, M. Massetti**, D. Mariano**, L Smith**, D. Willmott**, E.

Johnson**, IBM, Rochester, MN*, IBM, Essex Junction, VT**

1:25 1.2 Micron, High Speed, High Density CMOS Analog LibraryJ. Trontelj, L. Trontelj, S. Ozbolt, T. Pletersek, V. Kunc, University Edvard kardelj, Ljubljana, Yugoslavia

1:50 Advanced Standard Cell Library Provides High Performance Mixed Digital, Analog, and

EEPROM Single Chip Solutions

G. Richmond, D. Sowards, S. Khan, B.S. Nataraj, EXAR Inc., San Jose, CA

2:15 A Reduced Circuit Library Design SystemR.D. Kilmoyer, D.J. Hathaway, A.M. Chu, IBM, EssexJunction, VT

2:40 A High-Speed 16-Bit Cascadable ALU Using an ASPECTStandard Cell Approach

B.L. Gabel, W.M. Keshlear, National Semiconductor Corp, Puyallup, WA

3:05 A VLSI Chip Set for a Small Mainframe Processor

S. Yamada, T. Sano, M. Saito, M. Motohashi, H. Oki, H, Tsuruya, NEC Corporation, Kawasaki, Japan

24.1

24.2

24.3

24.4

24.5

24.6

CONTENTS

THURSDAYAFTERNOON 101 Meeting Rooms—Convention Center Session 25 PAPER

HIGH PERFORMANCECMOS PROCESSES

Chairman: M.KingCo-Chairman: S. Kohyama

1:00 A High Performance Submicron Twin Tub V Technology for Custom VLSI Application 25.1

C.W. Leung, Ml. Chen, W.T. Cochran, M.J. Thoma, B.C. Grugett, T. Yang, D.R. Stone, MN.S. Tsai, AT&T Bell

Laboratories, Allentown, PA

1:25 A 0.8um CMOS Technology for High Performance ASIC Memory and Channelless Gate Array 25.2

FT. Liou, Y.P. Han, F. Bryant, R. Miller, S.W. Chiu, L. Eng, C. Spinner, M. Zamanian, G. Klein, J. Barnes,

SGS-Thomson Microelectronics, Carrollton, TX

1:50 An Advanced Triple Level Metal CMOS Technology for ASIC Applications 25.3

J. Schmiesing, K.Y. CHang, F. Pintchovski, K. Baker, J. Klein, C.S. Meyer, S. Lai, D. Hoang, D. Tang, Motorola,

Inc., Austin, TX

2:15 Challenges of a Vintage 1994 CMOS Logic Chip 25.4

J.H. Hohl, B.C. Johnson, University of Arizona, Tucson, AZ

2:40 An Advanced High Voltage CMOS Process for Custom Logic Circuits with Embedded EEPROM 25.5

K.Y. Chang, S. Cheng, K-M. Chang, J. Chalmers, C. Swift, J. Yeargain, Motorola, Inc., Austin, TX

3:05 A SiOx Resistor Load SRAM Process for ASIC Applications 25.6

T. Okumura, S. Onishi, K. Tanaka, K. Sakiyama, Sharp Corp, Tenri City, Japan

3:30 Unified Design Methodology and Device Architecture for Multi-Generation ASIC Applications 25.7

T. Kuroda, H. Suzuki, H. Akiba, T. Aoki, T. Shigematsu, K. Kawagai, Toshiba Corp, Kawasaki, Japan

THURSDAYAFTERNOON Lilac Ballroom North—Convention Center Session 26 PAPER

TELECOM CIRCUITS

Chairman: C.JungoCo-Chairman: D.A. Wayne

1:00 A Mixed Analog/Digital CMOS ICfor Digital Telephony Applications 26.1

D.W. Simmons, D.L. Lynch, H. Slizil, T. Wong, G'". Quelsne, Bell-Northern Research, Ottawa, Ont, Canada

1.25 A Low Power, High Performance, Phone Headset Amplifier in CMOS Technology 26.2

M. Negahban*, R. Stolaruk*, V. Kraz**, Silicon Systems Inc., Tustin, CA*, Plantronics Inc., Santa Cruz, CA**

1:50 ASVQuadFilterCodeclCwjthuPPropgrarnmability 26.3

G. Quesnel, D.L. Lyrich^ Bell-Northern Research8 Ltd, Ottawa, Ont, Canada

2:15 An Analog Front End for Full-Duplex Digital Transceivers Working on Twisted Pairs 26.4

O. Agazzi, A. Adan, Harris Semiconductor Co, Melbourne, FL

2:40 An Analog Interface Circuit (AIC) for High Speed Modems 26.5

S. Wong, K. Titizer, B. Fotouhi, R. Gregorian, Sierra Semiconductor, San Jose, CA

3:05 A Single-Supply CMOS V.22bis Modem Analog Processor 26.6

S.J. Daubert, D.W. Green, J.M. Khoury, J.M. Trosino, E.J. Zimany, J.R. Barner, J. Plany, M.F. Tompsett, AT&T Bell

Laboratories, Murray Hill, NJ

3:30 A Fully Integrated Analog Front End LSI for 9600/4800 bps Modems 26.7

K. Terashima, Y. Fujita, S. Nomura, H, Kishigami, Toshiba Corp, Kawasaki, Japan

CONTENTS

THURSDAY AFTERNOON Lilac Ballroom North—Convention Center Session 26 PAPER

RELIABILITY

Chairman: T.M.KellyCo-Chairman: S.R. Quigley

1:00 ESD Protection Structure Issues and Design for Custom Integrated Circuits 27.1

L.R. Avery, David Sarnoff Research Center, Princeton, NJ

1:25 Resistorless ESD Protection Device for High Speed CMOS Circuits 27.2

Q. Say, National SemiconductorCorp, Milpatas, CA

1:50 Thermal and Electrical Transients During ESD Stress 27.3

S. Dave, Consultant, Palo Alto, CA

2:15 RELY: A Reliability Simulatorfor VLSI Circuits 27.4

W-J. Hsu, C-C. Shih, Information Sciences Institute, Marinadel Rey, CA

2:40 Design Methodology for Defect Tolerant Integrated Circuits 27.5

W. Maly, Carnegie-Mellon Univ., Pittsburgh, PA

3:05 A Circuit Breaker for Redundant IC Systems 27.6

L.R. Carley, W. Maly, Carnegie-Mellon University, Pittsburgh, PA

3:30 Marginal Test of DRAMs by Masked Alpha-Radiation 27.7

D. Gleis, K. Hoffman, Bundeswehr, Univ., Munich, West Germany

3:55 LATE PAPER

RELIANT: A Reliability Analysis Tool for VLSI Interconnects 27.8

D. Frost, K. Poole, D. Haeussler, Clemson University, Clemson, SC