CSE 425 LAB 6 Part 1Simple Hardware Design targeting MicroBlaze on Digilent Nexys 2 Board

IntroductionThis lab guides you through the process of using Xilinx Platform Studio 12.4 (XPS) to create a simple system that includes a processor, a BRAM and peripherals such as DIP switches, push buttons, and seven-segment displays which interact with processor.

In this lab, you will use the BSB (Base System Builder) of the XPS to create a processor system consisting of the following blocks:

∙ MicroBlaze (version 8.00.b)∙ MDM (MicroBlaze Debug Module)∙ LMB (Local Memory Bus) BRAM Controllers

Completed Design

MicroBlaze

LMBBRAMCNTLR

BRAM

LMBBRAMCNTLR

MDM UART

GPIO

GPIO

GPIO

PLB

LEDs

DIP

SSEG

XPSBRAMCNTLR

BRAM

∙ BRAM (Block RAM)∙ UART (Universal Asynchronous Receiver Transmitter) for serial communication∙ XPS BRAM Controller∙ BRAM (Block RAM)∙ GPIO modules which provide communication between peripherals and the system

‣ Note: In this exercise, you use PLB (Processor Local Bus) which provides bus infrastructure for interconnection of the system.

Step 1

⁃ You need board support files to create your reference system. Board support files contains the necessary information and files which are specific to your physical system.⁃ To get board support files for Digilent Nexys 2 board, go to Digilent website and download the related file as shown below.

⁃ Unzip the file, and copy the extracted files under ./Digilent_Nexys_EDK_Board_Support_Files_V_2_1\lib\Digilent\boards into the related directory (C:\Xilinx\12.4\ISE_DS\EDK\board\Digilent\boards) in your host machine (computer).

Step 2

⁃ Open XPS by selectingStart → All Programs → Xilinx ISE Design Suite 12.4 → EDK → Xilinx Platform Studio.⁃ Leave the default Base System Builder option and click OK to start the wizard.

⁃ Define a directory to create your project and click OK.⁃ In the upcoming screen, it will be asked to select the interconnect type for your system. ⁃ You will use PLB (Processor Local Bus) for this project. So leave PLB system selected and click OK.⁃ Continue with selecting “I would like to create a new design” and click Next.⁃ In this stage, Base System Builder asks for board selection which fits to your design. Since you copied our board settings, Base System Builder shows our Nexys 2-1200 Board in the menu. Select it and click Next.

⁃ In the System Configuration dialog, leave the default Single-Processor System option and click Next.⁃ In the Processor Configuration dialog box, leave the default settings:

♦ Reference Clock Frequency: 50 MHz♦ Processor Type: MicroBlaze♦ System Clock Frequency: 50 MHz♦ Local Memory: 8 KB♦ Debug Interface: On-Chip HW Debug Module♦ Enable Floating Point Unit: UNCHECKED

After checking this settings, click Next.⁃ Peripheral Configuration Section shows the peripherals which are ready on our board according to board support files selected.

In this stage, you can start to build our hardware by selecting:♦ LED_7SEGMENT♦ LEDs_8Bit♦ Push_Buttons_3Bit♦ RS232_PORT♦ Switches_8Bit♦ dlmb_cntlr (which is selected by default and cannot be removed from the system!)♦ ilmb_cntlr (which is selected by default and cannot be removed from the system!)

⁃ Configure your system similarly as the configuration above and click Next.

⁃ Skip the Cache Configuration stage and click Next.⁃ Leave the default selections in the Application Configuration dialog and click Next.⁃ Verify the system summary and analyze the memory map of the system and the files which are created.⁃ Click Finish and select Start using Platform Studio in the upcoming screen.

Step 3

⁃ A System Assembly View will be displayed showing peripherals and busses in thesystem, and the system connectivity.

⁃ Click on the Block Diagram tab to open a block diagram view and observe thevarious components that are used in the design.⁃ In the System Assembly View click on plus button and observe the expanded (detailed) bus connection view of the system.⁃ Click on the Ports filter and have an expanded view. This is where you can make internal and external net connections.⁃ Click on the Addresses tab and have an expanded view. This is where you can assign base/high addresses to the peripherals in the system.

Step 4

⁃ Run PlatGen by selecting Hardware → Generate Netlist to generate the system netlist (NGC).

‣ Note: The NGC file is a netlist file that contains both logical design data and constraints. This file replaces both Electronic Data Interchange Format (EDIF) and Netlist Constraints File (NCF) files.

⁃ Click on the Design Summary tab. The Design Summary allows you to quickly access design overview information, reports, and messages. It displays information specific to your targeted device and software tools. The panes on the left side of the Design Summary allow you to control the information displayed in the right pane.⁃ Browse to your project directory and analyze directories that were created.⁃ Generate bitstream by selecting Device Configuration → Update Bitstream.Prior to download, the instruction memory (FPGA Block RAM) will be updated in the bitstream with the executable generated using the GNU compiler.⁃ Download your application to the board by doing following operations:► Set up your circuit and make the connections between your PC and the Digilent Nexys 2 board.► Connect 9-pin RS-232 cable to the board.► Start a serial communication between your PC and the board by doing:

♦ Open the “putty” program on your machine♦ Enter the necessary parameters:

– Communiccation Port: COM1 (Check where your cable is connected)– Data bits: 8– Stop bits: 1– Parity: None– Flow Control: none

♦ Click Open to start the connection session.

► Open Adept tool and select “download.bit” bitstream file under “./implementation/” .► Click Program to download the configuration into the FPGA.

Step 5

⁃ In this step, you will add a hardware block into your existing system.⁃ Go to IP Catalog menu and click on Memory and Memory Controller section.⁃ Double-click on XPS BRAM Controller and click Yes to add this block to your system. Leave the default settings in the configuration window and click OK.⁃ Double-click on Block RAM (BRAM) Block in the same section and click Yes to add this block to your system. Leave the default settings in the configuration window and click OK.

‣ Note: XPS BRAM Controller defines an interface between PLB and BRAM. In other words, it simply does transformation between PLB transactions and BRAM transactions.

⁃ In the System Assembly View, select Bus Interfaces tab and expand xps_bram_if_cntlr_0

instance. Connect it to the PLB line by selecting mb_plb in the SPLB line.⁃ In the System Assembly View, select Bus Interfaces tab and expand bram_block_0 instance. Connect it to the xps_bram_if_cntlr_0 by selecting xps_bram_if_cntlr_0_PORTA.

⁃ As you see figure below, there is no address space assigned for xps_bram_if_cntlr_0 instance.

⁃ Change size of xps_bram_if_cntlr_0 instance to 16K.⁃ Click Generate Addresses button to create the updated memory address map with xps_bram_if_cntlr_0 instance.⁃ Click Device Configuration → Update Bitstream to update bitstream file including your added hardware block.