CSE 311 Foundations of Computing I Lecture 25 Circuits for FSMs, Carry-Look-Ahead Adders Autumn 2011 CSE 3111 Announcements Nice overview of adder circuits atAutumn 2011CSE 3112 Last lecture highlights Languages not recognized by any DFA { 0 n 1 n : n0 } Binary Palindromes Strings of Balanced Parentheses Using DFAs for efficient pattern matching Autumn 2011CSE 3113 FSMs in Hardware Encode the states in binary: e.g. states 0,1,2,3 represented as 000,100, 010,001, or as 00,01,10,11. Encode the input symbols as binary signals Encode the outputs possible as binary signals Build combinational logic circuit to compute transition function: Autumn 2011CSE 3114 Boolean Circuit for State Transition Function current statenext state input signals output signals FSMs in Hardware C ombine with sequential logic for Registers to store bits of state Clock pulse At start of clock pulse, current state bits from registers and input signals are released to the circuit At end of clock pulse, output bits are produced and next state bits are stored back in the same registers Autumn 2011CSE 3115 Boolean Circuit for State Transition Function current statenext state input signals output signals FSM for binary addition Assume that the two integers are a n-1...a 2 a 1 a 0 and b n-1...b 2 b 1 b 0 and bits arrive together as [a 0,b 0 ] then [a 1,b 1 ] etc. s C out =1 1 [0,1],[1,0] C out =0 1 C out =1 0 C out =0 0 [1,1] [0,1],[1,0] [0,0] [0,1],[1,0] [1,1] [0,1],[1,0] [1,1] [0,0] [1,1] [0,0] [0,1],[1,0] [1,1] [0,0] [1,1] Generate a carry of 1 [0,1],[1,0] Propagate a carry of 1 if it was already there FSM for binary addition using output on edges Assume that the two integers are a n-1...a 2 a 1 a 0 and b n-1...b 2 b 1 b 0 and bits arrive together as [a 0,b 0 ] then [a 1,b 1 ] etc. [1,1] Generate a carry of 1 [0,1],[1,0] Propagate a carry of 1 if it was already there [0,1],[1,0]: 1 C out =0C out =1 [0,0]: 0 [0,1],[1,0]: 0 [0,0]: 1 [1,1]: 0 [1,1]: 1 Example: 1-bit Full Adder Autumn 2011CSE 3118 A Sum C out C in B 1-Bit Full Adder current state input signals next state output FSMs without sequential logic What if the entire input bit-strings are available at all once at the start? E.g. 64-bit binary addition Dont want to wait for 64 clock cycles to compute the output! Suppose all input strings have length n Can chain together n copies of the state transition circuit as one big combinational logic circuit Autumn 2011CSE 3119 A 2-bit ripple-carry adder Autumn 2011CSE a0a0 b0b0 C out C in Sum 0 a Sum C out C in b 1-Bit Full Adder a1a1 b1b1 Sum 1 C out C in 0 Problem with Chaining Transition Circuits Resulting Boolean circuit is deep There is a small delay at each gate in a Boolean circuit The clock pulse has to be long enough so that all combinational logic circuits can be evaluated during a single pulse Deep circuits mean slow clock. Autumn 2011CSE 31111 Speeding things up? To go faster, need to work on both 1 st half and 2 nd half of the input at once How can you determine action of FSM on 2 nd half without knowing state reached after reading 1 st half? Autumn 2011CSE b 1 b 2...b n/2 b n/2+1...b n-1 b n what state? Idea: Figure out what happens in 2 nd half for all possible values of the middle state at once Transition Function Composition Transition table gives a function for each input symbol Autumn 2011CSE State01 s0s0 s0s0 s1s1 s1s1 s0s0 s2s2 s2s2 s0s0 s3s3 s3s3 s3s3 s3s3 s0s0 s2s2 S3S3 s1s , s0s0 s2s2 s3s3 s1s s0s0 s2s2 s3s3 s1s f0f0 f1f1 State reached on input b 1...b n is f b n (f b n-1...(f b 2 (f b 1 (start)))...)= f b n f b n-1... f b 2 f b 1 (start) Constant size 2-level Boolean logic to convert input symbol to bits for transition function compute composition of two transition functions Total depth 2 log 2 n and size n Autumn 2011 CSE fb6fb5fb6fb5 fb8fb7fb8fb7 b8b8 b7 b7 b5b5 b6b6 fb5fb5 fb7fb7 fb6fb6 fb8fb8 fb8fb7fb6fb5fb8fb7fb6fb5 fb2fb1fb2fb1 fb4fb3fb4fb3 b1b1 b2b2 b3b3 b4b4 fb1fb1 fb2fb2 fb3fb3 fb4fb4 fb4fb3fb2fb1fb4fb3fb2fb1 fb8fb7fb6fb5fb4fb3fb2fb1fb8fb7fb6fb5fb4fb3fb2fb1 b fbfb fg gfgf Transition Function Composition Carry-Look-Ahead Adder Compute generate G i = a i b i [1,1] propagate P i =a i b i [0,1],[1,0] These determine transition and output functions Carry C i =G i ( P i C i-1 ) also written C i =G i +P i C i-1 Sum i = P i C i-1 Unwinding, we get C 0 =G 0 C 1 =G 1 +G 0 P 1 C 2 =G 2 +G 1 P 2 +G 0 P 1 P 2 C 3 =G 3 +G 2 P 3 +G 1 P 2 P 3 +G 0 P 1 P 2 P 3 C 4 =G 4 +G 3 P 4 +G 2 P 3 P 4 +G 1 P 2 P 3 P 4 +G 0 P 1 P 2 P 3 P 4 etc. Autumn 2011CSE 31115 Carry-Look-Ahead Adder Compute all generate G i = a i b i [1,1] propagate P i =a i b i [0,1],[1,0] Then compute all: C 0 =G 0 C 1 =G 1 +G 0 P 1 C 2 =G 2 +G 1 P 2 +G 0 P 1 P 2 C 3 =G 3 +G 2 P 3 +G 1 P 2 P 3 +G 0 P 1 P 2 P 3 C 4 =G 4 +G 3 P 4 +G 2 P 3 P 4 +G 1 P 2 P 3 P 4 +G 0 P 1 P 2 P 3 P 4 etc. Finally, use these to compute Sum 0 = P 0 Sum 1 = P 1 C 0 Sum 2 = P 2 C 1 Sum 3 = P 3 C 2 Sum 4 = P 4 C 3 Sum 5 = P 5 C 4 etc If all C i are computed using 2-level logic, total depth is 4. Autumn 2011CSE 31116 Adders using Composition Carry-look-ahead circuit for carry C n-1 has n = (n+2)(n-1)/2 gates a lot more than ripple-carry adder circuit. Composition: (G,P) followed by (G,P) gives the same effect as (G,P) where G= G (G P) and P= P P also written as G= G + G P and P= PP Autumn 2011CSE Composition gives an alternative approach Adders using Composition Composition: (G,P) followed by (G,P) gives the same effect as (G,P) where G= G (G P) and P= P P also written as G= G + G P and P= PP Use this for the circuit component in transition function composition tree Computes C n-1 in depth 2 log 2 n and size n But we need all of C 0, C 1,..., C n-1 not just C n-1 Autumn 2011CSE Constant size 2-level Boolean logic to convert input symbol to bits for transition function compute composition of two transition functions Total depth 2 log 2 n and size n Autumn 2011 CSE fb5fb4fb5fb4 fb7fb6fb7fb6 b7b7 b6 b6 b4b4 b5b5 fb4fb4 fb6fb6 fb5fb5 fb7fb7 fb7fb6fb5fb4fb7fb6fb5fb4 fb1fb0fb1fb0 fb3fb2fb3fb2 b0b0 b1b1 b2b2 b3b3 fb0fb0 fb1fb1 fb2fb2 fb3fb3 fb3fb2fb1fb0fb3fb2fb1fb0 fb7fb6fb5fb4fb3fb2fb1fb0fb7fb6fb5fb4fb3fb2fb1fb0 b fbfb fg gfgf Transition Function Composition Computing all the values We need to compute all of f b 7 f b 6 f b 5 f b 4 f b 3 f b 2 f b 1 f b 0 Already computed f b 6 f b 5 f b 4 f b 3 f b 2 f b 1 f b 0 = f b 6 (f b 5 f b 4 ) (f b 3 f b 2 f b 1 f b 0 ) f b 5 f b 4 f b 3 f b 2 f b 1 f b 0 = (f b 5 f b 4 ) (f b 3 f b 2 f b 1 f b 0 ) f b 4 f b 3 f b 2 f b 1 f b 0 = f b 4 (f b 3 f b 2 f b 1 f b 0 ) f b 3 f b 2 f b 1 f b 0 Already computed f b 2 f b 1 f b 0 = f b 2 (f b 1 f b 0 ) f b 1 f b 0 Already computed f b 0 Already computed Autumn 2011CSE 31120 Parallel Prefix Circuit The general way of doing this efficiently is called a parallel prefix circuit Designed and analyzed by Michael Fischer and Richard Ladner (University of Washington) Uses the adder composition operation that sets G= G + G P and P= PP we just show it for the part for computing P which is a Parallel Prefix AND Circuit Autumn 2011CSE 31121 Parallel Prefix n/2 inputs The Parallel Prefix AND Circuit Parallel Prefix n/2 inputs P1P1 P n/2 P n/2+1 PnPn Parallel Prefix n inputs P1P1 P 1 P 2...P n/2 P 1 P 2...P n/2 P n/2+1 P 1 P 2...P n n/2 AND gates per level log 2 n levels P1P2P1P2 Parallel Prefix Adder Circuit depth 2 log 2 n Circuit size 4 n log 2 n Actual adder circuits in hardware use combinations of these ideas and more but this gives the basics Nice overview of adder circuits atAutumn 2011CSE 31123