September 16, 2003CMS Annual Review

1CSC Muon Trigger

Current Status of CSC Trigger Elements – Quick Summary

Jay Hauser, with many slides from Darin Acosta and Stan Durkin

On-chamber Comparator ASICs for Cathodes (CFEB cards) – DONE. ALCT Anode Trigger – almost done (~90%)

Peripheral-crate TMB Trigger Motherboard – pre-production prototypes MPC Muon Port Card – 2nd generation prototype CCB Clock & Control Board – 2nd generation prototype

Track Finder crate in counting house SP2002 Sector Processor – 2nd generation prototype CSC Muon Sorter – 1st generation prototype Backplane – 2nd generation prototype

September 16, 2003CMS Annual Review

2CSC Muon Trigger

CSC Muon Trigger Scheme

CSC

CFEBCFEBCFEB CFEB

ALCT1 of 24

CFEB

1 of 2

LVDB

1 of 5

1 of 5

Anode Front-end Board

Cathode Front-end Board

Anode LCT Board

MPC

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

CCBC

ONTROLLER

Peripheral Crate on iron disk (1 of 60)

Trigger Timing & Control

CSC Track-Finder Crate (1)

Trigger Motherboard (9)

DAQ Motherboard (9)Clock Control Board

Optical link

In underground counting room On detector

Muon Portcard (1)

EMU part: on-chamber nearing end of production, peripheral crate production > ESR in Nov. ‘03

TriDAS part: Second generation prototypes

Trigger Primitives

3-D Track-Finding and Measurement

Sector Processor (12)

Muon Sorter (1)

September 16, 2003CMS Annual Review

3CSC Muon Trigger

On-chamber CSC Trigger Electronics

Comparator ASICs – DONE. Compare pulse heights from

adjacent strips to find position of muon to ½-strip

15000 16-channel ASICS on CFEB boards (OSU)

ALCT Boards – nearly DONE. Finds tracks among anode

hits, stores data for readout 468+spares boards of 3 types

(288-, 384-, 672-channel)

ALCT Shipments By Destination (5-Sept-2003)

0

20

40

60

80

100

120

UC-FAST UF-FAST PNPI-FAST IHEP-FAST-384 IHEP-FAST-288 DUBNA-FAST SPARES-ALLTYPES

Number Left

Number Shipped

September 16, 2003CMS Annual Review

4CSC Muon Trigger

CSC Peripheral Crates in UXC55

MPC

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

DMB

TMB

CCB

CONTROLLER

Clock Control Board (CCB)

TRIG Motherboard (TMB)

DAQ Motherboard (DMB)

Crate Controller

Muon Port Card (MPC)

September 16, 2003CMS Annual Review

5CSC Muon Trigger

SP2002 (Main Board)

Merged 3 SR2000s

Optical Transceivers

•16 x 1.6 Gbit/s Links

Front FPGA

TLK2501 Transceiver

Phi Local LUT

Eta Global LUT

Phi Global LUT

VME/CCB

FPGA

To/from custom GTLP back-plane

Data conversion:

Receiver: Florida

12 Used in CMS System

September 16, 2003CMS Annual Review

6CSC Muon Trigger

SP Trigger Logic

From SP2000 to SP2002 mezzanine card (5 manufactured)

Xilinx Virtex-2 XC2V4000~800 user I/O

Performs track-finding logic and PT assignment

Florida

September 16, 2003CMS Annual Review

7CSC Muon Trigger

GTLP BACKPLANEINTERFACE

MEZZANINE CARD (same as SP design)

LVDSDRIVERSAND SCSI-3CONNECTORS

Muon Sorter

Rice

Sorts up to 36 muons from 12 SP’s and transmits best 4 to GMT Have 4 boards in hand, one stuffed (except for backplane interface) Sorter testing is in progress, will test with Track-Finder in the autumn Only 1 needed in CMS

September 16, 2003CMS Annual Review

8CSC Muon Trigger

CSC Test Beam Studies 2003 First structured beam period May 23-June 1

Trigger primitives tests were highly successful: Verified peripheral crate electronics design for Nov. ESR

MPC-to-SP optical link data transfer unsuccessful (synch. problems)

Unstructured beam period June 13-28 Improved low- and high-rate CLCT and TMB studies, angle scans

Second structured beam period Sept. 17-22 Patches to fix optical link data transfer from MPC to SP New readout shell program (fully OO software)

September 16, 2003CMS Annual Review

9CSC Muon Trigger

2003 Time-structured Beam Test Setup

Peripheral Crate2 DMB, 2 TMB1 CCB, 1 MPC

FED crate 1 DDU

PC

TTC crate

DAQ Data

Trigger primitives

S1 S2 S3

beam

CSC 1 CSC 2

Track finder Crate

TRIDAS

X5A Setup

September 16, 2003CMS Annual Review

10CSC Muon Trigger

CSC Bunch ID From ALCT Timing First, tune the ALCT data latching in 2 ns intervals (0-32ns)

and maximize the single-BX fraction of events:

Then look at the BX distribution relative to BX from scintillator (L1A):

ALCT BX efficiency 98.7%

September 16, 2003CMS Annual Review

11CSC Muon Trigger

CSC Trigger High Rate Tests

Expected LCT rate at LHC < 25 KHz (ME1/1)

data consistent with dead-time = 225 ns

Chamber #1 CLCT

0

500

1,000

1,500

2,000

0 500 1,000 1,500 2,000 2,500 3,000

Beam Intensity (KHz)

CL

CT

Ra

te (

KH

z)

September 16, 2003CMS Annual Review

12CSC Muon Trigger

CSC Track Finder Test

Successfully passed optical link loopback tests and MPCSP chain tests using 40 MHz crystal oscillator to drive system

MPCSP optical link tests failed at the structured beam tests in May 2003 (link errors every few ms)

Clock was derived from TTC system (mivivxrx) Combined clock jitter presumably too large to drive optical links PLL was not used to clean clock (i.e. QPLL was not available)

Sector Processor2 CSCs

September 16, 2003CMS Annual Review

13CSC Muon Trigger

Additional 2003 Test Beam Results (Later, unstructured beam period) Very high efficiencies achieved

Highest trigger efficiency of 99.9% required low rate (few kHz)

Improved DAQ throughput allowed readout up to 80k full events per spill. Typical “run” is 1 or 2 spills.

Improved scans taken: Logic scope read out on most data HV scan Comparator threshold scan Pattern requirements scan Angle scans

b

September 16, 2003CMS Annual Review

14CSC Muon Trigger

Sector Processor Clock Patch

Voltage Controlled Crystal Oscillator PLL Patch

• Low jitter Output

• Cleans Backplane clock to drive SP logic

• x2 BackPlane Clock supplies reference to TLK2501

LVDS Repeater Delivers Multiplied Clock to Front

FPGAs to Drive TLK2501 clock input

VCXO and PLL added to clean synchronous clock

September 16, 2003CMS Annual Review

15CSC Muon Trigger

SP Patch Results

Conditions Type of Test Time Errors

Patched CCB Clock, 100m fibers

SPSP loopback PRBS test 5 hours x 3 links 0

“ MPCSP PRBS test (within same TF crate)

24 hours x 3 links 0

TTCvx with 40.0787 MHz XO Patch

MPCSP PRBS test (within same TF crate)

32 hours x 3 links 0

“ MPC SP PRBS test (peripheral crate to TF crate) with L1A rate @ 100kHz.

14 hours x 3 links 0

Eagerly awaiting QPLL chips from CERN

September 16, 2003CMS Annual Review

16CSC Muon Trigger

Preparation for Sept. 2003 Beam Test

CSCs

Scintillator Panels

HV Supply

CCBMPC

DDU

Dynatem

TMB

DMB

SP

CCBSBS

TTCvi

TTCvx

Cosmic ray test stand in Florida

System brought to working order

(everything now shipped to CERN)

TF CratePeriph Crate

September 16, 2003CMS Annual Review

17CSC Muon Trigger

Conclusions The CSC system is in very good shape:

Chambers being mounted on disks at SX5 Majority of the chambers already built and tested, including on-

chamber electronics Test beam showed that CSC peripheral crate electronics work very

well under “battle conditions” Of course, much work remains:

We especially need to validate the optical link clocking for MPC-SP data transfer

Production starts soon for peripheral crate electronics Production planning will start soon for Track Finder (MPC, SP, MS)

boards