CSC-326 Transformer Protection IED Technical …...Preface Purpose of this manual This manual describes the functions, operation, installation, and placing into service of device CSC-326

CSC-326

Transformer Protection IED

Technical Application Manual

CSC-326 Transformer

Protection IED

Technical Application Manual

Compiled: Jin Rui

Checked: Hou Changsong

Standardized: Li Lianchang

Inspected: Cui Chenfan

Version： V1.01

Doc.Code：0SF.450.085(E)

Issued Date：2012.8.31

Version：V1.01

Doc. Code：0SF.450.085(E)

Issued Date：2012.8

Copyright owner: Beijing Sifang Automation Co., Ltd

Note: the company keeps the right to perfect the instruction. If equipment does not agree

with the instruction at anywhere, please contact our company in time. We will provide you

with corresponding service.

® is registered trademark of Beijing Sifang Automation Co., Ltd.

We reserve all rights to this document, even in the event that a patent is issued and a different commercial proprietary right is registered. Improper use, in particular reproduction and dis-semination to third parties, is not permitted.

This document has been carefully checked. If the user nevertheless detects any errors, he is asked to notify us as soon as possible.

The data contained in this manual is intended solely for the product description and is not to be deemed to be a statement of guaranteed properties. In the interests of our customers, we constantly seek to ensure that our products are developed to the latest technological stand-ards as a result; it is possible that there may be some differences between the hard-ware/software product and this information product.

Manufacturer: Beijing Sifang Automation Co., Ltd.

Tel: +86-10-62961515

Fax: +86-10-62981900

Internet: http://www.sf-auto.com

Add: No.9, Shangdi 4th Street, Haidian District, Beijing, P.R.C.100085

Preface

Purpose of this manual

This manual describes the functions, operation, installation, and placing into service of device CSC-326. In particular, one will find:

Information on how to configure the device scope and a description of the device functions and setting options;

Instructions for mounting and commissioning;

Compilation of the technical specifications;

A compilation of the most significant data for experienced users in the Appendix.

Target Audience

Protection engineers, commissioning engineers, personnel concerned with adjustment, checking, and service of selective protective equipment, automatic and control facilities, and personnel of electrical facilities and power plants.

Applicability of this Manual

This manual is valid for SIFANG Distance Protection IED CSC-326; firmware version V1.00 and higher

Indication of Conformity

Additional Support

In case of further questions concerning IED CSC-326 system, please contact SIFANG representative.

Safety information

Strictly follow the company and international safety regulations.

Working in a high voltage environment requires serious approch to

aviod human injuries and damage to equipment

Do not touch any circuitry during operation. Potentially lethal

voltages and currents are present

Avoid to touching the circuitry when covers are removed. The IED

contains electirc circuits which can be damaged if exposed to static

electricity. Lethal high voltage circuits are also exposed when covers

are removed

Using the isolated test pins when measuring signals in open circuitry.

Potentially lethal voltages and currents are present

Never connect or disconnect wire and/or connector to or from IED

during normal operation. Dangerous voltages and currents are

present. Operation may be interrupted and IED and measuring

circuitry may be damaged

Always connect the IED to protective earth regardless of the

operating conditions. Operating the IED without proper earthing may

damage both IED and measuring circuitry and may cause injuries in

case of an accident.

Do not disconnect the secondary connection of current transformer

without short-circuiting the transformer’s secondary winding.

Operating a current transformer with the secondary winding open will

cause a high voltage that may damage the transformer and may

cause injuries to humans.

Do not remove the screw from a powered IED or from an IED

connected to power circuitry. Potentially lethal voltages and currents

are present

Using the certified conductive bags to transport PCBs (modules).

Handling modules with a conductive wrist strap connected to

protective earth and on an antistatic surface. Electrostatic discharge

may cause damage to the module due to electronic circuits are

sensitive to this phenomenon

Do not connect live wires to the IED, internal circuitry may be

damaged

When replacing modules using a conductive wrist strap connected to

protective earth. Electrostatic discharge may damage the modules

and IED circuitry

When installing and commissioning, take care to avoid electrical

shock if accessing wiring and connection IEDs

Changing the setting value group will inevitably change the IEDs

operation. Be careful and check regulations before making the

change

Contents Chapter 1 Introduction ................................................................................................... 1

1 Overview .................................................................................................................... 2

2 Features ..................................................................................................................... 3

Chapter 2 Basic protection elements ............................................................................. 9

1 Startup element .........................................................................................................10

1.1 Introduction ..................................................................................................10

1.2 Sudden-change current startup element ......................................................10

1.3 Differential current startup element ..............................................................10

2 Input and output signals ............................................................................................ 11

3 Settings .....................................................................................................................13

4 Report .......................................................................................................................16

Chapter 3 Differential protection ...................................................................................17

1 Introduction ...............................................................................................................18

2 Applications...............................................................................................................18

3 Protection algorithm ..................................................................................................19

3.1 Differential and restraint current calculation .................................................20

3.2 Automatic Ratio compensation ....................................................................22

3.3 Automatic Vector group and zero sequence current compensation ..............26

4 Protection principle....................................................................................................32

4.1 Instantaneous differential protection characteristic .......................................32

4.2 Treble slope percent differential protection characteristic .............................34

4.3 Selective inrush stabilization schemes .........................................................37

4.3.1 2nd harmonic stabilization ...........................................................................38

4.3.2 Fuzzy recognition of inrush based on the waveform ....................................38

4.4 Overexcitation stabilization ..........................................................................40

4.5 CT Failure supervision .................................................................................42

4.6 CT Saturation supervision ............................................................................43

4.7 Differential current supervision.....................................................................44

5 Input and output signals ............................................................................................46

6 Settings .....................................................................................................................47

7 Report .......................................................................................................................50

8 Technical data ...........................................................................................................51

Chapter 4 Restricted earth fault protection ...................................................................53

1 Introduction ...............................................................................................................54

2 Applications...............................................................................................................54

3 Protection principle....................................................................................................56

3.1 Differential and restraint current calculation .................................................57

3.2 Automatic Ratio compensation ....................................................................59

3.3 Positive sequence current blocking ..............................................................61

3.4 Restricted earth fault current alarm ..............................................................62

4 Input and output signals ............................................................................................63

5 Settings .....................................................................................................................64

6 Report ...................................................................................................................... 66

7 Technical data ........................................................................................................... 67

Chapter 5 Overexcitation protection ............................................................................. 69

1 Introduction ............................................................................................................... 70

2 Protection principle ................................................................................................... 70

2.1 Protection principle ...................................................................................... 70

2.2 Voltage channel configuration ..................................................................... 76


4 Settings .................................................................................................................... 78

5 Report ...................................................................................................................... 79

6 Technical data ........................................................................................................... 80

Chapter 6 Overcurrent protection................................................................................. 83

1 Introduction ............................................................................................................... 84

2 Protection principle ................................................................................................... 84

2.1 Protection Elements .................................................................................... 84

2.2 Inrush Restraint Feature .............................................................................. 86

2.3 Direction Determination Feature .................................................................. 87

2.4 CBF initiation Feature ................................................................................. 90


4 Setting ...................................................................................................................... 92

5 Report ...................................................................................................................... 99

6 Technical data ........................................................................................................... 99

Chapter 7 Earth fault protection ................................................................................. 101

1 Protection principle ................................................................................................. 102

1.1 Protection elements .................................................................................. 102

1.2 Inrush Restraint Feature ............................................................................ 104

1.3 Direction Determination Feature ................................................................ 105

1.4 CBF initiation Feature ............................................................................... 107

2 Input and output signals .......................................................................................... 108

3 Setting .................................................................................................................... 109

4 Report .................................................................................................................... 115

5 Technical data ......................................................................................................... 116

Chapter 8 Neutral earth fault protection ..................................................................... 119


1.1 Protection Elements .................................................................................. 120

1.2 Inrush Restraint Feature ............................................................................ 122

1.3 Direction Determination Feature ................................................................ 122

1.4 CBF initiation Feature ............................................................................... 124


3 Setting .................................................................................................................... 126

4 Report .................................................................................................................... 132

5 Technical data ......................................................................................................... 133

Chapter 9 Thermal overload protection ...................................................................... 135

1 Introduction ............................................................................................................. 136

2 Protection principle.................................................................................................. 136


4 Setting ..................................................................................................................... 138

5 Report ..................................................................................................................... 140

6 Technical data ......................................................................................................... 141

Chapter 10 Overload protection ................................................................................... 143



3 Setting ..................................................................................................................... 146

4 Report ..................................................................................................................... 148

Chapter 11 Overvoltage protection ............................................................................... 149

5 Introduction ............................................................................................................. 150


6.1 Phase to phase overvoltage protection ...................................................... 150

6.2 Phase to earth overvlotage protection........................................................ 151

7 Logic diagram ......................................................................................................... 151


9 Setting ..................................................................................................................... 152

10 Report .............................................................................................................. 154

11 Technical data .................................................................................................. 154

Chapter 12 Circuit breaker failure protection ................................................................ 157

1 Introduction ............................................................................................................. 158


3 Logic diagram ......................................................................................................... 161


5 Setting ..................................................................................................................... 164

6 Report ..................................................................................................................... 167

7 Technical data ......................................................................................................... 167

Chapter 13 Dead zone protection ................................................................................. 169

1 Introduction ............................................................................................................. 170


2.1 Function description................................................................................... 171

3 Logic diagram ......................................................................................................... 171


5 Setting ..................................................................................................................... 173

6 Report ..................................................................................................................... 174

7 Technical data ......................................................................................................... 174

Chapter 14 STUB protection ........................................................................................ 175

1 Introduction ............................................................................................................. 176


2.1 Function description................................................................................... 176

3 Logic diagram ......................................................................................................... 177


5 Setting ..................................................................................................................... 178

6 Report .................................................................................................................... 180

7 Technical data ......................................................................................................... 181

Chapter 15 Poles discordance protection .................................................................... 183

1 Introdcution ............................................................................................................. 184


2.1 Function description .................................................................................. 184

3 Logic diagram ......................................................................................................... 185


5 Setting .................................................................................................................... 187

6 Report .................................................................................................................... 188

7 Technical data ......................................................................................................... 188

Chapter 16 Secondary system supervision .................................................................. 189

1 VT failure supervision function ................................................................................ 190

2 Function principle ................................................................................................... 190


4 Setting .................................................................................................................... 194

5 Report .................................................................................................................... 195

6 Technical data ......................................................................................................... 196

Chapter 17 External BIs to trip BOs ............................................................................. 197

1 Introduction ............................................................................................................. 198

2 Function principle ................................................................................................... 198

3 BI Trigger Record ................................................................................................... 199

4 BI Switch SetGroup ................................................................................................ 200

5 BI “Blk Rem Access” and “RELAY TEST” ................................................................ 200

6 BI “BI_Config1~ BI_Config2” and “BI TRIGGER DR1~ 10” ..................................... 201

7 Setting .................................................................................................................... 201

Chapter 18 Station communication .............................................................................. 203

1 Overview ................................................................................................................ 204

1.1 Protocol ..................................................................................................... 204

1.1.1 LON communication protocol ............................................................. 204

1.1.2 IEC61850-8 communication protocol .................................................. 204

1.1.3 IEC60870-5-103 communication protocol ........................................... 205

1.2 Communication port .................................................................................. 205

1.2.1 Front communication port ................................................................... 205

1.2.2 RS485 communication ports ............................................................... 205

1.2.3 Ethernet communication ports ............................................................ 205

1.3 Technical data ........................................................................................... 205

Front communication port .............................................................................................. 206

RS485 communication port ........................................................................................... 206

2 Typicalcommunication scheme ............................................................................... 208

2.1 Typical substation communication scheme ................................................ 208

2.2 Typical time synchronizing scheme ........................................................... 208

Chapter 19 Hardware .................................................................................................. 211

This chapter describes the IED hardware. ..................................................................... 211

3 Introduction ............................................................................................................. 212

3.1 IED structure ............................................................................................. 212

3.2 IED appearance ......................................................................................... 212

3.3 IED module arrangement ........................................................................... 213

3.4 The rear view of the protection IED ............................................................ 213

4 Local human-machine interface .............................................................................. 214

4.1 Human machine interface .......................................................................... 214

4.2 LCD ........................................................................................................... 215

4.3 Keypad ...................................................................................................... 215

4.4 Shortcut keys and functional keys .............................................................. 216

4.5 LED ........................................................................................................... 217

4.6 Front communication port .......................................................................... 218

5 Analog input module ............................................................................................... 219

5.1 Introduction ................................................................................................ 219

5.2 Terminals of Analogue Input Module (AIM) ................................................ 219

5.3 Technical data ............................................................................................ 220

5.3.1 Internal current transformer ................................................................. 220

5.3.2 Internal voltage transformer ................................................................ 221

6 Communication module .......................................................................................... 222

6.1 Introduction ................................................................................................ 222

6.2 Substaion communication port ................................................................... 222



6.2.3 Ethernet communication ports............................................................. 222

6.2.4 Time synchronization port ................................................................... 223

6.3 Terminals of Communication Module ......................................................... 223

6.4 Operating reports ....................................................................................... 224

6.5 Technical data ............................................................................................ 224

6.5.1 Front communication port ................................................................... 224

6.5.2 RS485 communication port ................................................................. 225

6.5.3 Ethernet communication port .............................................................. 225

6.5.4 Time synchronization .......................................................................... 226

7 Binary input module ................................................................................................ 227

7.1 Introduction ................................................................................................ 227

7.2 Terminals of Binary Input Module (BIM) ..................................................... 227

7.3 Technical data ............................................................................................ 229

8 Binary output module .............................................................................................. 230

8.1 Introduction ................................................................................................ 230

8.2 Terminals of Binary Output Module (BOM) ................................................. 230

8.2.1 Binary Output Module A ...................................................................... 230

8.2.2 Binary Output Module C ...................................................................... 233

8.3 Technical data ............................................................................................ 234

9 Power supply module .............................................................................................. 236

9.1 Introduction ................................................................................................ 236

9.2 Terminals of Power Supply Module (PSM) ................................................ 236

9.3 Technical data ........................................................................................... 238

10 Techinical data ................................................................................................. 239

10.1 Basic data ................................................................................................. 239

10.1.1 Frequency .......................................................................................... 239

10.1.2 Internal current transformer ................................................................ 239

10.1.3 Internal voltage transformer ................................................................ 239

10.1.4 Auxiliary voltage ................................................................................. 239

10.1.5 Binary inputs....................................................................................... 240

10.1.6 Binary outputs .................................................................................... 240

10.2 Type tests .................................................................................................. 241

10.2.1 Product safety-related Tests ............................................................... 241

10.2.2 Electromagnetic immunity tests .......................................................... 242

10.2.3 DC voltage interruption test ................................................................ 244

10.2.4 Electromagnetic emission test ............................................................ 244

10.2.5 Mechanical tests ................................................................................. 244

10.2.6 Climatic tests ...................................................................................... 245

10.2.7 CE Certificate ..................................................................................... 246

10.3 IED design ................................................................................................ 246

Chapter 20 Appendix ................................................................................................... 247

1 General setting list .................................................................................................. 248

1.1 Function setting list ................................................................................... 248

1.2 Binary setting list ....................................................................................... 266

2 General report list ................................................................................................... 288

3 Time inverse characteristic ..................................................................................... 295

3.1 11 kinds of IEC and ANSI inverse time characteristic curves ..................... 295

3.2 User defined characteristic ........................................................................ 296

4 CT Requirement ..................................................................................................... 296

4.1 Overview ................................................................................................... 296

4.2 Current transformer classification .............................................................. 296

4.3 Abbreviations (according to IEC 60044-1, -6, as defined) .......................... 297

4.4 General current transformer requirements ................................................. 298

4.4.1 Protective checking current ................................................................ 298

4.4.2 CT class ............................................................................................. 299

4.4.3 Accuracy class ................................................................................... 301

4.4.4 Ratio of CT ......................................................................................... 301

4.4.5 Rated secondary current .................................................................... 301

4.4.6 Secondary burden .............................................................................. 302

4.5 Rated equivalent secondary e.m.f requirements ........................................ 302

4.5.1 Transformer differential protection ...................................................... 303

Chapter 1 Introduction

1


About this chapter This chapter gives an overview of SIFANG transformer pro-

tection IED.


2

1 Overview

It is selective, reliable and high speed IED (Intelligent Electronic Device)

for transformer protection with powerful capabilities to cover following

applications:

For large and medium two- or three-winding transformers, and au-

totransformer

Used in a wide range of voltage levels, up to 1000kV

For single or multi-breaker arrangement

Up to 7 three-phase sets of CTs input (special ordering)

Work as main protection unit only or full functions unit for the

complicated application

Communication with station automation system

The IED is able to provide all main protection functions and backup pro-

tection functions in one case, including differential protection, restricted

earth fault (REF), overexcitation, thermal overload, overcurrent, earth

fault protection, etc.

The integrated flexible logic make the IED suitable to be applied to (au-

to)transformers with all the possible vector groups, with/without earthing

connection inside the protected zone.

The wide application flexibility makes the IED an excellent choice for both

new installations and retrofitting of the existing stations.

.


3

2 Features

Protection and monitoring IED with extensive functional library, user

configuration possibility and expandable hardware design to meet with

user’s special requirements

Inter-lock between two CPU modules, avoiding mal-operation due to

internal severe fault of one module

Transformer differential protection (87T)

Treble slope percent differential protection

Automatic CT ratio matching

Automatic vector group and zero sequence current compensation

Settable 2nd harmonic restraint function for transformer inrush

Fuzzy waveform recognition restraint function for transformer

inrush

3rd or 5th harmonic restraint for overexcitation

CT saturation detection

CT secondarycircuit supervison

Differential current alarm

Restricted earth fault protection (87N)

Two slope percent REF protection

Automatic CT ratio matching

CT saturation recognition

REF differential current supervision

Positive sequence current blocking

A complete protection functions library, include:


4

Transformer differential protection (87T)

Restricted earth fault protection (87N)

Overcurrent protection (50, 51, 67)

Earth fault protection (50N, 51N, 67N)

Neutral earth fault protection (50G, 51G, 67G)

Thermal overload protection (49)

Overload protection (50OL)

Delta winding overload protection (50OL)

Overexcitation protection (24)

Overvoltage protection (59)

Circuit breaker failure protection (50BF)

Poles discordance protection (50PD)

Dead zone protection (50SH-Z)

Voltage transformer secondary circuit supervision (97FF)

Current transformer secondary circuit supervision

2 sets external trip commands (BIs → BOs)

Self-supervision to all modules in the IED

Complete information recording: tripping reports, alarm reports,

startup reports and general operation reports. Any kinds of reports can

be stored up to 2000 and be memorized in case of power

disconnection

Up to three electric /optical Ethernet ports can be selected to

communicate with substation automation system by IEC61850 or

IEC60870-5-103 protocols

Up to two electric RS-485 ports can be selected to communicate with


5

substation automation system by IEC60870-5-103 protocol

Time synchronization via network(SNTP), pulse and IRIG-B mode

Configurable LEDs and output relays satisfied users’ requirement

Versatile human-machine interface

Multifunctional software tool CSmart/CSPC for setting, monitoring,

fault recording analysis, configuration, etc.


6

Protection functions

Description ANSI Code

IEC 61850

Logical Node

Name

IEC 60617

graphical symbol

Differential protection

Transformer differential protection 87T PDIF

Restricted earth fault protection 87N PDIF

Current protection

Overcurrent protection 50,51,67 PTOC

3IINV>

3I >>

3I >>>

Earth fault protection 50N, 51N, 67N PEFM

I0INV>

I0>>

I0>>>

Neutral earth fault protection 50G, 51G, 67G

Thermal overload protection 49 PTTR Ith

Overload protection 50OL PTOC 3I >OL

Delta Winding Overload Protection 50OL

Voltage protection

Overexcitation protection 24 PVPH U/f>

Overvoltage protection 59 PTOV 3U>

3U>>

Breaker protection and control function

Breaker failure protection 50BF RBRF

3I> BF

I0>BF

I2>BF

Dead zone protection 50SH-Z

Poles discordance protection 50PD RPLD

3I< PD

I0>PD

I2>PD

Secondary system supervision

CT secondary circuit supervision

VT secondary circuit supervision

Other functions

2 sets external trip commands (BIs →

BOs)


7

Monitoring functions

Description

Auxiliary contacts of circuit breaker supervision

Self-supervision

Fault recorder

Station communication

Description

Front communication port

Isolated RS232 port

Rear communication port

0-2 isolated electrical RS485 communication ports

0-3 Ethernet electrical/optical communication ports

Time synchronization port

Communication protocols

IEC 61850 protocol

IEC 60870-5-103 protocol

Digital communication network through converter

IED software tools

Functions

Reading measuring value

Reading IED report

Setting

IED testing

Disturbance recording analysis

IED configuration

Printing


8

Chapter 2 Basic protection elements

9


About this chapter

This chapter describes basic protection elements including

startup elements, phase selectors and directional elements.


10

1 Startup element

1.1 Introduction

Startup elements are designed to detect a faulty condition in the power

system and initiate all necessary procedures for selective clearance of

the fault. The main startup element of CSC-326 is current

sudden-change startup element(abrupt current), the backup startup

element is diffrential current startup elment.

Startup element includes:

Current sudden-change startup element(abrupt current)

differential current startup element

1.2 Sudden-change current startup element

Sudden-change current startup element is the main startup element that

can sensitively detect most of faults. Its criteria are as followings:

_

( ) 2 ( ) ( 2 )

startupi I

i i t i t T i t T

where

I_startup is a fix threshold value(IQd =0.2A when the secondary

value of CT is 1A, and IQd =1A when secondary value of CT is 5A)

1.3 Differential current startup element

max _

max

_

, , ,

0.8 _

d diff startup

d d

diff startup

I I

I Max I a b c

I I percent diff

where


11

I_diff startup is the startup threshold of differential protection,

I_Percent Diff is a setting value, and Idφis the phase differential current.

2 Input and output signals

IA1

IB1

IC1

IA2

IB2

IC2

IA3

IB3

IC3

IA4

IB4

IC4

Relay Startup

IA5

IB5

IC5

Sudden-change current

startup element

Figure 1 Sudden-change current startup element


12

IA1

IB1

IC1

Differential current

startup element

IA2

IB2

IC2

IA3

IB3

IC3

IA4

IB4

IC4

Relay Startup

IA5

IB5

IC5

Figure 2 Differential current startup element

Table 1 Analog input list

Signal Description

IA1 Phase A current input of 1st CT set

IB1 Phase B current input of 1st CT set

IC1 Phase C current input of 1st CT set

IA2 Phase A current input of 2nd CT set

IB2 Phase B current input of 2nd CT set

IC2 Phase C current input of 2nd CT set

IA3 Phase A current input of 3th CT set

IB3 Phase B current input of 3th CT set

IC3 Phase C current input of 3th CT set







13

Signal Description


Table 2 Binary output list

Signal Description

Relay Startup Relay Startup

3 Settings

Table 3 Settings of basic protection element

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

HV Wind Conn/Y

0 1 0 Connection for HV winding,

0:wye connection, 1:delta

connection

MV Wind Conn/Y

0 1 0 Connection for MV winding,


connection

LV Wind Conn/Y

0 1 1 Connection for LV winding,


connection

Vet Grp Angle MVA 1.000 3000. 120.0 Vector Group Angle( VET

GRP ANGLE)

SN kV 1.000 1000. 220.0 Capacity of the transformer

HV VT Ratio MVA 1.000 9999. 2200.0 Voltage transformer(VT) Ra-

tio in HV side

HV CT Pri A 50.00 9999. 1200.0 CT Primary(PRI) current in

HV side

HV CT Sec A 1.000 5.000 1.0 CT Secondary(SEC) current

in HV side

HV Voltage Chan

Sel

1 3 1 HV voltage channel location

MV Voltage Chan

Sel

1 3 2 MV voltage channel loca-

tion


14

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

HV NCT Pri(REF)

A 50.00 9999. 1200.0 Neutral CT (NCT) Prima-

ry(PRI) current in HV side

for REF

HV NCT Sec(REF)

A 1.000 5.000 1.0 Neutral CT (NCT) Second-

ary(SEC) current in HV side

for REF

HV NCT Pri(BU)



for backup protection

HV NCT Sec(BU)


ary(PRI) current in HV side


MV UN kV 1.000 1000. 110.0 Nominal voltage (UN) in

Middle voltage (MV)side

MV VT Ratio 1.000 9999. 1100.0 Voltage transformer(VT) Ra-

tio in MV side

MV CT Pri A 50.00 9999. 1200.0 CT Primary(PRI) current in

MV side

MV CT Sec A 1.000 5.000 1.0 CT Secondary(SEC) current

in MV side

MV NCT Pri(REF)


ry(PRI) current in MV side

for REF

MV NCT Sec(REF)


ary(SEC) current in MV

side for REF

MV NCT Pri(BU)




MV NCT Sec(BU)


ary(PRI) current in MV side


LV UN kV 1.000 1000. 10.50 Nominal voltage (UN) in Low

voltage (LV)side

LV VT Ratio 1.000 9999. 105.0 Voltage transformer(VT) Ra-

tio in LV side


15

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

LV CT Pri A 50.00 9999. 3000.0 CT Primary(PRI) current in

LV side

LV CT Sec A 1.000 5.000 1.0 CT Secondary(SEC) current

in LV side

LV Sec Inside

Delta

A 1.000 5.000 1.0 CT Secondary(SEC) cur-

rent in LV inside delta

HV Rated Cur Pri

A 0 9999 Rated primary current for

HV side (calculated value,

read only)

HV Rated Cur Sec

A 0 9999 Rated secondary current for


read only)

Ratio Factor KTAH

0 9999 HV ratio factor for differen-

tial protection (calculated

value, read only)

Ratio Factor KTAM

0 9999 MV ratio factor for differen-


value, read only)

Ratio Factor KTAL

0 9999 LV ratio factor for differential

protection (calculated

value, read only)

Ratio REF KTAH

0 9999 HV ratio factor, with ze-

ro-sequence current calcu-

lated, for REF protection

(calculated value, read

only)

Ratio REF KNH

0 9999 HV ratio factor with ze-

ro-sequence current directly

measured, for REF protec-

tion (calculated value,

read only)

Ratio REF KTAM

0 9999 MV ratio factor, with ze-




only)


16

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

Ratio REF KNM

0 9999 MV ratio factor with ze-




read only)

Table 4 Binary settings of basic protection

Setting Unit Min. Max. Default

setting Description

Auto Trans 0 1 0

Autotransformer not comm

on transformer

1-autotransformer ;

0- not autotransformer

Two-Wind Trans

0 1 0

Two-winding(TWO WIND )

not three -winding trans-

former (TRANS)

1-two-winding trans;

0-three-winding trans

CT Fail Detect 0 1 0

VT Failure Detection On/Off

1-On, 0-Off.

4 Report

Table 5 Event report list

Information Description

Relay startup The relay is initiated by startup elements

Chapter 3 Differential protection

17


About this chapter This chapter describes the protection principle, input and

output signals, parameter, IED report and technical data for

differential protection function.


18

1 Introduction

The numerical current differential protection represents the main protec-

tion function of the IED. It provides a fast short-circuit protection for

power transformers. The protected zone is selectively limited by the CTs

at its ends. The device is able to perform this function on 2 or 3 winding

transformers in a variety of voltage levels and protected object types.

2 Applications

The IED provides numerical differential protection function which can be

used to protect power transformers in various configurations. For exam-

ple, it is possible to use it for a two-winding transformer, three-winding

transformer as well as auto-transformer. Examples for some of applica-

tions are illustrated in the below figure.

A

B

C

HV LV1.AI

1.BI

1.CI

a

b

c

2.aI

2.bI

2.cI

CSC-326

Figure 3 Application of differential protection on a two-winding Yd

transformer

a

b

c

2.aI

2.bI

2.cI

A

B

C

CSC-326

1.AI

1.BI

1.CI


19

Figure 4 Application of differential protection on an auto

transformer

A

B

C

HV

a

b

c

LV

CSC-326

1.AI

1.BI

1.CI

2.aI

2.bI

2.cI

Figure 5 Application of differential protection on a two-winding Yd

transformer with earthing transformer inside the protected zone

A

B

C

HV

LV

1.AI

1.BI

1.CI

a

b

c

3.aI

3.bI

3.cI

CSC-326

a

b

c

2.aI

2.bI

2.cI

MV

Figure 6 Application of differential protection on a three-winding

Ydd transformer

3 Protection algorithm

This section describes basic principle of differential protection function.


20

First, the case of a single phase transformer with two windings is con-

sidered. The basic principle is based on current comparison at two sides

of the protected object. Indeed, the differential protection function makes

use of the fact that a protected object carries always the same current at

its two sides in healthy operation condition. This current flows into one

side of the protected object and leaves it from the other side. A difference

in currents is an indication of a fault within this section. An example of this

condition is shown in below figure, when a fault inside the protected zone

causes a current I1prim. + I2prim. flowing in from both sides of the protected

object.

Protected Zone

CT-1 CT-2

Protected

Transformer

CSC-326

I1-prim. I2-prim.

I2I1

Figure 7 Basic principle of differential protection for two ends

(single phase)

For protected objects with three or more sides, the basic principle is ex-

panded in that the total of all currents flowing into the protected object is

zero in healthy operation, whereas in case of a fault the total in-flowing

current is equal to the fault current.

When an external fault causes a heavy current to flow through the pro-

tected transformer, differences in the magnetic characteristics of the

current transformers CT-1 and CT-2 under saturation condition may

cause a significant difference in the secondary currents I1 + I2 connected

to IED. If the difference is greater than the pickup threshold, the differen-

tial protection function can trip even though no fault occurred in the pro-

tected zone. To prevent the protection function from such erroneous op-

eration, a restraint (stabilizing) current is brought in. For differential pro-

tection IED, the restraint current is normally derived from the I1 and I2.

The next subsection goes on to demonstrate how the differential and re-

straint currents are calculated.

3.1 Differential and restraint current calculation


21

The differential current Idiff and the restraining current Ires are calculated

by the following equation. The following definitions apply for each phase

of the protected object.

1

1

(max)

1

)(2

1N

i

ijres

N

i

idiff

jiIII

II

Equation 1

Where iI is the current vector of side i, corresponding to HV, MV and LV

windings; N is total current inputs of the IED. In other words, it is number

of the protected object sides; (max)I j

is the maximum current vector

among the N current inputs of the IED, suppose it is side j; 1

( )1

NI i ji

i

is

the sum of the other current inputs of the IED, not including side j. Idiff is

derived from the fundamental frequency current and produces the trip-

ping effect quantity, whereas Ires counteracts this effect. To clarify the

situation, three important operating conditions with ideal and matched

measurement qualities are examined.

(a) External fault under undisturbed conditions:

I1 flows into the protected zone, I2 leaves the protected zone, i.e. is

negative according to the definition of signs, therefore I2 = –I1.

Idiff = I1 + I2 = I1 – I1 = 0

Ires = 0.5×| I1 - (–I1) | = 0.5×|2I1| = |I1|

No tripping effect (Idiff = 0); the restraint (Ires) corresponds to the exter-

nal fault current flowing through the protected object.

(b) Internal fault, fed with equal currents from both sides:

The following applies I2 = I1

Idiff = I1 + I2 = I1 + I1 = 2 I1

Ires = 0.5×| I1 - I1| = 0


22

Tripping effect (Idiff) corresponds to double the fault current, and restraint

value (Ires) are equal to zero.

(c) Internal fault, fed from one side only:

The following applies when assuming I2 = 0

Idiff = I1 + I2 = I1 + 0 = I1

Ires = 0.5×|I1 - I2| =0.5× |I1 - 0| = 0.5×|I1|=0.5 I1

Tripping quantity (Idiff) and restraint quantity (Ires) are equal and corre-

spond to the single-sided fault current.

The results show that the device is capable to properly discriminate in-

ternal and external faults by using the definitions proposed for differential

and restraint current. However, the device is still subjected to some in-

fluences that induce differential currents even during normal operation

condition. These influences should be compensated in appropriate

manners. The specific treatments designed to cope with these influences

includes automatic ratio compensation and automatic vector group

compensation which are explored in the next subsections.

3.2 Automatic Ratio compensation

Differential protection of power transformers represents some problems

in the application of current transformers. CTs should be matched to the

current rating of each transformer winding, so that normal current through

the power transformer is equal on the secondary side of the CT on dif-

ferent windings. However, because only standard CT ratios are available,

this matching may not be exact. As a result, the secondary currents of the

current transformers are not generally equal when a current flows

through the power transformer. The difference between the currents

flowing through CTs’ secondary circuit depends on the transformation ra-

tio of the protected power transformer, as well as the rated currents of the

current transformers. Therefore, the currents should be matched in order

to become comparable. To do so, the input currents of the IED are con-

verted in relation to the power transformer rated currents. This is

achieved by entering the characteristic values of the power transformer

(i.e. rated apparent power and rated voltages) and primary rated currents

of CTs into the IED by using user-entered settings. As a result, matching

to various power transformer and current transformer ratios is performed

purely mathematically inside the device. Therefore, no external matching


23

transformer is required. In this context, the rated primary current of each

side, I1N, is calculated automatically according to below equation.

N

NN

U

SI

1

13

Equation 2

Where SN is rated apparent power of the transformer and U1N is rated

voltage of the corresponding side.

The rated secondary current of each side, I2N, is then calculated.

CT

NN

n

II 1

2

Equation 3

Rated secondary current of the high voltage side is then taken as the

reference current. The currents of the other sides are automatically

matched to the rated current of the high voltage side by calculation of

correction factor KCT for MV and LV side, according to below equations,

respectively:

HVCT

MVCT

HVN

MVN

HVCT

MVCT

MVNN

HVNN

MVCTMVN

HVCTHVN

MVN

HVNMVCT

n

n

U

U

n

n

US

US

nI

nI

I

IK

1

1

1

1

1

1

2

2

3/

3/

/

/

Equation 4

HVCT

LVCT

HVN

LVN

HVCT

LVCT

LVNN

HVNN

LVCTLVN

HVCTHVN

LVN

HVNLVCT

n

n

U

U

n

n

US

US

nI

nI

I

IK

1

1

1

1

1

1

2

2

3/

3/

/

/

Equation 5

Where KCT-MV is the correction factor for middle voltage side and

KCT-LV is the correction factor for Low voltage side,


24

I1N is the primary rated current of the transformer (I1N-HV for high volt-

age side, I1N-MV for middle voltage side and I1N-LV for low voltage

side),

I2N is the secondary rated current of the transformer (I2N-HV for high

voltage side, I2N-MV for middle voltage side, I2N-LV for low voltage

side),

nCT is CT ratio of the transformer (nCT-HV for high voltage side, nCT-MV

for middle voltage side, nCT-LV for low voltage side),

U1N is rated voltage of the transformer (U1N-HV for high voltage side,

U1N-MV for middle voltage side, U1N-LV for low voltage side).

As mentioned previously, all of the calculations are automatically per-

formed inside the IED by its CPU. The related settings can be found

under the menu “Test Menu”.

Below figure shows an example of automatic ratio compensation in case

of a two-winding transformer. The primary nominal currents of the HV and

LV sides, (I1N = 402A, I2N= 1466A) are calculated from the rated ap-

parent power of the transformer (160MVA) and the nominal voltages of

each side (230kV and 63kV). Since the nominal currents of the current

transformers deviate from the nominal currents of the power transformer

sides, the secondary current of LV side is multiplied with the factor

KCT-LV. Subsequent to this matching, equal current magnitudes are

achieved at both sides under nominal conditions of the power transform-

er.

CTRATIO=500/1A

SN=160MVA

CTRATIO=2000/1A

U1N-LV=63kVU1N-HV=230kV

Figure 8 Example of automatic ratio compensation in a two-winding

transformer

1

160402

3 230N HV

MVAI A

An

II

CT

HVNHVN 804.0

500

40212


25

AMVA

I LVN 1466633

1601

AI LVN 733.02000

14662

097.1733.0

804.0LVCTK

Concerning three-winding power transformers, the windings may have

different power ratings. In order to compare secondary currents in an

appropriate manner, all currents are matched to the rated secondary

current of HV winding having highest power rating. This apparent power

is nominated as the rated apparent power of the transformer.

Below figure shows an example of a three-winding power transformer.

HV winding and MV winding are rated for 160MVA. The rated primary

and secondary currents of these windings are calculated as shown in

previous example. However, the LV winding has 25MVA rating (e.g. for

auxiliary supply). The rated current of this winding may result in 721A.

However, differential protection has to process comparable currents.

Therefore, the currents of LV winding should be referred to the rated

apparent power of the transformer, i.e. 160MVA. This results in a rated

current of 4619A. This is the base value for the LV winding, which should

be further multiplied by KCT-LV to be used in calculation process of dif-

ferential protection.

CTRATIO=2000/1A

160MVA 160MVA

25MVA

CTRATIO=500/1A

CTRATIO=2500/1A

U1N-MV=63kVU1N-HV=230kV

U1N-LV=20kV

Figure 9 Example of automatic ratio compensation in a

three-winding transformer

AMVA

I LVN 4619203

1601

An

II

CT

LVNHVN 848.1

2500

461912

435.0848.1

804.0LVCTK


26

If a three-winding transformer with a delta LV winding (with no CB in-

stalled) is used to supply substation LVAC loads, it may be desired that

LV current should not be integrated in differential protection. In this case,

Binary setting “Diff Includes LV Cur” is used to select whether LV current

should be included in differential protection calculation procedure or not.

By applying setting “Diff Includes LV Cur” to 0, only HV and MV currents

would be included in differential protection calculation. On the contrary,

when a three-winding transformer is equipped with three CBs in its sides,

it may be desired to include LV current in differential protection. This can

be achieved by applying setting “Diff Includes LV Cur” to 1 to respective

Binary setting.

3.3 Automatic Vector group and zero sequence

current compensation

Transformers have different vector groups, which cause a shift of the

phase angles between the primary and the secondary side. Without ad-

equate correction, this phase shift would cause a false differential current.

Furthermore, the conditioning of the starpoint(s) of the power transformer

has a great impact on the resulting differential current during through fault

currents.

The IED removes this problem. To do so, all CTs at the power trans-

former are connected Wye (polarity markings pointing away from the

transformer). User-entered settings in the relay are then used to char-

acterize the power transformer and allow the relay to automatically per-

form all necessary phase angles, and zero sequence compensation. This

section describes the procedures that perform this compensation inside

the relay and produce the required calculated quantities for transformer

differential protection. The phase angle compensation as well as zero

sequence current elimination procedure is performed by programmed

coefficient matrices which are capable to simulate the difference in phase

angle of currents flowing through transformer windings. Thus, compen-

sation is possible for the entire commonly used transformer vector

groups. This simplifies application of the IED in various configurations, if

the setting corresponding to vector Group Angle, “Vet Grp Angle”, is

properly entered into the device, together with the settings for connection

type of transformer windings in each side, “HV WIND CONN/Y-0 D-1”,

“MV WIND CONN/Y-0 D-1”, “LV WIND CONN/Y-0 D-1”, which could be

set to 1-delta or 0-wye. The basic principle of numerical vector group and

zero-sequence compensation is shown through some examples. A

through review of all possible connection groups as well as device


27

treatment in each case is explored in Appendix.

(1). Take example for Yy0 connection, including similar ones of Yy0

(separate or auto-connected windings), YNy0, Yyn0, YNyn0 (separate or

auto-connected windings) and so on. Below figure shows an example in

case of Yy0 connection group with no earthed starpoint. The figure

shows the windings (left) and the vector diagrams of symmetrical cur-

rents (right).

Yy0

C

c

A B

a b

A

BC

a

c b

Figure 10 Vector Group and zero sequence compensation for Yy0

transformer

The equations including the coefficient matrix are as follow:

1 -1 01

0 1 -13

-1 0 1

A A

B B

C C

I I

I I

I I

Equation 6

1 -1 01

0 1 -13

-1 0 1

a a

b b

c c

I I

I I

I I

Equation 7

According to these matrices, if we deduct side 1 currents BA II , the re-


28

sulting current AI has the same direction as AI on side 2. Multiplying it

with 31 , matches the absolute value. The matrices describe the con-

version for all three phases. Using these matrices, the elimination of zero

sequence currents are warranted regardless of starpoint earth connec-

tion.

As mentioned previously, the two above equations can be used similarly

for auto-transformers, as the auto-connected windings in au-

to-transformers can only be connected Y(N)y(n)0. If the starpoint is

earthed, both the auto-connected HV and LV windings are affected. The

zero sequence components in current flowing through both sides of the

transformer are then coupled because of the common starpoint. These

zero sequence components are eliminated by the application of the ma-

trices presented in the above equations.

(2). Take example for Yd1 connection, including similar ones of Yd1 and

YNd1 without earthing transformer installed at delta side. Below figure

shows an example in case of Yd1 connection group with no earthed

starpoint.

Yd1

A B C

a cb

BC

c

A

b

a

Figure 11 Vector Group compensation for Yd1 transformer

The equation including the coefficient matrix is as follows:

1 0 -11

-1 1 03

0 -1 1

A A

B B

C C

I I

I I

I I


29

Equation 8

If an earthing transformer/reactor is installed inside the protected zone on

delta side, the IED should be informed about it by Binary setting “HV

D_side Eliminate I0”, “MV D_side Eliminate I0” or “LV D_side Eliminate

I0”. The Binary setting related to delta side with earthing connection

should be set to “1-eliminate” in such condition. By taking example for

Yd1 connection with earthing transformer installed at delta side, Binary

setting “LV D_side Eliminate I0” is set to “1-eliminate”, and thus, device

performs a zero sequence current elimination on delta side. In this case,

the equations including the coefficient matrices are as follow:

1 0 -11

-1 1 03

0 -1 1

A A

B B

C C

I I

I I

I I

Equation 9

c

b

a

c

b

a

I

I

I

I

I

I

.

211

121

112

.3

1

Equation 10

(3). Take example for Ydd3 connection, including similar ones of Ydd3

and YNdd3 without earthing transformer installed at delta sides. Below

figure shows an example in case of Ydd3 connection group with no

earthed starpoint in Wye side.


30

Ydd3

A B C

ac b

BC

c(c’)

A

b(b’)

a(a’)

a'c' b'

Figure 12 Vector Group compensation for Ydd3 transformer


0 1 -11

-1 0 13

1 -1 0

A A

B B

C C

I I

I I

I I

Equation 11

(4). Take example for Yd5 connection, including similar ones of Yd5 and

YNd5 with earthing transformer installed at delta side. Below figure

shows an example in case of Yd5 connection group with no earthed

starpoint.

Yd5

A B C

c ba

BC

b

A

a

c


31

Figure 13 Vector Group compensation for Yd5 transformer

By setting binary setting “LV D_side Eliminate I0” to “1-eliminate”, the

equations including the coefficient matrices are as follow:

-1 1 01

0 -1 13

1 0 -1

A A

B B

C C

I I

I I

I I

Equation 12

c

b

a

c

b

a

I

I

I

I

I

I

.

211

121

112

.3

1

Equation 13

(5). Take example for Dy1 connection, including similar ones of Dy1 and

Dyn1 without earthing transformer installed at delta side. Below figure

shows an example in case of Dy1 connection group with no earthed

starpoint.

Dy1

A B C

a b c

BC

c

A

b

a

Figure 14 Vector Group compensation for Dy1 transformer



32

1 -1 01

0 1 -13

-1 0 1

a a

b b

c c

I I

I I

I I

Equation 14

If an earthing transformer/reactor is installed inside the protected zone on

delta side, binary setting “HV D_side Eliminate I0” is set to “1-eliminate”,

and thus, device performs a zero sequence current elimination on delta

side. In this case, the equations including the coefficient matrices are as

follow:

C

B

A

C

B

A

I

I

I

I

I

I

.

211

121

112

.3

1

Equation 15

1 -1 01

0 1 -13

-1 0 1

a a

b b

c c

I I

I I

I I

Equation 16

Subsequent to application of the magnitude, vector group and zero se-

quence compensation, the IED use the following calculated quantities

(per phase) to discriminate between internal and external faults: funda-

mental component of differential and restraint currents together with in-

stantaneous value, 2nd and 5th harmonic contents of differential current.

The following sections go on to demonstrate the fault recognition criteria

using these derived quantities.

4 Protection principle

4.1 Instantaneous differential protection

characteristic


33

An instantaneous (unrestrained) differential characteristic which entails

an overcurrent protection is provided for fast tripping on heavy internal

faults. The characteristics can be enabled or disabled by using Binary

setting “Func_Inst Diff” (1-on, 0-off). If setting “1-on” is selected, a trip

signal is issued regardless of the magnitude of the restraining current, as

soon as the differential current rises above the threshold ID>> (setting "

I_Inst Diff "). The generated trip signal is phase selective. it means that

the device issues event reports “Inst Diff Trip A”, “Inst Diff Trip B” or “Inst

Diff Trip C”, when the calculated differential current in phase A, B or C

exceeds the threshold ID>> (setting " I_Inst Diff "). The purpose of this

stage of differential protection is extremely fast operation in case of high

magnitude internal fault currents. This is always the case when the short

circuit current is higher than IN/Uk%, which indicates a fault inside the

power transformer. It should be noted that the magnitude of through fault

currents are always lower than IN/Uk%, when they are supplied via

power transformer. （In this equation, IN is nominal current and Uk% is

short circuit voltage of the power transformer.）

The logic diagram of instantaneous differential protection is shown in

below figure.

Func_Inst Diff On

Ia>I_Inst Diff

INST DIFF TripAAND

Ib>I_Inst Diff

Ib>I_Inst Diff

AND

AND

INST DIFF TripB

INST DIFF TripC

Figure 15 Tripping logic of the instantaneous differential protection

As mentioned previously and can be seen from the figure, the stage op-

erates as an unrestrained protection function. In other words, it is not in-

hibited by any of harmonic stabilization features of the percent differential

element as well as the CT failure detection. This means that it can oper-

ate even when, for example, a considerable second harmonic is present

in the differential current, which is caused by current transformer satura-

tion by a DC component in the fault current, and which could be inter-

preted by the inrush inhibit function as an inrush current.


34

This high current stage evaluates the fundamental component of the dif-

ferential current as well as the instantaneous values. Instantaneous value

processing ensures fast tripping even in case the fundamental compo-

nent of the current is strongly reduced by current transformer saturation.

Fast trip area is shown in Figure 16.

4.2 Treble slope percent differential protection

characteristic

The percent differential protection uses a treble-slope dual break-point

operating characteristic with magnetizing inrush and overexcitation and

CT failure detection inhibits integrated. The treble slope characteristics

can be enabled or disabled by using Binary setting “Func_Percent Diff”

(1-on, 0-off). If setting 1-on is selected, the stage calculates differential

and restraint current separately in each phase to obtain operating point in

each operation condition. The derived point is then mapped into Idiff-Ires

plane to examine whether it lies in trip or block area which is defined

according to predefined operating characteristic. The operation charac-

teristic is shown in below figure.

I_ResPoint1 Diff

I_Percent Diff

IDiff

IRest

Restraint current

Dif

fere

nti

al c

urr

ent

Slope 3

Slope 2

Slope 1

Trip area

block area

I_Inst Diff

Fast trip area

I_ResPoint2 Diff

Figure 16 Differential protection characteristics for transformers

In this characteristic, branch 1 represents the sensitivity threshold of the

differential protection. The setting of ID> (setting "I_Percent Diff") defines

the minimum differential current required for operation. The setting is

chosen based on the amount of differential current that might be seen

under normal operating conditions which corresponds to constant error

currents such as magnetizing currents and CT errors under no-load con-


35

ditions. The setting for slope of branch 1 is applicable for restraint cur-

rents of zero to the first break-point indicated on restraint axis (setting

"I_ResPoint1 Diff"). The slope (setting “Slope1_Diff”) defines the ratio of

differential to restraint current above which the percent differential stage

will operate. The first break-point on restraint axis defines the end of the

slope 1 region and the start of the second branch region. This setting

should be set just above the maximum operating current level of the

transformer. This level is somewhere between the maximum

forced-cooled rated current of the transformer and the maximum emer-

gency overload current level.

Branch 2 considers current-proportional errors which may result from

transformation errors of the main CTs or the input CTs of the relay. This

may also contain the error caused by the influence of tap changers in

power transformers with voltage control. The setting for slope of branch 2

(setting “Slope2_Diff”) is applicable for restraint currents of the first

break-point to the second one on restraint axis, and defines the ratio of

differential to restraint current above which the element will operate. This

slope is set to ensure sensitivity to internal faults at normal operating

current levels. The second break-point on restraint axis (setting

“I_ResPoint2 Diff”) defines the end of the slope 2 region and the begin-

ning of the slope 3 region. This setting should be set to the level at which

any of the protection CTs is probable to saturate.

In the range of high through fault currents which may give rise to high

differential currents as a result of CT saturation, branch 3 is applicable to

provide additional stabilization. The setting for the slope of this branch

(setting “Slope3_Diff”) is applicable up to the point at which the branch

intersects the characteristic of instantaneous differential protection.

As a summary of the fault detection using operating characteristics of the

above figure, the calculated differential and restraint currents, IDiff and

IRest, are compared by the differential protection with the operating

characteristic according to the following formula ,

1 1

2 1 1 1 1 2

3 2 2 2 1 1 1 2

( )

( ) ( )

diff res D res R

diff res R R D R res R

diff res R R R R D R res

I S I I I I

I S I I S I I I I I

I S I I S I I S I I I I

Equation 17

Where S1 is the slope of the branch 1 (setting “Slope1_Diff”),


36

S2 is the slope of the branch 2, (setting “Slope2_Diff”),

S3 is the slope of the branch 3, (setting “Slope3_Diff”),

ID> is the setting for the sensitivity threshold of the differential protection,

(setting “I_Percent Diff”),

IR1 is the setting for the first breakpoint restraint current, (setting

“I_ResPoint1 Diff”),

IR2 is the setting for the second breakpoint restraint current, (setting

“I_ResPoint2 Diff”).

If the operating point calculated from the quantities of differential and re-

straint current falls into the trip area, a trip signal is issued by the percent

differential protection. The issued signals are phase selective. They can

be found in event report as “Per Diff Trip A”, “Per Diff Trip B” and “Per Diff

Trip C”.

This stage cannot operate when there is an inrush or overexcitation sta-

bilization or a restraint due to CT failure detection. This is illustrated in

below logic diagram.

ID>

Phase-A

PER DIFF Trip A

PER DIFF Trip B

PER DIFF Trip C

A

N

D

ID>

Phase-B

ID>

Phase-C

ArestAdiff II ,

BrestBdiff II ,

CrestCdiff II ,

A

N

D

PER DIFF BLK A

PER DIFF BLK B

PER DIFF BLK C

CT FAIL

A

N

D

Func_Percent Diff on

Block Diff at CT_Fail on

Figure 17 Tripping logic of the percent differential protection

It should be noted that when the IED is delivered, both the instantaneous

and percent differential protection functions are switched off. Setting of

“0-off” is applied for Binary settings “Func_Inst Diff” and “Func_Percent


37

Diff”. This is because the fact that these protection functions should not

be used before at least the vector group and other essential parameters

for each side is correctly set. Without these settings the equipment may

show unpredictable behavior. (E.g. tripping)

4.3 Selective inrush stabilization schemes

In power transformers, high short-time magnetizing currents may be

present during power-up (inrush currents). The inrush current can

amount to a multiple of the rated current. These currents enter the pro-

tected zone. However, it does not exit again. They thus produce differen-

tial quantities, as they seem like single-end fed fault currents. Therefore,

they should be recognized in an appropriate manner. By this way, it is

possible to prevent false operation of differential protection caused by

inrush current. This possibility is provided in the IED. Selective inrush

stabilization can be enabled or disabled by Binary setting “Block Diff at

Inrush”, (1-Block, 0-Not Block). If setting “1-Block” is applied, the function

monitors differential current to detect an inrush condition. If the condition

is detected, it is possible to block differential protection phase-selectively.

Furthermore, alarm report entitled “Diff 2har Blk” is issued whenever in-

rush detection impose a blocking condition to differential protection. It

should be noted that the latter, is generated when any condition (2nd

harmonic, 3rd/5th harmonic, CT fail) leads to blocking of differential pro-

tection.

The IED provides two schemes to detect inrush conditions. The first

scheme is 2nd harmonic stabilization; the second scheme is fuzzy

recognition of inrush conditions based on the waveform. The two

schemes are convenient for user to be selected by the setting “2nd HAR

NOT WAVE” (1-2nd harmonic on; 0-waveform on). The two implemented

algorithm work alternatively. As soon as an inrush condition is recognized

by each of them, a restraint condition is applied to the respective phase

evaluation of percent differential protection. Since the applied restraint by

2nd harmonic detection operates individually per phase, the protection is

fully operative even when the protected transformer is switched onto a

single-phase fault, whereas inrush currents may possibly be present in

one of the healthy phases. It is, however, possible to set the protection in

a way that when the 2nd harmonic recognition is fulfilled only in one sin-

gle phase, not only the phase with the inrush current, but also the re-

maining phases of the percent differential protection are blocked. This is

achieved by cross-blocking the differential protection for a certain period

to avoid spurious tripping. The setting corresponds to “T_2nd Harm

Block”. Within this time, all three phases are blocked as soon as an in-


38

rush current is detected in any one phase. After the timer is expired, only

the phase with inrush current content is blocked.

4.3.1 2nd harmonic stabilization

By selecting “1-Block” for control-word “Block Diff at Inrush” and select-

ing“1-2nd harmonic” for Binary setting “2nd HAR NOT WAVE”, inrush

current is recognized if the second harmonic content in the differential

current exceeds a selectable threshold (setting “Ratio_2nd Harm”). The

ratio between the 2nd harmonic and the fundamental frequency compo-

nent is decisive to discriminate inrush conditions from the other operation

conditions. The ratio is calculated by the below equation. As soon as the

measured ratio exceeds the set thresholds, a restraint is applied to the

percent differential protection in respective phase.

2

2

K

I

I

diff

diff

Equation 18

Where Idiff-φ2 is 2nd harmonics magnitude of differential current, Kφ2 is

the setting for 2nd harmonics ratio, Idiff-φ is fundamental frequency

component of differential current.

4.3.2 Fuzzy recognition of inrush based on the waveform

By selecting “1-block” in control-word “Block Diff at Inrush”, and selecting

“0-waveform on” for Binary setting “2nd HAR NOT WAVE”, inrush current

is detected by a fuzzy recognition method based on waveform. In this

context, differential current waveform is sampled in each phase by 2n

number of samples per cycle, each of the samples is nominated as I(k),

k=1, 2, …, 2n. Then the value of X(k) is calculated according to the below

equation.

nknkIkI

nkIkIkX ,...,2,1,

)()(

)()()(

Equation 19

The smaller values of X(k) represent that the calculated point corre-


39

sponds to fault condition with higher confidence level. Alternatively, the

larger values of X(k) gives a picture that there is large content of inrush

current in the waveform. Assume that X(k) belongs to “inrush Fuzzy

class” with membership function of A[X(k)]. Then, the fuzzy similarity co-

efficient for the n calculated values of X(k) in one cycle is defined as be-

low equation.

n

k

nkXAN

1

/)]([

Equation 20

The derived value of N is used in the IED to assess the differential cur-

rent corresponds to inrush condition or not. To do so, the value of N is

compared with a threshold K, and inrush content is recognized in the

current waveform, if N>K.

2

2

K

I

I

Adiff

Adiff

2

2

K

I

I

Bdiff

Bdiff

2

2

K

I

I

Cdiff

Cdiff

O

R

O

R

O

R

PER DIFF BLK A

PER DIFF BLK B

PER DIFF BLK C

A

N

D

A

N

D

A

N

D


2nd Harm Not Wave on



Block Diff at Inrush on



T_2nd Harm Block

T_2nd Harm Block

T_2nd Harm Block

Figure 18 logic diagram of inrush stabilization schemes by 2nd harmonic


40

Fuzzy Inrush

Recognition in

Ph-A

Fuzzy Inrush

Recognition in

Ph-B

Fuzzy Inrush

Recognition in

Ph-C

2nd Harm Not Wave offPER DIFF BLK A

PER DIFF BLK B

PER DIFF BLK C

A

N

D

A

N

D

A

N

D


2nd Harm Not Wave off

2nd Harm Not Wave off




T_2nd Harm Block

T_2nd Harm Block

T_2nd Harm Block

Figure 19 logic diagram of inrush stabilization schemes by fuzzy

recognition

4.4 Overexcitation stabilization

Apart from the second harmonic, other harmonic contents can be se-

lected in the IED to cause stabilization of percent differential protection.

This is because the fact that unwanted differential currents caused by

transformer overexcitation may result in false tripping of the percent dif-

ferential protection. Since steady state overexcitation is characterized by

odd harmonics, the 3rd or the 5th harmonic can be selected in the IED to

judge for overexcitation stabilization. If it is desired to impose a blocking

condition to percent differential protection by these harmonics, Binary

setting “Block Diff at Overexcit” should be set to “1-on”. By applying this

setting, alarm report entitled “Diff 3/5har Blk” is issued whenever 3rd or

5th harmonic detection impose a blocking condition to differential protec-

tion. It should be noted that the latter, is generated when any condition

(2nd harmonic, 3rd/5th harmonic, CT fail) leads to blocking of differential

protection.

It is possible to use Binary setting “Overexcitation 3rd NOT 5th” to select

whether 3rd or 5th harmonic detection is utilized for detection of

overexcitation condition (1-3rd harmonic, 0-5th harmonic). Since the third

harmonic is often eliminated in delta winding of power transformers, the

fifth harmonic is more commonly used.

Similar to the 2nd harmonic stabilization, the applied restraint by 3rd or


41

5th harmonic detection operates individually per phase. It is, however,

possible to set the protection in a way that when the 3rd or 5th harmonic

recognition is fulfilled only in one single phase, not only the phase with

the inrush current, but also the remaining phases of the percent differen-

tial protection are blocked. This is achieved by cross-blocking the differ-

ential protection for a certain period to avoid spurious tripping. The set-

ting corresponds to “T_3/5th Harm Block”. Within this time, all three

phases are blocked as soon as an 3rd or 5th harmonic is detected in any

one phase. After the timer is expired, only the phase with 3rd or 5th

harmonic content is blocked.

The detection method used for 3rd or 5th harmonic is similar to those

applied for 2nd harmonic. However, setting “Ratio_3/5th Harm” is deci-

sive in this case. It means that 3rd or 5th harmonic is recognized if the

ratio between third or fifth harmonic and the fundamental frequency

component of the differential current exceeds the setting threshold. The

ratio is calculated by the below equation.

5/3

5/3

K

I

I

diff

diff

Equation 21

Where Idiff-φ3/5 is 3rd/5th harmonic magnitude of differential current,

Kφ3/5 is the setting for 3rd/5th harmonic ratio, Idiff-φ is fundamental

frequency component of differential current. Below figure show logic di-

agram of overexcitation stabilization.

Overexcit 3rd NOT 5th off O

R

O

R

O

R

PER DIFF BLK A

PER DIFF BLK B

PER DIFF BLK C

A

N

D

A

N

D

A

N

D

Block Diff at Overexcit on

Overexcit 3rd NOT 5th onA

N

D

Overexcit 3rd NOT 5th off


N

D

Overexcit 3rd NOT 5th off


N

D

T_3/5th Harm Block

T_3/5th Harm Block

T_3/5th Harm Block

5/3

3

K

I

I

Adiff

Adiff

5/3

5

K

I

I

Adiff

Adiff

5/3

3

K

I

I

Bdiff

Bdiff

5/3

5

K

I

I

Bdiff

Bdiff

5/3

3

K

I

I

Cdiff

Cdiff

5/3

5

K

I

I

Cdiff

Cdiff

Figure 20 logic diagram of overexcitation stabilization


42

4.5 CT Failure supervision

During steady-state operation, the CT failure supervision monitors the

transient behavior of the currents flowing through secondary circuit of

each phase and thus registers failures in the secondary circuit of the

current transformers for each side of the power transformer. The function

can be enabled or disabled by using setting “CT Fail Detect” (1-On, 0-Off).

If setting “1-On” is applied, IED issues the alarm report “Ph_A CT Fail”,

“Ph_B CT Fail”, “Ph_C CT Fail”, whenever a CT failure is detected. It is

also possible to set differential protection to be blocked or not at CT fail-

ure detection through setting "Block Diff at CT_Fail" (1-Block, 0-Not

Block). By setting “1-Block”, the percent differential protection is blocked

immediately in all phases. Blocking condition is cancelled as soon as the

device is again supplied with a normal current in the relevant faulty

phase(s). It should be noted that the setting "Block Diff at CT_Fail" is not

useful if the differential current is very high (more than 1.2 Ie, Ie is the

rated current of high voltage side). In other words, blocking conditions

takes place only for treble slope percent differential protection. This

means that the instantaneous differential protection will issue trip if a dif-

ferential current greater than setting “I_Inst Diff” is present, even if " Block

Diff at CT_Fail " is set to 1-Block.

The criteria for CT failure detection are as follow:

The currents flowing through all three phases of CT secondary are nor-

mal at each side of the protected object. As a result, the differential cur-

rent is near to zero. When one or two phase current of one side is de-

creased to less than a threshold (half of the memory current), at the

same time all three phase currents in other side(s) are normal, and dif-

ferential current is more than a threshold (>0.3I_Percent Diff) at least in

one phase, the condition maybe an indication of CT failure in the muta-

tive phase(s). CT failure detection logic is illustrated in below figure.


43

CT Fail

O

R

Max {Idiff_A, Idiff_B, Idiff_C}>0.3I_Percent Diff

Among {IMV_A, IMV_B, IMV_C}

and {ILV_A, ILV_B, ILV_C} all

currents without changing

Among {IHV_A, IHV_B, IHV_C} only 1

or 2 phase current decreased

Among {IHV_A, IHV_B, IHV_C} and

{ILV_A, ILV_B, ILV_C} all currents

without changing

Among {IMV_A, IMV_B, IMV_C} only 1


Among {IHV_A, IHV_B, IHV_C} and

{IMV_A, IMV_B, IMV_C} all currents

without changing

Among {ILV_A, ILV_B, ILV_C} only 1


A

N

D

A

N

D

A

N

D

A

N

D

CT Fail Detect on

Figure 21 CT Fail detection logic

4.6 CT Saturation supervision

When Internal and external faults occurs, it is possible that transient and

steady fault currents induce the CT saturation. CT saturation may lead to

mal-operation of differential protection when an external fault occurs. In

order to avoid mal-operation of protection in such situations, CT satura-

tion supervision element is integrated in IED.

When transient saturation of CT occurs, the 2nd harmonic content in the

corresponding phase current is dominant. Also whenever steady satura-

tion of CT occurs, the 3rd harmonic content in the corresponding phase

current is dominant. Both 2nd and 3rd harmonic contents of all phase

currents of each side of the protected transformer are calculated to judge

whether CT saturation occurs or not. Comprehensive harmonic ratio is

calculated by below equation.

harKI

I

I

I

32


44

Equation 22

Where:

Iφ2 is 2nd harmonic magnitude of phase current at each side,

Iφ3 is 3rd harmonic magnitude of phase current at each side,

Khar is the setting for comprehensive harmonic ratio, fixed in the soft-

ware.

If the 2nd and 3rd harmonic contents of any phase current are more than

Khar, then CT satisfies the above formulas and it is saturated. Usually

before the CT saturation status, there is a short time period in which CT

still works in its linear characteristic. By very fast CT saturation detection

of IED, it needs only 4ms before any CT saturation happening to detect

the fault which is internal or external fault. In order to distinguish satura-

tion caused by internal faults and external faults effectively, percent dif-

ferential protection based on sample values is used. If CT saturation is

induced by external fault, differential protection will be blocked. However

if CT saturation is induced by internal fault, differential protection will

send its trip signal.

The typical saturation figure of phase A CT saturation is shown in below

figure.

Figure 22 Typical phase A current transformer Saturation waveform

4.7 Differential current supervision


45

In normal operation condition, zero differential current is assumed in

each phase. The differential current supervision monitors the differential

currents and checks its value to be less than a threshold. An alarm report

is generated as “Diff Cur Alarm” after 5s, if the differential current ex-

ceeds the threshold value. The alarm is an indication of miss-connection

in CT secondary windings, and therefore is released to remind user to

detect the faulty connection in secondary circuit and remove it. The func-

tion can be enabled or disabled by using setting “Func_Diff Alarm” (1-On,

0-Off). The fixed threshold for releasing alarm is 0.3I_Percent Diff. How-

ever, to avoid incorrect alarm indications, the threshold value is increased

to 0.1A (in 1A nominal current inputs) and to 0.3A (in A nominal current

inputs), if 0.3I_Percent Diff<0.1A. This is shown in below equations.

.

.

max{0.3 _ ,0.1 } 1

max{0.3 _ ,0.3 } 5

D alarm n

D alarm n

I I Percent Diff A if I A

I I Percent Diff A if I A

Equation 23

Logic of differential current supervision is shown in below figure.

DIFF Alarm5s

Idiff_A>ID.alarm

Idiff_B>ID.alarm

Idiff_C>ID.alarm

O

R

A

N

D

Func_Diff Alarm on

Figure 23 CT Fail detection logic

DANGER: Before Differential protection is put into operation on site, po-

larity of current transformer must have been checked right by an energiz-

ing test of every side of the transformer or a test of simulating an external

fault of the side in primary system. Otherwise a mal-operation may occur

during an external fault.


46


IA1

IB1

IC1

Diff Alarm

IA2

IB2

IC2

IA3

IB3

IC3

IA4

IB4

IC4

Diff Trip

Inst Diff A Trip

Inst Diff B Trip

Inst Diff C Trip

Per Diff A Trip

Per Diff B Trip

Per Diff C Trip

Relay Startup

IA5

IB5

IC5

Differential Protection

Figure 24 Transformer differention protection module, with up to 15

current inputs


47


Signal Description

IA1 Phase A current input of 1st CT set

IB1 Phase B current input of 1st CT set

IC1 Phase C current input of 1st CT set

IA2 Phase A current input of 2nd CT set

IB2 Phase B current input of 2nd CT set

IC2 Phase C current input of 2nd CT set











Signal Description

Diff Alarm Differential alarm

Diff Trip Differential trip

Inst Diff A Trip Instantaneous differential phase A Trip

Inst Diff B Trip Instantaneous differential phase B Trip

Inst Diff C Trip Instantaneous differential phase C Trip

Per Diff A Trip Percent differential phase A Trip

Per Diff B Trip Percent differential phase B Trip

Per Diff C Trip Percent differential phase C Trip


6 Settings

Table 8 Instruction for Vector Group Angle setting

Binary setting values


48

Binary setting values

HV Wind Conn/Y-0 D-1 0 0 0 1 1 1

MV Wind Conn/Y-0 D-1

(Only for three-winding trans-

formers)

0 1 0 1 1 0

LV Wind Conn/Y-0 D-1 1 1 0 1 0 0

Vet Grp Angle odd odd even even odd odd

Remarks

Y-Y-D-1

/3/5/7/9/

11

Y-D-D-1

/3/5/7/9/

11

Y-Y-Y-

2/4/6/8

/10/12

D-D-D-

2/4/6/8/

10/12

D-D-Y-

1/3/5/7

/9/11

D-Y-Y-

1/3/5/7

/9/11

Table 9 Settings of Differential protection

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

I_Inst Diff A 0.5Ir 20Ir 20 Instantaneous Differential

(ID>>) current setting

I_Percent Diff A 0.08Ir 4Ir 2.1 Percentage Differential (ID>)

current setting

I_ResPoint1 Diff A 0.1Ir Ir 2 The 1st breakpoint restraint

current (IR1)

I_ResPoint2 Diff A 0.1Ir 10Ir 2 The 2nd breakpoint restraint

current (IR2)

Slope1_Diff 0 0.2 0.2 the 1st slope

Slope2_Diff 0.2 0.7 0.5 the 2nd slope

Slope3_Diff 0.25 0.95 0.7 the 3rd slope

Ratio_2nd Harm 0.05 0.80 0.15 2nd harmonic(HAR) ratio

Ratio_3/5th Harm 0.05 0.80 0.35 3rd

/ 5th harmonic(HAR) ratio

T_2nd Harm Block s 0 20 20

Within the delay 2nd

har-

monic block all three phas-

es. After the delay, then

only the local phase is

blocked.

T_3/5th Harm s 0 20 20 Within the delay 5th har-


49

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

Block monic block all three phas-



blocked.

Table 10 Binary settings of Differential protection


setting Description

Func_Inst Diff 0 1 0 Instantaneous differential

protection ON 1-on; 0-off.

Func_Percent Diff 0 1 0

Percentage differential pro-

tection ON 1-on; 0-off.

Block Diff at Inrush

0 1 0

Inrush block differential pro-

tection

1-block; 0-not block.

2nd Harm Not

Wave

0 1 0

2nd harmonic (HAR) inhibit

not the fuzzy recognition

based on the wave-

form(WAVE)

1-2nd harmonic on; 0-

waveform on

Block Diff at

Overexcit 0 1 0

Overexcitation block differ-

ential protection


Overexcit 3rd NOT

5th 0 1 0

Overexcitation stabilization

judgement

3rd or 5th harmonic (HAR)

inhibit on

1-3rd

harmonic; 0-5th har-

monic.

Func_Diff Alarm 0 1 0

Differential current (DIFF)

Alarming on

1-on; 0-off.

Block Diff at

CT_Fail 0 1 0

Block differential protection

when there is CT failure



50


setting Description

HV D_side Elimi-

nate I0 0 1 0

Eliminate calculated 3I0

when HV side winding is

connected in Delta mode

1- eliminate; 0-not eliminate

MV D_side Elimi-

nate I0 0 1 0


when MV side winding is



LV D_side Elimi-

nate I0 0 1 0


when LV side winding is



Diff Includes LV

Cur 0 1 0

LV current is included in

calculation of the differential

protection.

1- Diff Includes LV Cur;

0-Diff NOT Includes LV Cur

7 Report



Per Diff Trip A

Treble slope percent Differential protection (ID>) trip for phase A/B/C Per Diff Trip B

Per Diff Trip C

Inst Diff Trip A

Instantaneous Differential protection (ID>>) trip for phase A/B/C Inst Diff Trip B

Inst Diff Trip C

Table 12 Alarm report list


Ph_A Ct Fail Phase A CT failure

Ph_B Ct Fail Phase B CT failure


51


Ph_C Ct Fail Phase C CT failure

Diff Cur Alarm Imbalance differential current alarm

Diff 2har Blk Differential protection is blocked by 2nd

harmonic.

Diff 3/5har Blk Differential protection is blocked by 3rd

or 5th harmonic.

Table 13 Operation report list


Func_Diff On Differential protection is switched ON (by CW)

Func_Diff Off Differential protection is switched OFF (by CW)

8 Technical data

Table 14 Differential protection technical data

Item Range or value Tolerance

Instantaneous differential current 0.5 Ir to 20.00 Ir ≤ ±3% setting or ±0.02Ir

Percentage differential current 0.08 Ir to 4.00 Ir ≤ ±3% setting or ±0.02Ir,

Restraint current 1 0.1 Ir to 1 Ir ≤ ±3% setting or ±0.02Ir

Restraint current 2 0.1 Ir to 10 Ir ≤ ±3% setting or ±0.02Ir

Slope 1 0.0 to 0.2

Slope 2 0.2 to 0.7

Slope 3 0.25 to 0.95

2nd harmonic restraint ratio 0.05 to 0.80 of fundamental

3rd / 5th harmonic restraint ratio 0.05 to 0.80

Reset ratio of restrained differ-ential

approx. 0.7

Operating time of restraint dif-ferential

≤ 30ms at 200% setting, and IDifferential>2IRestraint

Operating time of instantaneous differential

20ms typically at 200% setting

Reset time approx. 40ms


52

Chapter 4 Restricted earth fault protection

53

Chapter 4 Restricted earth fault

protection

About this chapter This chapter describes the protection principle, input and

output signals, parameter, IED report and technical data for

restricted earth fault protection function.


54

1 Introduction

The restricted earth fault protection detects earth faults in power trans-

formers with earthed starpoint or in non-earthed power transformers with

a starpoint former (earthing transformer/reactor) installed inside the pro-

tected zone. A precondition for using this function is that a CT should be

installed in the starpoint connection, i.e. between the starpoint and earth.

The starpoint CT and the phase CTs define the limits of the protected

zone by restricted earth fault protection.

2 Applications

The IED provides two restricted differential protection functions which

can be used independently at various locations. For example, it is possi-

ble to use them for both windings of YNyn transformer which is earthed at

both starpoints. Further, one of them can be implemented to protect an

earthed transformer winding and the other for an earthing transform-

er/reactor. In case of auto-transformers, one of them is sufficient to pro-

tect the auto-windings. Examples for some of applications are illustrated

in the below figure.

A

B

C

HV

a

b

c

LV

CSC-326 013I

2.AI

2.BI

2.CI

2.2.2.023 CBA IIII

Figure 25 Application of restricted earth fault protection on an

earthed transformer winding


55

A

B

C

HV

a

b

c

LV

013I

2.cI

2.bI

2.aI

CSC-3262.2.2.023 cba IIII


earthing transformer winding

A

B

C

HV

a

b

c

LV

013I

2.BI

2.CI

2.AI

CSC-326

2.2.2.023 CBA IIII

013I

2.cI

2.bI

2.aI

2.2.2.023 cba IIII

Figure 27 Application of restricted earth fault protection on both

sides of transformer


56

a

b

c

013I

3.aI

3.bI

3.cI

A

B

C

2.BI

2.CI

2.AI

CSC-326

2.2.2.023 CBA IIII

3.3.3.033 cba IIII


auto-transformer


During healthy operation condition, no starpoint current 3I01 flows

through the starpoint CT. Furthermore, the sum of the phase currents 3I02

=IA.2 + IB.2 + IC.2 is almost zero. In case of auto-transformer, both the re-

sidual currents 3I02 =IA.2 + IB.2 + IC.2 and 3I03 =IA.3 + IB.3 + IC.3 are zero. With

an earth fault inside the protected zone, a starpoint current 3I01 flows.

Moreover, depending on the earthing conditions of the power system

outside the protected zone, a further earth current may be recognized in

the residual current path of the phase CTs (3I02 and 3I03). Since all the

currents flowing into the protected zone are defined positive, the residual

current from the system (3I02 and 3I03) is more or less in phase with the

starpoint current (3I01). With an earth fault outside the protected zone, a

starpoint current 3I01 flows into the protected zone, together with equal

residual current 3I02 and 3I03 which flows toward outside of the protected

zone, through the phase CTs. Keeping in mind positive direction current

flow, which is toward the protected zone, the starpoint current is in phase

opposition with 3I02 and 3I03.

With the described situations, it may seem to be simple to discriminate an

internal fault from an external one. However, there are some difficulties to

do so. For instance, when a strong fault without earth connection occurs

outside the protected zone, a residual current may appear in the residual

current path of the phase CTs. The residual current is caused by different

degrees of saturation in phase CTs and could simulate a fault in the

protected zone. Thus, additional measures should be taken to prevent

this current to cause false tripping. To achieve this objective, the re-

stricted earth fault protection provides a restraint quantity.


57

3.1 Differential and restraint current calculation

The differential current Idiff0 and the restraining current Irest0 are calculated

according to below figure.

3,3,3max

333

0302010

0302010

IIII

IIII

rest

diff

Equation 24

Idiff0 and Irest0 are compared by the restricted earth fault protection with

a dual-slope operating characteristic defined by below equation and

shown in below figure.

DDresresDdiff

DDresDdiff

SIIifISI

SIIifII

000000

00000

/

/

Equation 25

Where I0D is the setting for sensitivity threshold of restricted earth fault

protection (setting “HV 3I0_REF”, “MV 3I0_REF” or “LV 3I0_REF”), and

S0D is slope of the branch (setting “HV Slope_REF”, “MV Slope_REF” or

“LV Slope_REF”).

This characteristic can be enabled or disabled by using Binary setting

“HV Func_REF Trip”, “MV Func_REF Trip” or “LV Func_REF Trip”). If

setting “1-on” is selected, a trip signal is issued by restricted earth fault

protection when the operating point lies into tripping area (see below fig-

ure) and the preset time delay is expired (setting “HV T_REF Trip”, “MV

T_REF Trip” or “LV T_REF Trip”).

The trip logic for restricted earth fault protection is shown in below figure.


58

Diff0I

Res0I

3 0 _I REF

_Slope REF

Trip area

block area

Figure 29 Characteristic of restricted earth fault protection

A

N

DREF Trip

REF Alarm

Idiff0>HV 3I0_REF Alarm

Func_REF Trip on

T_REF Trip

T_REF Alarm

Func_REF Alarm on A

N

D

Figure 30 Tripping logic of the restricted earth fault protection

To clarify the proper operation during various situations, three important

operating conditions are examined.

External fault:

3I01 enters the protected zone, whereas 3I02 leaves the protected zone,

i.e. is negative according to the definition of signs, therefore 3I02 = –3I01.

Idiff0 = |3I01 + 3I02| = |3I01 – 3I02|= 0

Ires0 = max {|3I01|, |3I02|} = |3I01|

No tripping quantity (Idiff0 = 0); the restraint quantity (Irest0) corresponds

to the external fault current flowing through the starpoint connection.

Internal fault, fed only from the starpoint:


59

In this case, 3I02=0, thus,

Idiff0 = |3I01 + 3I02| = |3I01 + 0| = |3I01|

Ires0 = max {|3I01|, |3I02|} = |3I01|

Both the tripping (Idiff0) and the restraint (Irest0) quantities correspond to

the fault current flowing through the starpoint.

Internal fault, fed from the starpoint and from the system, e.g. with equal

earth current magnitude:

Both the 3I01 and 3I02 enter the protected zone, thus having positive sign.

The condition results in 3I02 = 3I01.

Idiff0 = |3I01 + 3I02| = |3I01 + 3I02|= 2×|3I01|

Ires0 = max {|3I01|, |3I02|} = |3I01|

Tripping quantity (Idiff0) corresponds to double the fault current flowing

through the starpoint connection, and restraint quantity (Irest0) is equal to

the fault current.

The results show that the device is capable to properly discriminate in-

ternal and external earth faults by using the definitions proposed for dif-

ferential and restraint current. However, the device is still subjected to

some influences that induce differential currents even during normal op-

eration condition. These influences should be compensated in appropri-

ate manner. The specific treatments designed to cope with these influ-

ences includes automatic ratio compensation which is explored as fol-

lows.

3.2 Automatic Ratio compensation

Restricted earth fault protection represents some problems in the appli-

cation of current transformers regarding to matching between phase and

starpoint CTs. The problem is originated from different ratio of phase and

starpoint CTs. The difference may result in a differential current in normal

operation condition. To remove this problem, the input currents of the

relay from starpoint CTs should be converted according to primary rated

currents of phase and starpoint CTs. In the IED, this objective is achieved

by taking a common reference value and converting all secondary cur-

rents of starpoint CTs into the same reference. The conversion is per-


60

formed by calculation of ratio compensation factor for starpoint CTs. The

compensation factors are then multiplied by the secondary current of

starpoint CTs to make them comparable with those current measured at

phase CTs. The conversion procedure is performed inside the device.

The ratio compensation factors are calculated as follow:

HVPhase

HVStarpo

HVStarpon

nK

int

int

Equation 26

MVPhase

MVStarpo

MVStarpon

nK

int

int

Equation 27

LVPhase

LVStarpo

LVStarpon

nK

int

int

Equation 28

Where HVStarpoK int is the ratio compensation factor for HV starpoint

CT; MVStarpoK int is the ratio compensation for MV starpoint CT

and LVStarpoK int is the ratio compensation for LV starpoint CT;

For auto-transformer, in addition to the common winding starpoint CT, the

measured current from phase winding of MV winding should also be

converted to the common reference current. In this context, the ratio

compensation factors are calculated as follow:

HVPhase

MVPhaseMV

n

nK

Equation 29

HVPhase

Starpo

Starpon

nK

int

int


61

Equation 30

Where MVK is the ratio compensation factor for MV phase CT, and

intStarpoKis the ratio compensation factor for common winding starpoint

CT.

The reference current is selected as is shown in below figure.

Table 15 Reference side selection for REF functions

Type function HV REF MV REF LV REF

2 winding HV CT --- LV CT

3 winding HV CT MV CT ---

Auto-transformer HV CT --- ---

3.3 Positive sequence current blocking

A

B

C

HV

a

b

c

LV

CSC-326 013I

2.AI

2.BI

2.CI

2.2.2.023 CBA IIII

CT2

When an external fault causes a heavy current to flow through the pro-

tected transformer, differences in the magnetic characteristics of the

current transformer CT2 under saturation condition may cause a signifi-

cant difference in the secondary currents I02 connected to IED. If the

difference is greater than the pickup threshold, the CBF protection func-

tion can trip even though no fault occurred in the protected zone. To

prevent the protection function from such erroneous operation, a restraint

(stabilizing) ratio, zero-sequence current divides positive-sequence cur-

rent, is brought in.


62

0

1

15%I

I

Where I0 is zero-sequence current, I1 is positive-sequence current.

Only when the ratio is greater than 15% can the CBF protection trip.

3.4 Restricted earth fault current alarm

In normal operation condition, zero differential current is expected for re-

stricted earth fault protection. The Restricted earth fault current supervi-

sion monitors Idiff0 and checks its value to be less than a threshold. An

alarm report is generated as “HV REF 3I0 Alarm”, “MV REF 3I0 Alarm” or

“LV REF 3I0 Alarm”, after the preset time of “HV T_REF Alarm”, “MV

T_REF Alarm” or “LV T_REF Alarm”, if the differential current exceeds

the threshold value “HV 3I0_REF”, “MV 3I0_REF” or “LV 3I0_REF”. The

alarm is an indication of miss-connection in phase or starpoint CT sec-

ondary windings, and therefore is released to remind user to detect the

faulty connection in secondary circuit and remove it. The function can be

enabled or disabled by using setting “HV Func_REF Alarm”, “MV

Func_REF Alarm” or “LV Func_REF Alarm”, (1-On, 0-Off). The setting

range of the threshold differential current to release restricted earth fault

current alarm is on [0.08-10A]. However, to avoid incorrect alarm indica-

tions, the threshold value is increased to 0.1A (in 1A nominal current in-

puts) and to 0.3A (in 5A nominal current inputs), if the set value is less

than 0.1A.

DANGER: Before Restricted Earth Fault protection is put into operation on

site, polarity of neutral current transformer for REF must have been

checked right by an energizing test of every side of the transformer or a

test of simulating an external fault of the side in primary system. Otherwise

a mal-operation may occur during an external earth fault.


63


IA1

IB1

IC1

REF Alarm

IA2

IB2

IC2

IREF

REF Trip

Relay Startup

Restricted Earth

Fault Protection

Figure 31 Restricted earth fault protection module


Signal Description

IA1 Phase A current input of CT of circuit breaker 1

IB1 Phase B current input of CT of circuit breaker 1

IC1 Phase C current input of CT of circuit breaker 1




IREF Neutral point current for REF


Signal Description

REF Alarm Restricted Earth Fault alarm

REF Trip Restricted Earth Fault trip



64

5 Settings

Table 18 Settings of Restricted earth fault protection for HV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

HV 3I0_REF A 0.08Ir 2Ir 2 Current setting for HV Restrict-

ed Earth Fault protection

HV

Slope_REF 0.2 0.95 0.5

Slope setting for HV Restricted

Earth Fault protection

HV T_REF

Trip s 0 60 0.03

HV Restricted Earth Fault trip

time setting

HV 3I0_REF

Alarm A 0.08Ir 2Ir 2

HV Restricted Earth Fault alarm

current setting

HV T_REF

Alarm s 0 60 0.03

HV Restricted Earth Fault alarm

time setting

Table 19 Binary settings of restricted earth fault protection for HV side of

transformer

Setting Unit Min. Max.

De-

fault

setting

Description

HV Func_REF

Trip 0 1 0

HV Restricted earth fault trip-stage

ON

1-on; 0-off.

HV Func_REF

Alarm 0 1 0

HV Restricted earth fault

Alarm-stage ON

1-on; 0-off.

Block HV REF

at HV CT_Fail 0 1 0

Block HV REF when CT failure,

1-Block;0-unblock

Table 20 Settings of Restricted earth fault protection for MV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

MV 3I0_REF A 0.08Ir 2Ir 2 Current setting for MV Restrict-

ed Earth Fault protection


65

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

MV

Slope_REF 0.2 0.95 0.5

Slope setting for MV Restricted


MV T_REF

Trip s 0 60 0.03

MV Restricted Earth Fault trip

time setting

MV 3I0_REF


MV Restricted Earth Fault alarm

current setting

MV T_REF

Alarm s 0 60 0.03

MV Restricted Earth Fault alarm

time setting

Table 21 Binary settings of restricted earth fault protection for MV side of

transformer


De-

fault

setting

Description

MV Func_REF

Trip 0 1 0

MV Restricted earth fault trip-stage

ON 1-on; 0-off.

MV Func_REF

Alarm 0 1 0

MV Restricted earth fault

Alarm-stage ON

1-on; 0-off.

Block MV REF

at MV CT_Fail 0 1 0

Block MV REF when CT failure,

1-Block;0-unblock

Table 22 Settings of restricted earth fault protection for LV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

LV 3I0_REF A 0.08Ir 2Ir 2 Current setting for LV Restricted


LV Slope_REF 0.2 0.95 0.5 Slope setting for LV Restricted


LV T_REF Trip s 0 60 0.03 LV Restricted Earth Fault trip

time setting

LV 3I0_REF


LV Restricted Earth Fault alarm

current setting


66

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

LV T_REF

Alarm s 0 60 0.03

LV Restricted Earth Fault alarm

time setting

Table 23 Binary settings of restricted earth fault protection for LV side of

transformer


De-

fault

setting

Description

LV Func_REF

Trip 0 1 0

LV Restricted earth fault trip-stage

ON 1-on; 0-off.

LV Func_REF

Alarm 0 1 0

LV Restricted earth fault

Alarm-stage ON

1-on; 0-off.

Block LV REF at

LV CT_Fail 0 1 0

Block LV REF when CT failure,

1-Block;0-unblock

6 Report



HV REF Trip HV Restricted Earth fault (REF) protection trip

MV REF Trip MV Restricted Earth fault (REF) protection trip

LV REF Trip LV Restricted Earth fault (REF) protection trip



HV REF 3I0 Alarm HV Restricted Earth fault (REF) protection trip

MV REF 3I0 Alarm MV Restricted Earth fault (REF) protection trip

LV REF 3I0 Alarm LV Restricted Earth fault (REF) protection trip


67



HV Func_REF On HV REF protection is switched ON (by CW)

HV Func_REF Off HV REF protection is switched OFF (by CW)

MV Func_REF On MV REF protection is switched ON (by CW)

MV Func_REF Off MV REF protection is switched OFF (by CW)

LV Func_REF On LV REF protection is switched ON (by CW)

LV Func_REF Off LV REF protection is switched OFF (by CW)

7 Technical data

Table 27 Restricted earth fault protection technical data

Item Rang or Value Tolerance

Differential current 0.08 Ir to 2.00 Ir ±3% setting or ±0.02Ir

Slope 0.2 to 0.95

Time delay 0.00 to 60.00s, step 0.01s ≤ ±1% setting or +40ms, at 200%

operating setting

Reset ratio Approx. 0.7, at tripping

Operating time ≤ 30ms, at 200% setting



68

Chapter 5 Overexcitation protection

69


About this chapter This chapter describes the protection principle, input and output

signals, parameter, IED report and technical data for

overexciation protection function.


70

1 Introduction

The overexcitation protection is used to detect impermissible overexcitation

conditions which can endanger power transformers. An increase in trans-

former flux beyond the rated values leads to saturation of the iron core and to

large eddy current losses which cause impermissible temperature rise in

transformer core.


2.1 Protection principle

The overexcitation condition may occur in power plant transformers when a

load center is disconnected from the system, and the voltage regulator does

not operate sufficiently fast to control the associated voltage rise. Similarly,

the overexcitation condition may occur as result of a decrease in frequency,

e.g. in island system. To protect the power transformer in such conditions, the

overexcitation protection function should pick up when the permissible limit of

flux is exceeded in the transformer core. To do so, the overexcitation protec-

tion function measures the voltage/frequency (U/f) ratio which is proportional

to the flux density B in transformer core, and puts it in relation to the nominal

flux density BN. The decision is then made based on the calculated ratio as is

shown in below equation.

NNN fU

fU

B

BN

Equation 31

Where N is the ratio of volt/hertz calculated by the device.

U and f are the measured voltage and frequency, and UN and fN are the rated

voltage and frequency (50Hz or 60Hz) of the device. While the rated fre-

quency is fixed to 50Hz or 60Hz in software, device is informed about rated

voltage by setting “Reference Voltage” which corresponds to nominal

phase-neutral voltage of the protected transformer when is transferred to


71

secondary value, using the turn ratio of voltage transformer. Thus, the use of

the overexcitation protection presumes that measured voltage is connected to

the device. Calculation of voltage/hertz ratio above is performed based on the

maximum voltage of the three phase-neutral or phase-phase voltages. Binary

setting “V/F Voltage(0-VPP,1-VPN)” determines whether phase-to-phase

voltage or phase-neutral voltage should be used for overexcitation protection,

by setting “0-VPP” or “1-VPN”, respectively.

It should be mentioned that the overexcitation protection can operate properly,

only if frequency is in range of 0.5 - 1.3 times the rated frequency and voltage

is greater than 0.7 times the rated voltage. If frequency or voltage is out of the

specified range, an alarm report “U or F EXCEED” is generated by the device,

after a fixed time delay of 150ms, and the overexcitation protection is blocked.

The logic is shown in below figure.

O

RU or F EXCEED150ms

f<0.5fn or

f>1.3fn

V<0.7Un

Figure 32 Condition for generating “U or F EXCEED” alarm

The overexcitation protection includes two definite characteristics (alarm and

trip) and one thermal characteristic. The latter characteristic provides an ap-

proximate replica of the temperature rise caused by overexcitation in the

protected object. The definite alarm stage can be enabled or disabled by us-

ing Binary setting “Func_Overexcit Alarm Def ” on. Similarly, the definite trip

stage can be enabled or disabled by using Binary setting “Func_Overexcit

Trip Def” on. Furthermore, the thermal characteristic can be set by Binary

setting “Func_Overexcit Trip Inv” on. It should be mentioned that the

overexcitation protection can be applied at HV, MV or LV side of the protected

transformer. However, it is not recommended to apply the function on the

transformer side with variable winding turns such as the transformer side with

an installed tap changer. To enable the protection on a given side, setting of

“HV Func_Overexcit” on, “MV Func_Overexcit” on and “LV Func_Overexcit”

on should be applied to corresponding Binary settings. However, these set-

tings should be applied to 1 only on one side at the same time. If any two of

“HV Func_Overexcit”, “MV Func_Overexcit” and “HV Func_Overexcit” are set

to 1 at the same time, alarm report “Setting Err” will be given by the device.

All the three available stages of the overexcitation protection use

phase-to-phase voltage or phase-neutral voltage of the corresponding side in

their calculations, based on the setting applied at Binary setting “V/F Volt-


72

age(0-VPP,1-VPN)”.

If the definite alarm stage is enabled in one side, and the calculated volt/hertz

ration exceeds the threshold defined by setting “Func_Overexcit Alarm Def”,

an alarm report “Def V/F Alarm ” is generated by the device, after the time

delay “T_Definite Alarm” elapsed. The logic for the definite alarm stage of

overexcitation protection is shown in below figure when it is applied to HV

side. The logic is the same when the protection function is applied to other

sides.

DEF V/F Alarm

A

N

D

O

R

O

R

O

R

U or F EXCEED

A

N

D

FVAlarmDEFfUN HvAB /,_

FVAlarmDEFfUN HvAC /,_

FVAlarmDEFfUN HvBC /,_

FVAlarmDEFfUN HvA /,_

FVAlarmDEFfUN HvB /,_

FVAlarmDEFfUN HvC /,_

A

N

D

HV Func_Overexcit on

Func_Overexcit Alarm Def on

HV T_REF Alarm

V/F Voltage(0-VPP,1-VPN) on

Figure 33 Logic of the definite alarm stage for overexcitation protection

Similarly, if the definite trip stage is enabled in one side, and the calculated

volt/hertz ration exceeds the threshold defined by setting “V/F_Definite Trip”,

an event report “Def V/F Trip” is generated by the device, subsequent to the


73

expiration of time delay “T_Definite Trip”. Tripping Logic of the definite trip

stage of overexcitation protection is shown in below figure.

DEF V/F Trip

A

N

D

O

R

O

R

O

R

U or F EXCEED

A

N

D

FVTripDEFfUN HvAB /,_

`

FVTripDEFfUN HvBC /,_

FVTripDEFfUN HvAC /,_

FVTripDEFfUN HvA /,_

FVTripDEFfUN HvB /,_

FVTripDEFfUN HvC /,_

A

N

D


Func_Overexcit Trip Def on


T_Definite Trip

Figure 34 Tripping logic of the definite trip stage for overexcitation protection

If thermal characteristic is set to “1-on” in one of transformer sides, it uses the

measured voltage and frequency of the corresponding side (depending on the

setting applied at Binary setting “V/F Voltage (0-VPP,1-VPN)”), together with

ten points derived from the manufacturer data. The points correspond to the

desired tripping times for a given volt/hertz ratios. Intermediate values are

determined by performing linear interpolation by the device. The ratios range

from N=1.05 to N=1.50. They are entered into the device by settings


74

“T1_Inverse V/F=1.05”, “T2_Inverse V/F=1.10”, “T3_Inverse V/F=1.15”,

“T4_Inverse V/F=1.20”, “T5_Inverse V/F=1.25”, “T6_Inverse V/F=1.30”,

“T7_Inverse V/F=1.35”, “T8_Inverse V/F=1.40”, “T9_Inverse V/F=1.45” and

“T10_Inverse V/F=1.50”. The device uses these points to form an inverse

characteristic such as those shown in below figure.

u/f

1.05

t(s)T10 T8 T6 T4 T2

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

T1T3T5T7T9

Figure 35 Thermal overexcitation characteristic

As can be seen from the above figure, N=1.05 works as a pickup threshold for

thermal stage. The thermal replica is implemented in IED by a counter which

is incremented from 0% to 100%, as soon as the calculated voltage/hertz ra-

tio of exceeds the pickup threshold (N=1.05). If the counter reaches to 100%

corresponding to expiration of trip time delay according to the trip character-

istic, the event report “Inv V/F Trip” is given. The trip signal is cancelled as

soon as the calculated voltage/hertz ratio falls below the pickup threshold

(N=1.05). However, the counter is decremented to zero according to cool

down time of the transformer (the time by which the thermal replica counter

reaches from 100% to 0%). The cool down time is informed to the device by

setting “T_Cool Down”.

Tripping Logic of the inverse thermal trip stage of overexcitation protection is

shown in below figure.


75

Inv V/F Trip

A

N

D

O

R

U or F EXCEED

A

N

D

O

R

u/f

1.0

5

t(s)T1

0T8 T6 T4 T2

1.1

0

1.1

5

1.2

0

1.2

5

1.3

0

1.3

5

1.4

0

1.4

5

1.5

0

T1T3T5T7T9

u/f

1.0

5

t(s)T1

0T8 T6 T4 T2

1.1

0

1.1

5

1.2

0

1.2

5

1.3

0

1.3

5

1.4

0

1.4

5

1.5

0

T1T3T5T7T9

u/f

1.0

5

t(s)T1

0T8 T6 T4 T2

1.1

0

1.1

5

1.2

0

1.2

5

1.3

0

1.3

5

1.4

0

1.4

5

1.5

0

T1T3T5T7T9

u/f

1.05

t(s)T10 T8 T6 T4 T2

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

T1T3T5T7T9

u/f

1.05

t(s)T10 T8 T6 T4 T2

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

T1T3T5T7T9

u/f

1.05

t(s)T10 T8 T6 T4 T2

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

T1T3T5T7T9

),( fUN HVAB

),( fUN HVBC

),( fUN HVAC

),( fUN HVA

),( fUN HVB

),( fUN HVC


Func_Overexcit Trip Inv on


O

R

A

N

D

Figure 36 Tripping logic of the thermal trip stage for overexcitation protection

NOTE: If it is possible for a given transformers to operate continuously under


76

the condition of N=1.05, corresponding time delay setting (“T1_Inverse

V/F=1.05”) should be set to 9999s. The same approach can be taken when, for

example, it is permissible for a transformer to operate continuously under the

condition N=1.10, N=1.15 and so on. It means that the thermal characteristic is

compound of 10 points at most, and it maybe contains less than 10 points. The

thermal characteristic would be disabled if all the delay time settings are set to

9999s.

2.2 Voltage channel configuration

UA/B/C voltage input channel of 1st Analog input module (hereinafter is

refered as AIM) is provided with the high accurate frequency measurement

hardware circuit. In order to offer the high performance overexcitation function

for HV, MV or LV side, the applied voltage input of HV side, MV side or LV

side must be connected with the UA/B/C voltage input channel of 1st Analog

input module (AIM1).

Only one of HV overexcitation, MV overexcitation or LV overexcitation func-

tions could be enabled for one transformer, so settings of “HV Voltage Chan

Sel” and “MV Voltage Chan Sel” under “Comm Para” submenu are used to

select the voltage channel.

For example of HV side; the setting “HV Voltage Chan Sel” can be set as 1, 2

and 3 which means voltage channels are connected to the corresponding

analog input module (see below table).

Table 28 Voltage channel selection setting

“Voltage Chan Sel” Voltage input channels, connected with external

volage inputs

1 UA/B/C voltage input channel of AIM1, which channels can

provide the frequency measurement hardware circuit.

2 UA/B/C voltage input channel of AIM2

3 UA/B/C voltage input channel of AIM3

If Binary setting “HV Func_Overexcit” is set 1 and “HV Voltage Chan Sel” is

set 2 or 3 (not 1), alarm report “Setting Err” will be given by the device. If Bi-

nary setting “MV Func_Overexcit” is set 1 and “MV Voltage Chan Sel” is set 2

or 3 (not 1), alarm report “Setting Err” will be given by the device. If “LV


77

Func_Overexcit”, anyone of “HV Voltage Chan Sel” and “MV Voltage Chan

Sel” is set 1, alarm report “Setting Err” will be given by the device.


UA

UB

UC

Relay Startup

Def V/F Alarm

Def V/F Trip

Inv V/F Trip

Overexcitation

Protection

Figure 37 Overexcitation protection module


Signal Description

UA Phase A voltage input

UB Phase B voltage input

UC Phase C voltage input


Signal Description

Def V/F Alarm Overexcitation protection(V/F) alarm with

definite (DEF) time characteristic

Def V/F Trip Overexcitation protection(V/F) tripping (Trip)

with definite (DEF) time characteristic

Inv V/F Trip Overexcitation protection(V/F) tripping (Trip)

with inverse(IVR) time characteristic



78

4 Settings

Table 31 Settings of overexcitation protection

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

Reference Volt-

age V 40 130 57.3

Nominal phase voltage in HV

side

V/F_Definite

Alarm 1 1.5 1.1 Alarming setting of volt/hertz

T_Definite Alarm s 0.1 9999 10 Timer setting for volt/hertz

alarming stage

V/F_Definite

Trip 1 1.5 1.2

Tripping setting of definite

volt/hertz stage

T_Definite Trip s 0.1 9999 1 Timer setting for definite

volt/hertz stage

T1_Inverse

V/F=1.05 s 0.1 9999 10

Timer setting for

volt/hertz=1.05

T2_Inverse

V/F=1.10 s 0.1 9999 90

Timer setting for

volt/hertz=1.10

T3_Inverse

V/F=1.15 s 0.1 9999 80

Timer setting for

volt/hertz=1.15

T4_Inverse

V/F=1.20 s 0.1 9999 70

Timer setting for

volt/hertz=1.20

T5_Inverse

V/F=1.25 s 0.1 9999 60

Timer setting for

volt/hertz=1.25

T6_Inverse

V/F=1.30 s 0.1 9999 50

Timer setting for

volt/hertz=1.30

T7_Inverse

V/F=1.35 s 0.1 9999 45

Timer setting for

volt/hertz=1.35

T8_Inverse

V/F=1.40 s 0.1 9999 40

Timer setting for

volt/hertz=1.40

T9_Inverse

V/F=1.45 s 0.1 9999 35

Timer setting for

volt/hertz=1.45

T10_Inverse

V/F=1.50 s 0.1 9999 30

Timer setting for

volt/hertz=1.50

T_Cool Down s 0.1 9999 25 Cool down time delay for

overexcitation protection


79

Table 32 Binary settings of overexcitation protection


De-

fault

set-

ting

Description

HV Func_Overexcit 0 1 0 HV Overexcitation (V/F) on

1-on; 0-off.

MV Func_Overexcit 0 1 0 MV Overexcitation (V/F) on

1-on; 0-off.

LV Func_Overexcit 0 1 0 LV Overexcitation (V/F) on

1-on; 0-off.

Func_Overexcit

Alarm Def 0 1 0

Definite Overexcitation (V/F)

Alarming on

1-on; 0-off.

Func_Overexcit Trip

Def 0 1 0

Definite (DEF)Overexcitation

(V/F) on

1-on; 0-off.

Func_Overexcit Trip

Inv 0 1 0

Inverse (IVR)Overexcitation

(V/F) on

1-on; 0-off.

V/F Volt-

age(0-VPP,1-VPN) 0 1 0

Overexcitation protection uses

phase-to-phase voltage (VPP)

or phase-to-earth voltage (VPN)

0-VPP; 1-VPN.

5 Report



Def V/F Trip Overexcitation protection(V/F) tripping (Trip) with definite (DEF)

and inverse(IVR) time characteristic Inv V/F Trip



Def V/F Alarm Overexcitation alarm


80


V or F Exceed Voltage or frequency is out of the permissible range

(25-65Hertz, >0.7 Un)



Func_Overexc On Overexcitation protection is switched ON (by CW)

Func_Overexc Off Overexcitation protection is switched OFF (by CW)

6 Technical data

Table 36 Overexcitation protection technical data


Reference voltage UN 40 to 130V, ≤ ±3 % setting or ±1 V

Inverse time characteristic

Ratio: 1.00 to 1.50 ≤ ±2.5% of the setting or 0.01

Time delay 0.1s to 9999s ≤±5% setting or ±70ms

Pair of Values for characteristic of V/f

1.05 /1.10 /1.15 /1.20 /1.25 /1.30 /1.35 /1.40 /1.45 /1.50

≤±5% setting or ± 70ms

Reset time, Approx. 70ms

Reset ratio ≥0.96

Definite time characteristic

Time delay T 0.1s to 9999s ≤±5% setting or ±70ms, at 200% operating setting

Reset time, Approx. 70ms

Reset ratio ≥0.96


81


82

Chapter 6 Overcurrent protection

83



signals, parameter, IED report and technical data for overcurrent

protection function.


84

1 Introduction

The non-directional overcurrent elements can be applied as backup protec-

tion functions for transformer as well as power system protection in networks

with radial nature and those which are supplied from a single source. The

directional overcurrent protection can also be applied in systems where pro-

tection coordination depends on both the magnitude of the fault current and

the direction of power flow to the fault location, for instance in case of par-

allel transformers supplied from a single source.


2.1 Protection Elements

Each voltage side of the protected transformer is provided with three over-current protection elements from which two elements operate as definite overcurrent stages and the other one operates with inverse time-current characteristic. All the elements can operate in conjunction with the integrated inrush restraint and directional functions.

Various stages of the elements are independent from each other and can be combined as desired. They can be enabled or disabled in each side using dedicated Binary settings. These Binary settings include “HV Func_OC1”, “HV Func_OC2” and “HV Func_OC Inv”, for HV side overcurrent protection, “MV Func_OC1”, “MV Func_OC2” and “MV Func_OC Inv”, for MV side overcurrent protection, “LV Func_OC1”, “LV Func_OC2” and “LV Func_OC Inv”, for LV side overcurrent protection. For example by applying setting “1-on” to “HV Func_OC1”, respective stage of overcurrent protection would be enabled in HV side.

Individual pickup value for each definite stage can be defined by setting “HV I_OC1” and “HV I_OC2” for HV side, “MV I_OC1” and “MV I_OC2” for MV side, “LV I_OC1” and “LV I_OC2” for LV side. By applying these settings, each phase current is compared separately with the setting value for each stage. If the respective value is exceeded, a trip time delay timer is started. The con-dition for start of the delay timer is expressed mathematically by below equa-tion, in which a, b and c represent three phases.

setII ( cba ,, )

Equation 32

The timer is set to count up to a user-defined time delay. The time delay can be set for each definite stage individually through settings “HV T_OC1” and


85

“HV T_OC2” for HV side, “MV T_OC1” and “MV T_OC2” for MV side, “LV T_OC1” and “LV T_OC2” for LV side. After the user-defined time delays have been elapsed, a trip signal is issued if the inrush restraint feature is applied and no inrush current is detected or if inrush restraint is disabled. However, the overcurrent protection would be blocked and therefore, no tripping takes place if the inrush restraint feature is enabled and an inrush condition exists. Further, an alarm report is issued as “HV Inrush Blk BU”, “MV Inrush Blk BU” or “LV Inrush Blk BU” indicating that a blocking condition is imposed to over-current element by inrush condition detection.

The pickup value for the inverse time-current stage can be defined by setting “HV I_OC Inv”, “MV I_OC Inv” and “LV I_OC Inv” for HV, MV and LV sides, respectively. Each phase current is separately compared with corresponding setting value. If a current exceeds 1.1 times the setting value, corresponding stage picks up. If an inverse time-current stage picks up, the tripping time is calculated from the actual fault current flowing, using the selected tripping curve. Maximum tripping time is limited to 100s.

The time delay of time-inverse characteristic is calculated based on the type

of the characteristic, the magnitude of the current and a time multiplier. For

the time-inverse characteristic, both ANSI and IEC based standard curves are

available and any user-defined characteristic can be defined using the fol-

lowing equation:

_

_ _ _

-1

P OC Inv

S

A OC Invt K OC Inv B OC Inv

I

I

Where I is the fault current;

Is is the current setting;

A_OC Inv: Time factor for inverse time stage

B_OC Inv: Time delay for inverse time stage

P_OC Inv: index for inverse time stage

K_OC Inv: Time multiplier Inrush restraint feature

(For detailed time inverse characteristic, refer to Appendix Time inverse

characteristic)

As mentioned previously, selection among the curves can be carried out by settings “HV Func_OC Inv”, “MV Func_OC Inv” and “LV Func_OC Inv” for HV, MV and LV sides, respectively. Furthermore, the time multiplier K_OC Inv can be set by user to coordinate the integrated inverse time-current characteristic of the device with other overcurrent relays installed for power system protec-tion. This can be performed by settings “HV K_OC Inv”, “MV K_OC Inv” and


86

“LV K_OC Inv” in case of HV, MV and LV overcurrent elements, respectively.

By applying pickup current and time multiplier settings, the device calculates the tripping time from the measured current in each phase separately, based on the selected inverse curve. Once the calculated time has been elapsed, a trip signal is issued provided that no inrush current is detected or inrush re-straint is disabled. If the inrush restraint feature is enabled and an inrush condition exists, the overcurrent protection would be blocked and therefore no tripping takes place. However, an alarm report is generated as “HV Inrush Blk BU”, “MV Inrush Blk BU” or “LV Inrush Blk BU”, indicating the blocking condi-tion which is imposed to overcurrent element by detection of inrush condition.

The trip signals and corresponding event reports are available separately for each stage. These include “HV OC1 Trip”, “HV OC2 Trip” and “HV OC Inv Trip” for HV side, “MV OC1 Trip”, “MV OC2 Trip” and “MV OC Inv Trip” for MV side, “LV OC1 Trip”, “LV OC2 Trip” and “LV OC Inv Trip” for LV side overcur-rent elements.

2.2 Inrush Restraint Feature

The transformer overcurrent protection may detect large magnetizing inrush currents flowing when transformer is energized. The inrush current may be several times of the nominal current, and may last from several tens of milli-seconds to several seconds. Inrush current comprises second harmonic as well as considerable fundamental component. So it may affect the overcur-rent protection which operates based on the fundamental component of the measured current. Inrush blocking unit in overcurrent function is provided for this purpose. It is possible to apply the inrush restraint feature separately to each definite stage and inverse time-current stage of overcurrent element by using Binary settings “HV OC1 Inrush Block”, “HV OC2 Inrush Block” and “HV OC Inv Inrush Block” on for HV side, “MV OC1 Inrush Block”, “MV OC2 Inrush Block” and “MV OC Inv Inrush Block” for MV side, “LV OC1 Inrush Block”, “LV OC2 Inrush Block” and “LV OC Inv Inrush Block” for LV side. By applying set-ting “1-on” to each of the mentioned Binary settings, no trip command would be possible by corresponding stage, if an inrush condition is detected.

Since Inrush current contains a relatively large second harmonic component which is nearly absent during a fault current, the inrush restraint feature op-erates based on the evaluation of the second harmonic content which is present in the measured current. The inrush condition is recognized if the ra-tio of second harmonic current to fundamental component exceeds the set-ting values “HV Ratio_I2/I1”, “MV Ratio_I2/I1” or “LV Ratio_I2/I1” in each phase. The setting is applicable to both the definite stages of overcurrent protection element as well as the inverse time-current stage for each voltage side of the protected transformer. As soon as the measured ratio exceeds the set threshold, a restraint is applied to those stages for which corresponding setting is applied to make them blocked in inrush condition detection (“HV OC1 Inrush Block”, “HV OC2 Inrush Block” and “HV OC Inv Inrush Block” for HV side, “MV OC1 Inrush Block”, “MV OC2 Inrush Block” and “MV OC Inv Inrush Block” for MV side, “LV OC1 Inrush Block”, “LV OC2 Inrush Block” and “LV OC Inv Inrush Block” for LV side.).


87

Since the applied restraint by second harmonic detection operates individu-ally per phase, the protection is fully operative even when the protected transformer is switched onto a single-phase fault, whereas inrush currents may possibly be present in one of the healthy phases. It is, however, possible to set the protection in a way that when the second harmonic recognition is fulfilled only in one single phase, not only the phase with the inrush current, but also the remaining phases of the overcurrent protection are blocked. This is achieved by cross-blocking the overcurrent protection for a certain period to avoid spurious tripping. The setting corresponds to “HV T2h_Cross_Blk”, “MV T2h_Cross_Blk”, “LV T2h_Cross_Blk”. Within this time, the overcurrent pro-tection in all three phases is blocked as soon as an inrush current is detected in any one phase. After the timer is expired, the overcurrent protection is blocked only in the phase with inrush current content. To put it more simply, cross blocking is reset if there is no more inrush in any phase, or the cross blocking time interval is elapsed. It should be noted that inrush currents flowing in the earth/ground path will not cross-block tripping by the phase elements.

Furthermore, if the fundamental component of phase current exceeds the upper limit value “HV Imax_2H_UnBlk”, “MV Imax_2H_UnBlk” or “LV Imax_2H_UnBlk”, the inrush restraint will no longer be effective in respective side, since a high-current fault is assumed in this case. The setting can be applied for each overcurrent element in each side of the protected trans-former.

2.3 Direction Determination Feature

The integrated directional function can be applied to each stage of overcur-rent element via dedicated Binary settings. These Binary settings include “HV OC1 Direction”, “HV OC2 Direction” and “HV OC Inv Direction” for HV side overcurrent stages, “MV OC1 Direction”, “MV OC2 Direction” and “MV OC Inv Direction” for MV side overcurrent stages and “LV OC1 Direction”, “LV OC2 Direction” and “LV OC Inv Direction” for LV side overcurrent stages. Fur-thermore, the directional orientation can be set individually for each stage of the overcurrent elements in various sides of the protected transformer. This can be performed by using Binary settings “HV OC1 Dir To Sys, “HV OC2 Dir To Sys” and “HV OC Inv Dir To Sys” for HV side, “MV OC1 Dir To Sys, “MV OC2 Dir To Sys” and “MV OC Inv Dir To Sys” for MV side, “LV OC1 Dir To Sys, “LV OC2 Dir To Sys” and “LV OC Inv Dir To Sys” for LV side. The possible settings for these Binary settings comprise “0-toward transformer” and “1-toward system”.

Basically, the direction determination is performed by determining the phase angle between the fault current and a reference voltage. The direction of a phase-directional element is detected by means of a cross-polarized voltage. It means that the fault current of the corresponding phase is used together with the healthy phase-to-phase voltage to determine direction of fault current. This takes effect to all three phases. Below figure shows the assignment of the measured values for the determination of fault direction for various types of pickups in phase overcurrent elements.

NOTE: The direction mentioned above is based on that the positive polarity is


88

at the side of the busbar and the negative polarity is at the side the trans-former.

Table 37 Voltage and current measurement used for direction determination

Phase Current Voltage

A aI bcU

B bI caU

C cI abU

As can be seen, the healthy voltages are used in direction determination. This allows for a correct direction determination even if the fault voltage has col-lapsed entirely because of a single-phase short-line fault. With three-phase short-line faults, memory voltage values are used to clearly determine the direction if the measurement voltages are not sufficient. The directional ele-ment of each side uses the voltage on itself side.

In a single-phase fault, the cross-polarized voltage (reference voltage) is 90° out of phase with the fault voltage. With phase-to-phase faults, the position of the reference voltage changes up to 30°, depending on the degree of collapse in the fault voltages. In order to satisfy different network conditions and ap-plications, the reference voltage can be rotated by an adjustable angle. For each side of the protected transformer, the directional angle can be set in-dependently. The settings include “HV Angle_OC”, “HV Angle_OC” and “LV Angle_OC”, for HV, MV and LV sides, respectively.

Forward

UBC_Ref

Angle_OC

IA

IA-

0°

90°

Bisector

Angle_Range

OC

Figure 38 Overcurrent protection directional characteristic

where:

Angle_OC: The settable characteristic angle


89

Angle_Range OC: 85º

During direction decision by directional function, a VT Fail condition (a short circuit or broken wire in the voltage transformer's secondary circuit or opera-tion of the voltage transformer fuse) may result in false or undesired tripping by directional overcurrent elements. In such a situation, it is possible to select operation status of the directional overcurrent protection elements in each side by using a number of control worlds to block the overcurrent protection elements or keep them in operational state with no direction decision (block direction decision). The corresponding Binary settings include “Block HV OC at HV VT_FAIL”, “Block MV OC at MV VT_FAIL” and “Block LV OC at LV VT_FAIL”, for HV, MV and LV sides, respectively. When the Binary settings are set as 0 to select “HV OC1 Direction”, corresponding overcurrent protec-tion elements will not judge direction at the local side VT failure. When they set as 1 to select “Block OC at VT Fail”, no operation is possible by the overcurrent protection elements. It is noted that the Binary settings affect all the stages of corresponding overcurrent elements at each side. For instance, by applying setting “0- HV OC1 Direction”, all the three stages of the over-current element will remain operative without direction determination in case of any fault in secondary circuit of HV side voltage transformer. On the other hand, setting “1- Blk HV OC at HV VT_Fail” makes them blocked.

The logic for Definite and Inverse time IDMTL overcurrent protection is shown in below figure.

OC 1 （2）Trip

Direction Unit OK

OC Inv Trip

HV Func_OC on

DIR Positive

VT failure

Direct OK at VT FAIL

A

N

D

A

N

D

O

R

HV Func_OC1 (2) on

I>HV I_OC1 (2)

Direction Unit OK

Inrush BLK OC

A

N

D

HV T_OC1(2)

HV Func_OC Inv on

Inverse Curve>

Direction Unit

OK

Direction Unit

OK

Inrush BLK OC

A

N

D

t


90

Figure 39 Tripping logic for overcurrent protection

2.4 CBF initiation Feature

It is possible to set whether the overcurrent protection elements can initiate the integrated CBF protection or not. The available choices depend on the voltage side of the power transformer at which overcurrent protection is ap-plied. In this context, HV side overcurrent protection element always initiates HV side CBF function with no additional setting. However, it is possible to select whether it can initiate MV and LV CBF protection functions via Binary settings “HV OC Initiate LV CBF” and “HV OC Initiate MV CBF”, respectively.

MV side overcurrent protection element always initiates MV side CBF function with no additional setting. However, it is possible to select whether it can ini-tiate HV side CBF protection function via Binary setting “MV OC Initiate HV1 CBF”.

LV side overcurrent protection element always initiates LV side CBF function with no additional setting. However, it is possible to select whether it can ini-tiate HV side CBF protection function via Binary setting “LV OC Initiate HV1 CBF”.

More detail information about the initiation conditions and related Binary set-tings can be found as below.


91


IA1

IB1

IC1

IA2

IB2

IC2

UA

UB

UC

OC1 Trip

OC2 Trip

OC Inv Trip

Relay Startup

Overcurrent

Protection

Figure 40 Overcurrent protection module


Signal Description











92


Signal Description

OC1 Trip Overcurrent stage 1 trip

OC2 Trip Overcurrent stage 2 trip

OC Inv Trip Overcurrent inverse stage trip


4 Setting

Table 40 Settings of overcurrent protection for HV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

HV I_OC1 A 0.05Ir 20Ir 5 HV overcurrent (O/C) current

setting for Stage 1

HV T_OC1 s 0 60 60 Time setting for HV OC, Stage

1

HV I_OC2 A 0.05Ir 20Ir 5 HV overcurrent (O/C) current

setting for Stage 2

HV T_OC2 s 0 60 60 Time setting for HV OC, Stage

2

HV

Curve_OC

Inv

1 12 1 Ref to IEC and ANSI Curves

HV I_OC Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI Curves

HV K_OC Inv 0.05 999 1 Ref to IEC and ANSI Curves

HV A_OC Inv s 0 200 0.14 Ref to IEC and ANSI Curves

HV B_OC Inv s 0 60 0 Ref to IEC and ANSI Curves

HV P_OC Inv 0 10 0.02 Ref to IEC and ANSI Curves

HV An-

gle_OC ° 0 90 45

The angle setting for voltage

ahead of current.

HV

Imax_2H_Un

Blk

A 0.25Ir 20Ir 5

The maximum 1st -harmonic

current setting to remove the

inrush block, in HV O/C pro-


93

tection

HV Ra-

tio_I2/I1 0.07 0.5 0.2

Inrush 2nd

harmonic ratio set-

ting for blocking HV O/C pro-

tection

HV

T2h_Cross_B

lk

s 0 60 20

Inrush 2nd

harmonic

cross-block time for HV O/C

protection

Table 41 Binary settings of overcurrent protection for HV side of transformer


De-

fault

set-

ting

Description

HV Func_OC1

0 1 0

The 1st stage of HV OC (OC_1)

protection is switched ON

1-on; 0-off.

HV OC1 Direc-

tion 0 1 0

Direction (DIR) detection of HV OC

Stage 1 is switched ON

1-on; 0-off.

HV OC1 Dir To

Sys 0 1 0

Direction unit of HV OC Stage 1

points to system

0 - point to the protected transformer

1- point to system

HV OC1 Inrush

Block 0 1 0

Inrush 2nd

harmonic detection HV

OC Stage 1 is switched ON

1-on; 0-off.

HV Func_OC2

0 1 0

The 2nd

stage of HV OC (OC_2)


1-on; 0-off.

HV OC2 Direc-

tion 0 1 0



1-on; 0-off.

HV OC2 Dir To

Sys 0 1 0

Direction unit of HV OC Stage 2

points to system


1- point to system

HV OC2 Inrush

Block 0 1 0

Inrush 2nd



1-on; 0-off.


94

HV Func_OC

Inv 0 1 0

The IDMTL inverse time stage of HV

OC protection is switched ON

1-on; 0-off.

HV OC Inv Di-

rection 0 1 0


IDMTL inverse time is switched ON

1-on; 0-off.

HV OC Inv Dir

To Sys 0 1 0

Direction unit of HV OC IDMTL in-

verse time points to system


1- point to system

HV OC Inv In-

rush Block 0 1 0

Inrush 2nd


OC IDMTL inverse time is switched

ON

1-on; 0-off.

Block HV OC at

HV VT_Fail 0 1 0

Select to block HV OC protection or

exit direction unit, when HV VT fails

0- HV Direct OK at HV VT Fail

1- Blk HV OC at HV VT Fail

HV OC Initiate

LV CBF 0 1 0

HV OC protection initiate LV side

CBF

0 - initiate, 1 – not initiate

HV OC Initiate

MV CBF 0 1 0

HV OC protection initiate MV side

CBF


Table 42 Settings of overcurrent protection for MV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

MV I_OC1 A 0.05Ir 20Ir 5 MV overcurrent (O/C) current

setting for Stage 1

MV T_OC1 s 0 60 60 Time setting for MV OC, Stage

1

MV I_OC2 A 0.05Ir 20Ir 5 MV overcurrent (O/C) current

setting for Stage 2

MV T_OC2 s 0 60 60 Time setting for MV OC, Stage

2

MV

Curve_OC 1 12 1 Ref to IEC and ANSI Curves


95

Inv

MV I_OC Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI Curves

MV K_OC Inv 0.05 999 1 Ref to IEC and ANSI Curves

MV A_OC Inv s 0 200 0.14 Ref to IEC and ANSI Curves

MV B_OC Inv s 0 60 0 Ref to IEC and ANSI Curves

MV P_OC Inv 0 10 0.02 Ref to IEC and ANSI Curves

MV An-

gle_OC ° 0 90 45


ahead of current.

MV

Imax_2H_Un

Blk

A 0.25Ir 20Ir 5



inrush block, in MV O/C pro-

tection

MV Ra-

tio_I2/I1 0.07 0.5 0.2

Inrush 2nd

harmonic ratio set-

ting for blocking MV O/C pro-

tection

MV

T2h_Cross_B

lk

s 0 60 20

Inrush 2nd

harmonic

cross-block time for MV O/C

protection

Table 43 Binary settings of overcurrent protection for MV side of transformer


De-

fault

set-

ting

Description

MV Func_OC1

0 1 0

The 1st stage of MV OC (OC_1)


1-on; 0-off.

MV OC1 Direc-

tion 0 1 0

Direction (DIR) detection of MV OC


1-on; 0-off.

MV OC1 Dir To

Sys 0 1 0

Direction unit of MV OC Stage 1

points to system


1- point to system

MV OC1 Inrush

Block 0 1 0

Inrush 2nd

harmonic detection MV


1-on; 0-off.


96

MV Func_OC2

0 1 0

The 2nd

stage of MV OC (OC_2)


1-on; 0-off.

MV OC2 Direc-

tion 0 1 0



1-on; 0-off.

MV OC2 Dir To

Sys 0 1 0

Direction unit of MV OC Stage 2

points to system


1- point to system

MV OC2 Inrush

Block 0 1 0

Inrush 2nd



1-on; 0-off.

MV Func_OC

Inv 0 1 0

The IDMTL inverse time stage of MV


1-on; 0-off.

MV OC Inv

Direction 0 1 0



1-on; 0-off.

MV OC Inv Dir

To Sys 0 1 0

Direction unit of MV OC IDMTL in-



1- point to system

MV OC Inv

Inrush Block 0 1 0

Inrush 2nd



ON

1-on; 0-off.

Block MV OC

at MV VT_Fail 0 1 0

Select to block MV OC protection or

exit direction unit, when MV VT fails

0- MV Direct OK at MV VT Fail

1- Blk MV OC at MV VT Fail

MV OC Initiate

HV1 CBF 0 1 0

MV OC protection initiate HV1 side

CBF


Table 44 Settings of overcurrent protection for LV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description


97

LV I_OC1 A 0.05Ir 20Ir 5 LV overcurrent (O/C) current

setting for Stage 1

LV T_OC1 s 0 60 60 Time setting for LV OC, Stage

1

LV I_OC2 A 0.05Ir 20Ir 5 LV overcurrent (O/C) current

setting for Stage 2

LV T_OC2 s 0 60 60 Time setting for LV OC, Stage

2

MV

Curve_OC

Inv


LV I_OC Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI Curves

LV K_OC Inv 0.05 999 1 Ref to IEC and ANSI Curves

LV A_OC Inv s 0 200 0.14 Ref to IEC and ANSI Curves

LV B_OC Inv s 0 60 0 Ref to IEC and ANSI Curves

LV P_OC Inv 0 10 0.02 Ref to IEC and ANSI Curves

LV Angle_OC 0 90 45 The angle setting for voltage

ahead of current.

LV

Imax_2H_Un

Blk

0.25Ir 20Ir 5



inrush block, in LV O/C protec-

tion

LV Ra-

tio_I2/I1 0.07 0.5 0.2

Inrush 2nd

harmonic ratio set-

ting for blocking LV O/C pro-

tection

LV

T2h_Cross_B

lk

0 60 20

Inrush 2nd

harmonic

cross-block time for LV O/C

protection

Table 45 Binary settings of overcurrent protection for LV side of transformer


De-

fault

set-

ting

Description

LV Func_OC1

0 1 0

The 1st stage of LV OC (OC_1) pro-

tection is switched ON

1-on; 0-off.

LV OC1 Direc- 0 1 0 Direction (DIR) detection of LV OC


98

tion Stage 1 is switched ON

1-on; 0-off.

LV OC1 Dir To

Sys 0 1 0

Direction unit of LV OC Stage 1

points to system


1- point to system

LV OC1 Inrush

Block 0 1 0

Inrush 2nd

harmonic detection LV


1-on; 0-off.

LV Func_OC2

0 1 0

The 2nd

stage of LV OC (OC_2)


1-on; 0-off.

LV OC2 Direc-

tion 0 1 0

Direction (DIR) detection of LV OC


1-on; 0-off.

LV OC2 Dir To

Sys 0 1 0

Direction unit of LV OC Stage 2

points to system


1- point to system

LV OC2 Inrush

Block 0 1 0

Inrush 2nd



1-on; 0-off.

LV Func_OC

Inv 0 1 0

The IDMTL inverse time stage of LV


1-on; 0-off.

LV OC Inv Di-

rection 0 1 0

Direction (DIR) detection of LV OC


1-on; 0-off.

LV OC Inv Dir

To Sys 0 1 0

Direction unit of LV OC IDMTL in-



1- point to system

LV OC Inv In-

rush Block 0 1 0

Inrush 2nd



ON

1-on; 0-off.

Block LV OC at

LV VT_Fail 0 1 0

Select to block LV OC protection or

exit direction unit, when LV VT fails

0- LV Direct OK at LV VT Fail

1- Blk LV OC at LV VT Fail


99

LV OC Initiate

HV1 CBF 0 1 0

LV OC protection initiate HV1 side

CBF


5 Report



HV OC Inv Trip Inverse time stage of HV overcurrent protection trip

HV OC1 Trip HV overcurrent stage 1 trip


MV OC Inv Trip Inverse time stage of MV overcurrent protection trip

MV OC1 Trip MV overcurrent stage 1 trip


LV OC Inv Trip Inverse time stage of LV overcurrent protection trip

LV OC1 Trip LV overcurrent stage 1 trip




HV Func_OC On Overcurrent protection of HV side is switched ON (by CW)

HV Func_OC Off Overcurrent protection of HV side is switched OFF (by CW)

MV Func_OC On Overcurrent protection of MV side is switched ON (by CW)

MV Func_OC Off Overcurrent protection of MV side is switched OFF (by CW)

LV Func_OC On Overcurrent protection of LV side is switched ON (by CW)

LV Func_OC Off Overcurrent protection of LV side is switched OFF (by CW)

6 Technical data

Table 48 Overcurrent protection technical data


Definite time characteristics

Current 0.08 Ir to 20.00 Ir ≤ ±3% setting or ±0.02Ir


100

Time delay 0.00 to 60.00s, step 0.01s ≤ ±1% setting or +40ms, at 200% operating setting


Reset ratio Approx. 0.95 at I/In ≥ 0.5

Inverse time characteristics


IEC standard Normal inverse;

Very inverse;

Extremely inverse;

Long inverse

≤ ±5% setting + 40ms, at 2

<I/ISETTING < 20, in accordance

with IEC60255-151

ANSI Inverse;

Short inverse;

Long inverse;

Moderately inverse;

Very inverse;

Extremely inverse;

Definite inverse


<I/ISETTING < 20, in accord-

ance with ANSI/IEEE C37.112,

user-defined characteristic

T=


<I/ISETTING < 20, in accordance

with IEC60255-151

Time factor of inverse time, A 0.005 to 200.0s, step 0.001s

Delay of inverse time, B 0.000 to 60.00s, step 0.01s

Index of inverse time, P 0.005 to 10.00, step 0.005

set time Multiplier for step n: k 0.05 to 999.0, step 0.01

Minimum operating time 20ms

Maximum operating time 100s

Reset mode instantaneous

Reset time approx. 40ms,

Directional element

Operating area range 170° ≤ ±3°, at phase to phase volt-age >1V Characteristic angle 0° to 90°, step 1°

Chapter 7 Earth fault protection

101



signals, parameter, IED report and technical data for earth fault



102


1.1 Protection elements

Each voltage side of the protected transformer is provided with three earth fault protection elements from which two elements operate as definite earth fault stages and the other one operates with inverse time-current characteris-tic. All the elements can operate in conjunction with the integrated inrush re-straint and directional functions.

Various stages of each element are independent from each other and can be combined as desired. They can be enabled or disabled in each side using dedicated Binary settings. These Binary settings include “HV Func_EF1”, “HV Func_EF2” and “HV Func_EF Inv” on, for HV side earth fault protection, “MV Func_EF1”, “MV Func_EF2” and “MV Func_EF Inv”, for MV side earth fault protection, “LV Func_EF1”, “LV Func_EF2” and “LV Func_EF Inv”, for LV side earth fault protection. For example by applying setting “1-on” to “HV Func_EF1”, respective stage of earth fault protection would be enabled in HV side.

Individual pickup value for each definite stage can be defined by setting “HV 3I0_EF1” and “HV 3I0_EF2” for HV side, “MV 3I0_EF1” and “MV 3I0_EF2” for MV side, “LV 3I0_EF1” and “LV 3I0_EF2” for LV side. By applying these set-tings, each earth current (quantity 3I0) calculated from the three phase cur-rents is compared separately with the setting value for each stage. If the re-spective value is exceeded, a trip time delay timer is started. The condition for start of the delay timer is expressed mathematically:

setII 00 33

Equation 33

The timer is set to count up to a user-defined time delay. The time delay can be set for each definite stage individually through settings “HV T_EF1” and “HV T_EF2” for HV side, “MV T_EF1” and “MV T_EF2” for MV side, “LV T_EF1” and “LV T_EF2” for LV side. After the user-defined time delay has been elapsed, a trip signal is issued if the inrush restraint feature is applied and no inrush current is detected or inrush restraint is disabled. The earth fault protection would be blocked and therefore, no tripping takes place if the inrush restraint feature is enabled and an inrush condition exists. However, an alarm report is issued nominated as “HV EF1 Inrush Block”, “HV EF2 Inrush Block” or “HV EF Inv Inrush Block”, indicating the blocking condition of earth fault element caused by inrush condition detection.

Pickup value for the inverse time-current stage can be set by setting “HV 3I0_EF Inv”, “MV 3I0_EF Inv” and “LV 3I0_EF Inv” for HV, MV and LV sides, respectively. Each earth current (quantity 3I0) calculated from the three phase


103

currents is separately compared with corresponding setting value. If a current exceeds 1.1 times the setting value, corresponding stage picks up. When an inverse time-current stage picks up, the tripping time is calculated from the calculated quantity 3I0, using the selected tripping curve. Maximum tripping time is limited to 100s.

The time delay of time-inverse characteristic is calculated based on the type

of the characteristic, the magnitude of the current and a time multiplier. For

the time-inverse characteristic, both ANSI and IEC based standard curves are

available and any user-defined characteristic can be defined using the fol-

lowing equation:

_

_ _ _

-1

HP EF Inv

S

A EF Invt K EF Inv B EF Inv

I

I

Equation 34

Where I is the calculated earth fault current;


A_EF Inv: Time factor for inverse time stage

B_EF Inv: Time delay for inverse time stage

P_EF Inv: index for inverse time stage

K_EF Inv: Time multiplier

By applying the desired setting values, the device calculates the tripping time

from the zero sequence current. Once the calculated time elapsed, report “EF

Inv Trip” will be issued.

As mentioned previously, selection among the curves can be carried out by settings “HV Curve_EF Inv”, “MV Curve_EF Inv” and “LV Curve_EF Inv” for HV, MV and LV sides, respectively. Furthermore, the time multiplier K_EF Inv can be applied by user to coordinate the integrated inverse time-current characteristic of the device with other earth fault relays installed for power system protection. This can be performed by settings “HV K_EF Inv”, “MV K_EF Inv” and “LV K_EF Inv” in case of HV, MV and LV earth fault elements.

By applying pickup current and time multiplier settings, the device determines the tripping time from the calculated earth current, based on the selected in-verse curve. Once the calculated time has been elapsed, a trip signal is is-sued provided that no inrush current is detected or inrush restraint is disabled. If the inrush restraint feature is enabled and an inrush condition exists the earth fault protection would be blocked and therefore no tripping takes place.


104

However, an alarm report is issued designated as “HV Inrush Blk BU”, “MV Inrush Blk BU” or “LV Inrush Blk BU”, indicating the blocking condition of overcurrent element caused by inrush condition detection.

The trip signals and corresponding event reports are available separately for each stage. They include “HV EF_1 Trip”, “HV EF_2 Trip” and “HV IDMTL EF Trip” for HV side, “MV EF_1 Trip”, “MV EF_2 Trip” and “MV IDMTL EF Trip” for MV side, “LV EF_1 Trip”, “LV EF_1 Trip” and “LV IDMTL EF Trip” for LV side earth fault elements.


The transformer earth fault protection may detect large magnetizing inrush currents flowing when transformer is energized. The inrush current may be several times of the nominal current, and may last from several tens of milli-seconds to several seconds.

Inrush current comprises second harmonic as well as a considerable funda-mental component. So, it may affect earth fault protection which operates based on the fundamental component of the measured current. Inrush blocking unit in earth fault function is provided for this purpose.

It is possible to apply the inrush restraint feature separately to each definite stage and inverse time-current stage of earth fault element by using Binary settings “HV EF1 Inrush Block”, “HV EF2 Inrush Block” and “HV EF Inv Inrush Block” for HV side, “MV EF1 Inrush Block”, “MV EF2 Inrush Block” and “MV EF Inv Inrush Block” for MV side, “LV EF1 Inrush Block”, “LV EF2 Inrush Block” and “LV EF Inv Inrush Block” on for LV side. By applying setting “1-on” to each of the mentioned Binary settings, no trip command would be possible by corresponding stage, if an inrush condition is detected.

Since the inrush current contains a relatively large second harmonic compo-nent which is nearly absent during a fault current, the inrush restraint oper-ates based on the evaluation of the second harmonic content which is present in the phase currents. The inrush condition is recognized if the ratio of second harmonic current to the fundamental component exceeds the setting value “HV Ratio_I2/I1_EF”, “MV Ratio_I2/I1_EF” or “LV Ratio_I2/I1_EF” in each phase current. The setting is applicable to both the definite stages of earth fault protection element as well as the inverse time-current stage. As soon as the measured ratio exceeds the set threshold, a restraint is applied to those stages for which corresponding setting is applied to make them blocked in inrush condition detection (“HV EF1 Inrush Block”, “HV EF2 Inrush Block” and “HV EF Inv Inrush Block” on for HV side, “MV EF1 Inrush Block”, “MV EF2 Inrush Block” and “MV EF Inv Inrush Block” for MV side, “LV EF_1 Inrush Detect ON”, “LV EF1 Inrush Block”, “LV EF2 Inrush Block” and “LV EF Inv Inrush Block” for LV side).

Furthermore, if the fundamental component of each phase current exceeds the upper limit value “HV Ratio_I2/I1”, “MV Ratio_I2/I1” or “LV Ratio_I2/I1”, the inrush restraint will no longer effective in respective side, since a high-current fault is assumed in this case.


105


The integrated directional function can be applied to each stage of earth fault elements via Binary settings. The Binary settings include “HV EF1 Direction”, “HV EF2 Direction” and “HV EF Inv Direction” on for HV side earth fault stages, “MV EF1 Direction”, “MV EF2 Direction” and “MV EF Inv Direction” for MV side earth fault stages and “LV EF1 Direction”, “LV EF2 Direction” and “LV EF Inv Direction” for LV side earth fault stages.

Furthermore, the directional orientation can be set individually for each stage of earth fault elements in various sides of the protected transformer. This can be performed by Binary settings “HV EF1 Dir To Sys”, “HV EF2 Dir To Sys” and “HV EF Inv Dir To Sys” for HV side, “MV EF1 Dir To Sys”, “MV EF2 Dir To Sys” and “MV EF Inv Dir To Sys” for MV side, “LV EF1 Dir To Sys”, “LV EF2 Dir To Sys” and “LV EF Inv Dir To Sys” for LV side. The possible settings for these Binary setting comprise “0-toward transformer” and “1-toward system”.

Basically, the direction determination is performed by comparing the zero sequence system quantities. In the current path, 3I0 current is calculated from the sum of the three phase currents. In the voltage path, the device calculates the zero sequence voltage 3V0 from the sum of the three phase voltages. Contrary to the directional phase elements, which work with the un-faulted voltage as reference voltage, the fault voltage itself is the reference voltage for the directional ground element. Depending on the connection of the volt-age transformer, this is the voltage 3V0 or VN. The directional element at each side operates with the residual/ neutral voltage of the same side.

In order to satisfy different network conditions and applications, the reference voltage can be rotated by an adjustable angle. For each side of the protected transformer, the directional angle can be set independently. The settings in-clude “HV Angle_EF”, “MV Angle_EF” and “LV Angle_EF”, for HV, MV and LV sides, respectively. It should be noted that the settings affect all the directional stages of the corresponding earth fault element.

NOTE: The direction mentioned above is based on that the positive polarities of

three phases CT. The voltage used by directional element is calculated by

three phase voltage. Details are shown as below.

Below figure shows an example of direction determination for a fault in phase

A. As can be seen from the figure, fault current 3I0 lags from fault voltage Va.

Accordingly, fault current -3I0 lags residual sequence voltage 3U0 by this

angle. The reference voltage 3U0 is rotated to be as close as possible to -3I0

current. Furthermore, the forward area is depicted in the figure.


106

Forward

Angle_EF

Bisector

0_Ref3U

0°

-3I 0

3I 090°

Angle_Range

EF

Figure 41 Characteristic of zero sequence directional element

where:

Angle_EF: The settable characteristic angle

Angle_Range EF: 80º

During direction decision by directional function, a VT Fail condition (a short circuit or broken wire in the voltage transformer's secondary system or an operation of the voltage transformer fuse) may result in false or undesired tripping by directional earth fault elements. In such a situation, it is possible to select operation status of the directional earth fault protection elements in each side by using a number of Binary settings to block the earth fault pro-tection elements or keep them in operational state with no direction decision (block direction decision). The Binary settings are designated as “Block HV EF at HV VT_Fail”, “Block MV EF at HV VT_Fail” and “Block LV EF at HV VT_Fail”, for HV, MV and LV sides, respectively. When the Binary settings are set as 0 to select “Direct OK at VT Fail”, corresponding earth fault protection elements will not judge direction at the local side VT failure. When they set as 1 to select “Block EF at VT Fail”, no operation is possible by the earth fault protection elements. It is noted that the Binary settings affect all the stages of corresponding earth fault elements at each side. For instance, by applying setting “Block HV EF at HV VT_Fail” off, all the three stages of the earth fault element will remain operative without direction determination in case of any fault in secondary circuit of HV side voltage transformer. On the other hand, setting “Block HV EF at HV VT_Fail” on makes them blocked.

It is possible to block earth fault protection elements in each side of the pro-tected transformer if a CT fail is detected in the same side. This can be per-formed by Binary settings “Block HV EF at HV CT_Fail”, “Blk MV EF at MV CT_FAIL” and “Blk LV EF at LV CT FAIL” in each voltage side. If setting 1 is applied to these Binary settings, any CT fail detection in a given side of the power transformer would bring blocking condition to all stages of the earth


107

fault element which is applied in the same side.

The logic for definite and inverse time IDMTL earth fault protection is shown in below figure.

E/F Trip

E/F Direction Unit OK

IDMTL E/F Trip

HV EF Direction

DIR Positive

VT failure


A

N

D

O

R

A

N

D

A

N

D

HV Func_EF1 (2) on

3I0>HV 3I0_EF1(2)

Direction Unit OK

Inrush BLK EF

HV T_EF1(2)

HV Func_EF1 (2) on

HV Func_EF Inv on

Inverse Curve>

E/F Direction OK

Inrush BLK EF

A

N

D

t

Figure 42 Tripping logic for earth fault protection


It is possible to set whether the earth fault protection elements can initiate the integrated CBF protection or not. The available choices depend on the volt-age side of the power transformer at which earth fault protection is applied. In this context, HV side earth fault protection element always initiates HV side CBF function with no additional setting. However, it is possible to select whether it can initiate MV and LV CBF protection functions via Binary settings “HV EF Initiate LV CBF” and “HV EF Initiate MV CBF” on, respectively.

MV side earth fault protection element always initiates MV side CBF function with no additional setting. However, it is possible to select whether it can ini-tiate HV side CBF protection function via Binary setting “MV EF Initiate HV1 CBF” on.

More detail information about the initiation conditions and related Binary set-tings can be found in below table.


108


IA1

IB1

IC1

IA2

IB2

IC2

UA

UB

UC

EF1 Trip

EF2 Trip

EF Inv Trip

Relay Startup

Earth Fault

Protection

Figure 43 Earth fault protection module


Signal Description







UA Phase A voltage input of VT of related winding of transformer

UB Phase B voltage input of VT of related winding of transformer

UC Phase C voltage input of VT of related winding of transformer


Signal Description

EF1 Trip Earth Fault stage 1 trip

EF2 Trip Earth Fault stage 2 trip

EF Inv Trip Earth Fault inverse stage trip


109

Signal Description


3 Setting

Table 51 Settings of earth fault protection for HV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

HV 3I0_EF1 A 0.05Ir 20Ir 5 HV earth fault (E/F) protection

current setting for Stage 1

HV T_EF1 s 0 60 60 Time setting for HV E/F, Stage 1

HV 3I0_EF2 A 0.05Ir 20Ir 5 HV earth fault (E/F) current set-

ting for Stage 2

HV T_EF2 s 0 60 60 Time setting for HV E/F, Stage 2

HV

Curve_EF

Inv


HV 3I0_EF

Inv A 0.05Ir 20Ir 1.2 Ref to IEC and ANSI Curves

HV K_EF

Inv 0.05 999 1 Ref to IEC and ANSI Curves

HV A_EF

Inv s 0 200 0.14 Ref to IEC and ANSI Curves

HV B_EF

Inv s 0 60 0 Ref to IEC and ANSI Curves

HV P_EF

Inv 0 10 0.02 Ref to IEC and ANSI Curves

HV An-

gle_EF ° 0 90 45


ahead of current.

HV

Imax_2H_U

nBlk_EF

A 0.25Ir 20Ir 5

The maximum 1st -harmonic cur-

rent setting to remove the inrush

block, in HV EF protection

HV Ra-

tio_I2/I1_EF 0.07 0.5 0.2



block, in HV EF protection


110

Table 52 Binary settings of earth fault protection for HV side of transformer


De-

fault

set-

ting

Description

HV Func_EF1 0 1 0

The 1st stage of HV earth fault

(EF_1) protection is switched ON

1-on; 0-off.

HV EF1 Direction 0 1 0

Direction (DIR) detection of HV EF


1-on; 0-off.

HV EF1 Dir To

Sys 0 1 0

Direction unit of HV EF Stage 1

points to system


1- point to system

HV EF1 Inrush

Block 0 1 0

Inrush 2nd


EF Stage 1 is switched ON

1-on; 0-off.

HV Func_EF2 0 1 0

The 2nd

stage of HV earth fault


1-on; 0-off.

HV EF2 Direction 0 1 0



1-on; 0-off.

HV EF2 Dir To

Sys 0 1 0

Direction unit of HV EF Stage 2

points to system


1- point to system

HV EF2 Inrush

Block 0 1 0

Inrush 2nd



1-on; 0-off.

HV Func_EF Inv 0 1 0

The IDMTL inverse time stage of HV

EF protection is switched ON

1-on; 0-off.

HV EF Inv Direc-

tion 0 1 0



1-on; 0-off.

HV EF Inv Dir To

Sys 0 1 0

Direction unit of HV EF IDMTL in-



111


1- point to system

HV EF Inv Inrush

Block 0 1 0

Inrush 2nd


EF IDMTL inverse time is switched

ON

1-on; 0-off.

Block HV EF at

HV VT_Fail 0 1 0

Select to block HV EF protection or

exit direction unit, when HV VT fails

0 - HV Direct OK at HV VT Fail

1 - Blk HV EF at HV VT Fail

Block HV EF at

HV CT_Fail 0 1 0

Block HV EF when there is HV CT

failure

1-Block; 0-NOT block

HV EF Initiate LV

CBF 0 1 0

HV EF protection initiate LV side

CBF


HV EF Initiate

MV CBF 0 1 0

HV EF protection initiate MV side

CBF


Table 53 Settings of earth fault protection for MV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

MV

3I0_EF1 A 0.05Ir 20Ir 5

MV earth fault (E/F) protection


MV T_EF1 s 0 60 60 Time setting for MV E/F, Stage 1

MV

3I0_EF2 A 0.05Ir 20Ir 5

MV earth fault (E/F) current set-

ting for Stage 2

MV T_EF2 s 0 60 60 Time setting for MV E/F, Stage 2

MV

Curve_EF

Inv


MV 3I0_EF

Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI Curves

MV K_EF

Inv 0.05 999 1 Ref to IEC and ANSI Curves

MV A_EF

Inv s 0 200 0.14 Ref to IEC and ANSI Curves


112

MV B_EF

Inv s 0 60 0 Ref to IEC and ANSI Curves

MV P_EF

Inv 0 10 0.02 Ref to IEC and ANSI Curves

MV An-

gle_EF ° 0 90 45


ahead of current.

MV

Imax_2H_U

nBlk_EF

A 0.25Ir 20Ir 5



block, in MV E/F protection

MV Ra-

tio_I2/I1_EF 0.07 0.5 0.2

Inrush 2nd

harmonic ratio setting

for blocking MV E/F protection

Table 54 Binary settings of earth fault protection for MV side of transformer


De-

fault

set-

ting

Description

MV Func_EF1 0 1 0

The 1st stage of MV earth fault


1-on; 0-off.

MV EF1 Direction 0 1 0

Direction (DIR) detection of MV EF


1-on; 0-off.

MV EF1 Dir To

Sys 0 1 0

Direction unit of MV EF Stage 1

points to system


1- point to system

MV EF1 Inrush

Block 0 1 0

Inrush 2nd



1-on; 0-off.

MV Func_EF2 0 1 0

The 2nd

stage of MV earth fault


1-on; 0-off.

MV EF2 Direction 0 1 0



1-on; 0-off.

MV EF2 Dir To

Sys 0 1 0

Direction unit of MV EF Stage 2

points to system


1- point to system


113

MV EF2 Inrush

Block 0 1 0

Inrush 2nd



1-on; 0-off.

MV Func_EF Inv 0 1 0

The IDMTL inverse time stage of MV


1-on; 0-off.

MV EF Inv Direc-

tion 0 1 0



1-on; 0-off.

MV EF Inv Dir To

Sys 0 1 0

Direction unit of MV EF IDMTL in-



1- point to system

MV EF Inv Inrush

Block 0 1 0

Inrush 2nd


EF IDMTL inverse time is switched

ON

1-on; 0-off.

Block MV EF at

MV VT_Fail 0 1 0

Select to block MV EF protection or

exit direction unit, when MV VT fails

0 - MV Direct OK at MV VT Fail

1 - Blk MV EF at MV VT Fail

Block MV EF at

MV CT_Fail 0 1 0

Block MV EF when there is MV CT

failure


MV EF Initiate

HV CBF 0 1 0

MV EF protection initiate HV1 side

CBF


Table 55 Settings of earth fault protection for LV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

LV 3I0_EF1 A 0.05Ir 20Ir 5 LV earth fault (E/F) protection


LV T_EF1 s 0 60 60 Time setting for LV E/F, Stage 1

LV 3I0_EF2 A 0.05Ir 20Ir 5 LV earth fault (E/F) current setting

for Stage 2

LV T_EF2 s 0 60 60 Time setting for LV E/F, Stage 2


114

LV

Curve_EF

Inv


LV 3I0_EF

Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI Curves

LV K_EF Inv 0.05 999 1 Ref to IEC and ANSI Curves

LV A_EF Inv s 0 200 0.14 Ref to IEC and ANSI Curves

LV B_EF Inv s 0 60 0 Ref to IEC and ANSI Curves

LV P_EF Inv 0 10 0.02 Ref to IEC and ANSI Curves

LV An-

gle_EF ° 0 90 45


ahead of current.

LV

Imax_2H_U

nBlk_EF

A 0.25Ir 20Ir 5



block, in LV E/F protection

LV Ra-

tio_I2/I1_EF 0.07 0.5 0.2

Inrush 2nd

harmonic ratio setting

for blocking LV E/F protection

Table 56 Binary settings of earth fault protection for LV side of transformer


De-

fault

set-

ting

Description

LV Func_EF1 0 1 0

The 1st stage of LV earth fault


1-on; 0-off.

LV EF1 Direction 0 1 0

Direction (DIR) detection of LV EF


1-on; 0-off.

LV EF1 Dir To

Sys 0 1 0

Direction unit of LV EF Stage 1

points to system


1- point to system

LV EF1 Inrush

Block 0 1 0

Inrush 2nd

harmonic detection LV EF


1-on; 0-off.

LV Func_EF2 0 1 0

The 2nd

stage of LV earth fault


1-on; 0-off.


115

LV EF2 Direction 0 1 0



1-on; 0-off.

LV EF2 Dir To

Sys 0 1 0

Direction unit of LV EF Stage 2

points to system


1- point to system

LV EF2 Inrush

Block 0 1 0

Inrush 2nd



1-on; 0-off.

LV Func_EF Inv 0 1 0

The IDMTL inverse time stage of LV


1-on; 0-off.

LV EF Inv Direc-

tion 0 1 0



1-on; 0-off.

LV EF Inv Dir To

Sys 0 1 0

Direction unit of LV EF IDMTL in-



1- point to system

LV EF Inv Inrush

Block 0 1 0

Inrush 2nd



1-on; 0-off.

Block LV EF at

LV VT_Fail 0 1 0

Select to block LV EF protection or

exit direction unit, when LV VT fails

0 - LV Direct OK at LV VT Fail

1 - Blk LV EF at LV VT Fail

Block LV EF at

LV CT_Fail 0 1 0

Block LV EF when there is LV CT

failure


LV EF Initiate HV

CBF 0 1 0

LV EF protection initiate HV1 side

CBF


4 Report




116


HV EF Inv Trip Inverse time stage of HV earth fault protection trip

HV EF1 Trip HV earth fault stage 1 trip


MV EF Inv Trip Inverse time stage of MV earth fault protection trip

MV EF1 Trip MV earth fault stage 1 trip


LV EF Inv Trip Inverse time stage of LV earth fault protection trip

LV EF1 Trip LV earth fault stage 1 trip




HV Func_EF On Earth fault protection of HV side is switched ON (by CW)

HV Func_EF Off Earth fault protection of HV side is switched OFF (by CW)

MV Func_EF On Earth fault protection of MV side is switched ON (by CW)

MV Func_EF Off Earth fault protection of MV side is switched OFF (by CW)

LV Func_EF On Earth fault protection of LV side is switched ON (by CW)

LV Func_EF Off Earth fault protection of LV side is switched OFF (by CW)

5 Technical data

Table 59 Earth fault protection technical data

Item Rang or value Tolerance





Reset ratio Approx. 0.95 at I/Ir ≥ 0.5




Very inverse;

Extremely inverse;

IEC60255-151


<I/ISETTING < 20


117

Long inverse

ANSI Inverse;

Short inverse;

Long inverse;

Moderately inverse;

Very inverse;

Extremely inverse;

Definite inverse

ANSI/IEEE C37.112,


<I/ISETTING < 20

user-defined characteristic

T=

IEC60255-151


<I/ISETTING < 20

Time factor of inverse time, A 0.005 to 200.0s, step

0.001s








Directional element

Operating area range of zero

sequence directional element 160°

≤ ±3°, at 3U0≥1V

Characteristic angle 0° to 90°, step 1°

Operating area range of negative

sequence directional element 160°

≤ ±3°, at 3U2≥2V



118

Chapter 8 Neutral earth fault protection

119


About this chapter This chapter describes the protection principle, input and output signals, parameter, IED report and technical data for neutral earth fault protection function.


120


1.1 Protection Elements

Each voltage side of the protected transformer is provided with three neutral earth fault protection elements from which two elements operate as definite earth fault stages and the other one operates with inverse time-current char-acteristic. All the elements can operate in conjunction with the integrated in-rush restraint and directional functions.

Various stages of each element are independent from each other and can be combined as desired. They can be enabled or disabled in each side using dedicated Binary settings. These Binary settings include “HV Func_Neu OC1”, “HV Func_Neu OC2” and “HV Func_Neu OC Inv”, for HV side earth fault protection, “MV Func_Neu OC1”, “MV Func_Neu OC2” and “MV Func_Neu OC Inv”, for MV side earth fault protection, “LV Func_Neu OC1”, “LV Func_Neu OC2” and “LV Func_Neu OC Inv”, for LV side earth fault protection. For example by applying setting “1-on” to “HV Func_Neu OC1”, respective stage of neutral earth fault protection would be enabled in HV side.

Individual pickup value for each definite stage can be defined by setting “HV 3I0_Neutral OC1” and “HV 3I0_Neutral OC2” for HV side, “MV 3I0_Neutral OC1” and “MV 3I0_Neutral OC2” for MV side, “LV 3I0_Neutral OC1” and “LV 3I0_Neutral OC2” for LV side. By applying these settings, each neutral current (quantity IN) measured from the installed neutral CT is compared separately with the setting value for each stage. If the respective value is exceeded, a trip time delay timer is started. The condition for start of the delay timer is ex-pressed mathematically:

setNN II _

Equation 35

The timer is set to count up to a user-defined time delay. The time delay can be set for each definite stage individually through settings “HV T_Neutral OC1” and “HV T_Neutral OC2” for HV side, “MV T_Neutral OC1” and “MV T_Neutral OC2” for MV side, “LV T_Neutral OC1” and “LV T_Neutral OC2” for LV side. After the user-defined time delay has been elapsed, a trip signal is issued if the inrush restraint feature is applied and no inrush current is de-tected or inrush restraint is disabled. The neutral earth fault protection would be blocked and therefore, no tripping takes place if the inrush restraint feature is enabled and an inrush condition exists. However, an alarm report is issued nominated as “HV Inrush Blk BU”, “MV Inrush Blk BU” or “LV Inrush Blk BU”, indicating the blocking condition of neutral earth fault element caused by in-rush condition detection.

Pickup value for the inverse time-current stage can be set by setting “HV 3I0_NOC Inv”, “MV 3I0_NOC Inv” and “LV 3I0_NOC Inv” for HV, MV and LV sides, respectively. Each neutral current (quantity IN) measured by installed neutral CT is separately compared with corresponding setting value. If a cur-rent exceeds 1.1 times the setting value, corresponding stage picks up. When


121

an inverse time-current stage picks up, the tripping time is calculated from the measured quantity IN, using the selected tripping curve. Maximum tripping time is limited to 100s.

For Time-inverse characteristic, the pickup value can be defined by setting “3I0_NOC Inv”. The measured zero sequence current is compared with cor-responding setting value. If it exceeds the setting, related signal will be re-ported and the tripping time is calculated according to the pre-defined char-acteristic. The tripping curve can be set as IEC or ANSI standard curves or any user-defined characteristic by following tripping time equation.

_

_ _ _

-1

P NOC Inv

S

A NOC Invt K NOC Inv B NOC Inv

I

I

Equation 36

Where I is the calculated neutral current;


where:

A_NOC Inv: Time factor for inverse time stage

B_ NOC Inv: Time delay for inverse time stage

P_ NOC Inv: index for inverse time stage

K_ NOC Inv: Time multiplier

As mentioned previously, selection between the curves can be carried out by settings “HV Curve_NOC Inv”, “MV Curve_NOC Inv” and “LV Curve_NOC Inv” for HV, MV and LV sides, respectively. Furthermore, the time multiplier K_NOC Inv can be applied by user to coordinate the integrated inverse time-current characteristic of the device with other relays installed for power system protection. This can be performed by settings “HV K_NOC Inv”, “MV K_NOC Inv” and “LV K_NOC Inv” in case of HV, MV and LV neutral earth fault elements.

By applying pickup current and time multiplier settings, the device determines the tripping time from the measured neutral current, based on the selected inverse curve. Once the calculated time has been elapsed, a trip signal is issued provided that no inrush current is detected or inrush restraint is disa-bled. If the inrush restraint feature is enabled and an inrush condition exists, the neutral earth fault protection would be blocked and therefore no tripping takes place. However, alarm report of “HV Inrush Blk BU”, “MV Inrush Blk BU” or “LV Inrush Blk BU” is issued, indicating the blocking condition of neutral earth fault element caused by inrush condition detection.

The trip signals and corresponding event reports are available separately for each stage. They include “HV Neu OC_1 Trip”, “HV Neu OC_2 Trip” and “HV Neu OC IDMTL” for HV side, “MV Neu OC_1 Trip”, “MV Neu OC_2 Trip” and “MV Neu OC IDMTL” for MV side, “LV Neu OC_1 Trip”, “LV Neu OC_1 Trip”


122

and “LV Neu OC IDMTL” for LV side neutral earth fault elements.


The transformer neutral earth fault protection may detect large magnetizing inrush currents flowing when transformer is energized. The inrush current may be several times of the nominal current, and may last from several tens of milliseconds to several seconds.

Inrush current comprises second harmonic as well as a considerable funda-mental component. So, it may affect neutral earth fault protection which op-erates based on the fundamental component of the measured current. Inrush blocking unit in neutral earth fault function is provided for this purpose.

It is possible to apply the inrush restraint feature separately to each definite stage and inverse time-current stage of earth fault element by using Binary settings “HV Neu OC1 Inrush Block”, “HV Neu OC2 Inrush Block” and “HV Neu OC Inv Inrush Block” on for HV side, “MV Neu OC1 Inrush Block”, “MV Neu OC2 Inrush Block” and “MV Neu OC Inv Inrush Block” on for MV side, “LV Neu OC1 Inrush Block”, “LV Neu OC2 Inrush Block” and “LV Neu OC Inv Inrush Block” on for LV side. By applying setting “1-on” to each of the men-tioned Binary settings, no trip command would be possible by corresponding stage, if an inrush condition is detected.

Since the inrush current contains a relatively large second harmonic compo-nent which is nearly absent during a fault current, the inrush restraint oper-ates based on the evaluation of the second harmonic content which is present in the measured neutral current (quantity IN), or in the phase currents, based on setting. The inrush condition is recognized if the ratio of second harmonic current to the fundamental component exceeds the setting value “HV Ra-tio_I2/I1_NOC”, “MV Ratio_I2/I1_NOC” or “LV Ratio_I2/I1_NOC” in the measured neutral current. The setting is applicable to both the definite stages of neutral earth fault protection element as well as the inverse time-current stage. As soon as the measured ratio exceeds the set threshold, a restraint is applied to those stages for which corresponding setting is applied to make them blocked in inrush condition detection (“HV Neu OC1 Inrush Block”, “HV Neu OC2 Inrush Block” and “HV Neu OC Inv Inrush Block” for HV side, “MV Neu OC1 Inrush Block”, “MV Neu OC2 Inrush Block” and “MV Neu OC Inv Inrush Block” for MV side, “LV Neu OC1 Inrush Block”, “LV Neu OC2 Inrush Block” and “LV Neu OC Inv Inrush Block” for LV side).

Furthermore, if the fundamental component of the measured neutral current exceeds the upper limit value “HV Imax_2H_UnBlk_NOC”, “MV Imax_2H_UnBlk_NOC” or “LV Imax_2H_UnBlk_NOC”, the inrush restraint will no longer effective in respective side, since a high-current fault is as-sumed in this case.


The integrated directional function can be applied to each stage of neutral earth fault elements via Binary settings. The Binary settings include “HV Neu OC1 Direction”, “HV Neu OC2 Direction” and “HV Neu OC Inv Direction” on for HV side earth fault stages, “MV Neu OC1 Direction”, “MV Neu OC2 Direc-tion” and “MV Neu OC Inv Direction” for MV side earth fault stages and “LV


123

Neu OC1 Direction”, “LV Neu OC2 Direction” and “LV Neu OC Inv Direction” for LV side earth fault stages.

Furthermore, the directional orientation can be set individually for each stage of neutral earth fault elements in various sides of the protected transformer. This can be performed by Binary settings “HV Neu OC1 Dir To Sys”, “HV Neu OC2 Dir To Sys” and “HV Neu OC Inv Dir To Sys” for HV side, “MV Neu OC1 Dir To Sys”, “MV Neu OC2 Dir To Sys” and “MV Neu OC Inv Dir To Sys” for MV side, “LV Neu OC1 Dir To Sys”, “LV Neu OC2 Dir To Sys” and “LV Neu OC Inv Dir To Sys” for LV side. The possible settings for these Binary setting comprise “0-toward transformer” and “1-toward system”.

Basically, the direction determination is performed by comparing the zero sequence system quantities. In the current path, 3I0 current is measured from the neutral CT installed at the transformer starpoint. In the voltage path, the device calculates the zero sequence voltage 3V0 from the sum of the three phase voltages. Contrary to the directional phase elements, which work with the un-faulted voltage as reference voltage, in this application, the fault volt-age itself is the reference voltage. Depending on the connection of the volt-age transformer, this is the voltage 3V0 or VN. The directional element at each side operates with the residual/ neutral voltage of the same side.

In order to satisfy different network conditions and applications, the reference voltage can be rotated by an adjustable angle. For each side of the protected transformer, the directional angle can be set independently. The settings in-clude “HV Angle_NOC”, “MV Angle_NOC” and “LV Angle_NOC”, for HV, MV and LV sides, respectively. It should be noted that the settings affect all the directional stages of the corresponding neutral earth fault element.

Forward

Angle_EF

Bisector

0_Ref3U

0°

-3I 0

3I 090°

Angle_Range

EF

Figure 44 Neutral directional element characteristic

where:

Angle_OC: The settable characteristic angle

Angle_Range OC: 80º


124

During direction decision by directional function, a VT Fail condition (a short circuit or broken wire in the voltage transformer's secondary system or an operation of the voltage transformer fuse) may result in false or undesired tripping by directional neutral earth fault elements. In such a situation, it is possible to select operation status of the directional neutral earth fault pro-tection elements in each side by using a number of Binary settings to block the neutral earth fault protection elements or keep them in operational state with no direction decision (block direction decision). The Binary settings are designated as “Block HV NOC at HV VT_Fail”, “Block MV NOC at HV VT_Fail” and “Block LV NOC at HV VT_Fail”, for HV, MV and LV sides, re-spectively. When the Binary settings are set as 0 to select “Direct OK at VT Fail”, corresponding neutral earth fault protection elements will not judge di-rection at the local side VT failure. When they set as 1 to select “Blk NEU OC at VT Fail”, no operation is possible by the neutral earth fault protection ele-ments. It is noted that the Binary settings affect all the stages of correspond-ing neutral earth fault elements at each side. For instance, by applying setting “Block HV NOC at HV VT_Fail” off, all the three stages of the neutral earth fault element will remain operative without direction determination in case of any fault in secondary circuit of HV side voltage transformer. On the other hand, setting “Block HV NOC at HV VT_Fail” on makes them blocked.

The logic for definite and inverse time IDMTL neutral earth fault protection is shown in below figure.

1) t: T_Neutral OC1(2)

t

Func_Neu OC1（ 2（ on

Dir_Forward

Func_Neu OC1（ 2（ on

3I0 > 3I0_Neutral OC1（ 2（

Func_Neu OC Inv on

And

And

Or

NEF Direction Unit OK

Inrush BLK NEF

3I0>3I0_NOC Inv


Inrush BLK NOC


VT failure

And

And

NEF Inv Trip

Neutral EF Trip


1)

t

Figure 45 Tripping logic for neutral earth fault protection



125

It is possible to set whether the neutral earth fault protection elements can in-itiate the integrated CBF protection or not. The available choices depend on the voltage side of the power transformer at which neutral earth fault protec-tion is applied. In this context, HV side neutral earth fault protection element always initiates HV side CBF function with no additional setting. However, it is possible to select whether it can initiate MV and LV CBF protection functions via Binary settings “HV Neu OC Init LV CBF” and “HV Neu OC Init MV CBF”, respectively.

MV side neutral earth fault protection element always initiates MV side CBF function with no additional setting.


NEF1 TripINBK

NEF2 Trip

NEF Inv Trip

UA

UB

UC Relay Startup

Neutral Earth

Fault Protection

Figure 46 Neutral earth fault protection module

Table 60 Analog output list

Signal Description

INBK Neutral current input of HV side, MV side, or LV side of transformer

UA Phase A voltage input of HV side, MV side, or LV side of transformer

UB Phase B voltage input of HV side, MV side, or LV side of transformer

UC Phase C voltage input of HV side, MV side, or LV side of transformer


Signal Description

NOC1 Trip Neutral Earth Fault stage 1 trip

NOC2 Trip Neutral Earth Fault stage 2 trip

NOC Inv Trip Neutral Earth Fault inverse stage trip



126

3 Setting

Table 62 Settings of neutral earth fault protection for HV side of transformer

Setting Unit Min.

(Ir:5A/1A)

Max. (Ir:5A/1

A)

Default setting (Ir:5A/1

A)

Description

c A 0.05Ir 20Ir 5

HV neutral over-current (NOC)

protection current setting for Stage

1

HV T_Neutral OC1

s 0 60 60 Time setting for HV NOC, Stage

1

HV 3I0_Neutral OC2

A 0.05Ir 20Ir 5

HV neutral over-current (NOC)

protection current setting for Stage

2

HV T_Neutral OC2

s 0 60 60 Time setting for HV NOC, Stage

1

HV Curve_NOC Inv


HV 3I0_NOC Inv

A 0.05Ir 20Ir 5 Ref to IEC and ANSI Curves

HV K_NOC Inv

0.05 999 1 Ref to IEC and ANSI Curves

HV A_NOC Inv

s 0 200 0.14 Ref to IEC and ANSI Curves

HV B_NOC Inv

s 0 60 0 Ref to IEC and ANSI Curves

HV P_NOC Inv

0 10 0.02 Ref to IEC and ANSI Curves

HV An-gle_NOC

° 0 90 45 The angle setting for voltage

ahead of current.

HV Imax_2H_UnBlk_NOC

A 0.25Ir 20Ir 5



inrush block, in HV NOC pro-

tection

HV Ra-tio_I2/I1_NOC

0.07 0.5 0.2 Inrush 2

nd harmonic ratio setting

for blocking HV NOC protection

Table 63 Binary settings of neutral earth fault protection for HV side of transformer


De-fault set-ting

Description


127

HV Func_Neu OC1

0 1 0

The 1st stage of HV neutral OC

(OC_1) protection is switched

ON

1-on; 0-off.

HV Neu OC1 Di-rection

0 1 0

Direction (DIR) detection of HV

neutral OC Stage 1 is switched

ON

1-on; 0-off.

HV Neu OC1 Dir To Sys

0 1 0

Direction unit of HV neutral OC

Stage 1 points to system

0 - point to the protected trans-

former

1- point to system

HV Neu OC1 In-rush Block

0 1 0

Inrush 2nd harmonic detection

HV neutral OC Stage 1 is

switched ON

1-on; 0-off.

HV Func_Neu OC2

0 1 0

The 2nd stage of HV neutral OC


ON

1-on; 0-off.

HV Neu OC2 Di-rection

0 1 0



ON

1-on; 0-off.

HV Neu OC2 Dir To Sys

0 1 0




former

1- point to system

HV Neu OC2 In-rush Block

0 1 0



switched ON

1-on; 0-off.

HV Func_Neu OC Inv

0 1 0

The IDMTL inverse time stage

of HV neutral OC protection is

switched ON

1-on; 0-off.

HV Neu OC Inv Direction

0 1 0


neutral OC IDMTL inverse time

stage is switched ON

1-on; 0-off.

HV Neu OC Inv Dir To Sys

0 1 0


IDMTL inverse time stage points

to system


former

1- point to system


128

HV Neu OC Inv Inrush Block

0 1 0


HV neutral OC IDMTL inverse

time stage is switched ON

1-on; 0-off.

Block HV NOC at HV VT_Fail

0 1 0

Select to block HV neutral OC protection or exit direction unit, when HV VT fails 0 - HV Direct OK at HV VT Fail 1 - Blk HV NOC at HV VT Fail

HV Neu OC Init MV CBF

0 1 0

HV neutral OC protection initi-

ate LV side CBF


Table 64 Settings of neutral earth fault protection for MV side of transformer

Setting Unit Min.

(Ir:5A/1A)

Max. (Ir:5A/1

A)


A)

Description

MV 3I0_Neutral OC1

A 0.05Ir 20Ir 5

MV neutral over-current (NOC)

protection current setting for

Stage 1

MV T_Neutral OC1

s 0 60 60 Time setting for MV NOC, Stage

1

MV 3I0_Neutral OC2

A 0.05Ir 20Ir 5

MV neutral over-current (NOC)


Stage 2

MV T_Neutral OC2

s 0 60 60 Time setting for MV NOC, Stage

1

MV Curve_NOC Inv


MV 3I0_NOC Inv


MV K_NOC Inv


MV A_NOC Inv


MV B_NOC Inv


MV P_NOC Inv


MV An-gle_NOC


ahead of current.

MV Imax_2H_UnBlk_NOC

A 0.25Ir 20Ir 5



inrush block, in MV NOC pro-

tection


129

MV Ra-tio_I2/I1_NOC

0.07 0.5 0.2 Inrush 2


for blocking MV NOC protection

Table 65 Binary settings of neutral earth fault protection for MV side of transformer


De-fault set-ting

Description

MV Func_Neu OC1

0 1 0

The 1st stage of MV neutral OC


ON

1-on; 0-off.

MV Neu OC1 Di-rection

0 1 0

Direction (DIR) detection of MV


ON

1-on; 0-off.

MV Neu OC1 Dir To Sys

0 1 0

Direction unit of MV neutral OC



former

1- point to system

MV Neu OC1 In-rush Block

0 1 0


MV neutral OC Stage 1 is

switched ON

1-on; 0-off.

MV Func_Neu OC2

0 1 0

The 2nd stage of MV neutral OC


ON

1-on; 0-off.

MV Neu OC2 Di-rection

0 1 0

Direction (DIR) detection of MV


ON

1-on; 0-off.

MV Neu OC2 Dir To Sys

0 1 0




former

1- point to system

MV Neu OC2 In-rush Block

0 1 0



switched ON

1-on; 0-off.

MV Func_Neu OC Inv

0 1 0


of MV neutral OC protection is

switched ON

1-on; 0-off.

MV Neu OC Inv Direction

0 1 0 Direction (DIR) detection of MV



130


1-on; 0-off.

MV Neu OC Inv Dir To Sys

0 1 0



to system


former

1- point to system

MV Neu OC Inv Inrush Block

0 1 0


MV neutral OC IDMTL inverse


1-on; 0-off.

Block MV NOC at MV VT_Fail

0 1 0

Select to block MV neutral OC protection or exit direction unit, when MV VT fails 0 - MV Direct OK at MV VT Fail 1 - Blk MV NOC at MV VT Fail

MV Neu OC Init MV CBF

0 1 0

MV neutral OC protection initi-

ate LV side CBF


Table 66 Settings of neutral earth fault protection for LV side of transformer

Setting Unit Min.

(Ir:5A/1A)

Max. (Ir:5A/1

A)


A)

Description

LV 3I0_Neutral OC1

A 0.05Ir 20Ir 5

LV neutral over-current (NOC)


Stage 1

LV T_Neutral OC1

s 0 60 60 Time setting for LV NOC, Stage 1

LV 3I0_Neutral OC2

A 0.05Ir 20Ir 5

LV neutral over-current (NOC)


Stage 2

LV T_Neutral OC2

s 0 60 60 Time setting for LV NOC, Stage 1

LV Curve_NOC Inv


LV 3I0_NOC Inv


LV K_NOC Inv


LV A_NOC Inv


LV B_NOC Inv



131

LV P_NOC Inv


LV An-gle_NOC


ahead of current.

LV Imax_2H_UnBlk_NOC

A 0.25Ir 20Ir 5



inrush block, in LV NOC protec-

tion

LV Ra-tio_I2/I1_NOC

0.07 0.5 0.2 Inrush 2


for blocking LV NOC protection

Table 67 Binary settings of neutral earth fault protection for LV side of transformer


De-fault set-ting

Description

LV Func_Neu OC1 0 1 0

The 1st stage of LV neutral OC


ON

1-on; 0-off.

LV Neu OC1 Di-rection

0 1 0

Direction (DIR) detection of LV


ON

1-on; 0-off.

LV Neu OC1 Dir To Sys

0 1 0

Direction unit of LV neutral OC



former

1- point to system

LV Neu OC1 In-rush Block

0 1 0


LV neutral OC Stage 1 is

switched ON

1-on; 0-off.

LV Func_Neu OC2 0 1 0

The 2nd stage of LV neutral OC


ON

1-on; 0-off.

LV Neu OC2 Di-rection

0 1 0



ON

1-on; 0-off.

LV Neu OC2 Dir To Sys

0 1 0




former

1- point to system

LV Neu OC2 In-rush Block

0 1 0 Inrush 2nd harmonic detection



132

switched ON

1-on; 0-off.

LV Func_Neu OC Inv

0 1 0


of LV neutral OC protection is

switched ON

1-on; 0-off.

LV Neu OC Inv Direction

0 1 0




1-on; 0-off.

LV Neu OC Inv Dir To Sys

0 1 0



to system


former

1- point to system

LV Neu OC Inv Inrush Block

0 1 0


LV neutral OC IDMTL inverse


1-on; 0-off.

Block LV NOC at LV VT_Fail

0 1 0

Select to block LV neutral OC protection or exit direction unit, when LV VT fails 0 - LV Direct OK at LV VT Fail 1 - Blk LV NOC at LV VT Fail

LV Neu OC Init LV CBF

0 1 0

LV neutral OC protection initiate

LV side CBF


4 Report



HV NOC Inv Trip Inverse time stage of neutral OC protection trip

HV NOC1 Trip HV neutral OC stage 1 trip


MV EF Inv Trip Inverse time stage of MV neutral OC protection trip

MV EF1 Trip MV neutral OC stage 1 trip


LV EF Inv Trip Inverse time stage of LV neutral OC protection trip

LV EF1 Trip LV neutral OC stage 1 trip



133



HV Func_NOC On NOC protection of HV side is switched ON (by CW)

HV Func_NOC Off NOC protection of HV side is switched OFF (by CW)

MV Func_NOC On NOC protection of MV side is switched ON (by CW)

MV Func_NOC Off NOC protection of MV side is switched OFF (by CW)

LV Func_NOC On NOC protection of LV side is switched ON (by CW)

LV Func_NOC Off NOC protection of LV side is switched OFF (by CW)

5 Technical data

Table 70 Neutral earth fault protection technical data

Item Rang or value Tolerance





Reset ratio Approx. 0.95 at I/Ir ≥ 0.5




Very inverse;

Extremely inverse;

Long inverse

≤ ±5% setting + 40ms, at 2 <I/ISETTING < 20, in accordance with IEC60255-151

ANSI Inverse;

Short inverse;

Long inverse;

Moderately inverse;

Very inverse;

Extremely inverse;

Definite inverse

≤ ±5% setting + 40ms, at 2 <I/ISETTING < 20, in accordance with ANSI/IEEE C37.112,

user-defined characteristic T=

≤ ±5% setting + 40ms, at 2 <I/ISETTING < 20, in accordance with IEC60255-151

Time factor of inverse time, A 0.005 to 200.0s, step

0.001s








Directional element

Operating area range 160° ≤ ±3°, at 3U0≥1V


134


Operating area range 160° ≤ ±3°, at 3U2≥2V


Chapter 9 Thermal overload protection

135


About this chapter This chapter describes the protection principle, input and output signals, parameter, IED report and technical data for thermal overload protection function.


136

1 Introduction

The insulating material surrounding the transformer windings ages rapidly if the temperature exceeds the design limit value. Furthermore, by using less and less metal per MVA of transformed power, the designed limit value is reduced in modern power transformers. Hence, it represents an essential requirement to provide thermal protection to supplement the winding temper-ature device. The thermal overload protection estimates winding temperature and therefore prevents damage to transformer caused by thermal overload-ing.


The thermal overload protection includes two stages (alarm and trip). They work by using an approximate replica of the temperature rise in the protected object caused by overload. The thermal replica is implemented based on thermal models (Cold / Hot Curve) of IEC60255-8 Std., without ambient temperature influence.

Both of the alarm and trip stages can be enabled or disabled by using Binary setting “HV Func_Thermal OvLd”, “MV Func_Thermal OvLd” or “LV Func_Thermal OvLd” on. The thermal overload protection can be assigned to any desired side (HV, MV or LV) of the protected object. However, for trans-formers with tap changer, it is recommended to use the function on the non-regulated side. To enable the protection on each side, setting of “1-on” should be applied to corresponding Binary setting.

Both of the thermal overload stages can use cold curve or hot curve in their calculations, based on the setting applied at Binary setting “HV Cold Curve”, “MV Cold Curve” or “LV Cold Curve”. If the protection is enabled in one side, and the measured current in each phase of the protected transformer in cor-responding side exceeds the threshold defined by setting “HV I_Therm OL Alarm”, “MV I_Therm OL Alarm” or “LV I_Therm OL Alarm”, a counter is in-cremented from 0% to 100%. When the counter is accumulated to its alarm setting which correspond to the expiration of alarm time delay according to the selected cold/hot characteristic, the alarm report “HV Load Alarm”, “MV Load Alarm” or “LV Load Alarm” is given to allow a preventive load reduction. The alarm signal is cancelled as soon as the measured phase current falls below the threshold defined by setting “HV I_Therm OL Alarm”, “MV I_Therm OL Alarm” or “LV I_Therm OL Alarm”. However, the counter is decremented to zero according to cool down time of the transformer (the time by which the thermal replica counter reaches from 100% to 0%). The cool down time is informed to the device by setting “HV T_Const Cool Down”, “MV T_Const Cool Down” and “LV T_Const Cool Down”.

Similarly, if the measured current in each phase of the protected transformer in corresponding side exceeds the threshold defined by setting “HV I_Therm OL Trip”, “MV I_Therm OL Trip” or “LV I_Therm OL Trip”, a counter is incre-mented from 0% to 100%. If the counter reaches to 100% corresponding to expiration of trip time delay according to the selected cold/hot characteristic, the event report “HV THERM Trip”, “MV THERM Trip” or “LV THERM Trip” is


137

given. The alarm signal is cancelled as soon as the measured phase current falls below the threshold defined by setting “HV I_Therm OL Trip”, “MV I_Therm OL Trip” or “LV I_Therm OL Trip”. However, the counter is decre-mented to zero according to cool down time of the transformer which is en-tered into the device by setting “HV T_Const Cool Down”, “MV T_Const Cool Down” and “LV T_Const Cool Down”.

The cold and hot curves used in each thermal overload stages, is based on thermal curves defined in IEC 60255-8 Std.

The curves provide an operating current/time characteristic that corresponds to the current overload characteristic of the transformer windings. The for-mulas corresponding to cold and hot curve is denoted by (1-46) and (1-47), respectively. The cold curve provides no memory regarding to previous thermal condition of the transformer, whereas, by using the hot curve, the protection function is able to represent a memorized thermal profile of the protected transformer.

22

2

ln

II

It

ph

ph

Equation 37

22

22

ln

II

IIt

ph

Pph

Equation 38

Where,

t is alarm/trip time of thermal overload protection function in seconds,

τ is thermal time constant of heating for the power transformer, in seconds. It is usually provided by the manufacturer. The device is informed about it by settings “HV T_Const Therm”, “MV T_Const Therm” and “H\LV T_Const Therm”.

Iph is the current flowing through corresponding side of the transformer, in each phase. It means that the calculation is performed separately for each phase, based on fundamental component measurement and also includes the effect of harmonic contents up to 7th harmonic. Thus, the minimum cal-culated alarm/ trip time is decisive for evaluation of the thresholds.

IΘ is the setting for alarm and trip stages of the thermal overload protection, in rms. It should be set considering the maximum permissible thermal continu-ous overload current of the transformer windings and insulations. The setting is applied by using “HV I_Therm OL Alarm” and “HV I_Therm OL Trip” for HV side, “MV I_Therm OL Alarm” and “HV I_Therm OL Trip” for MV side, and “H\LV I_Therm OL Alarm” and “HV I_Therm OL Trip” for LV side of the power transformer.

IP is the prior current to overload, assuming sufficient time to reach


138

steady-state temperature.

NOTE: When Binary setting “xx Curve/Hot Curve” is set to 0, and fundamental current is less than the settings, and the heat accumulation is cleared and set as “0” automatically.


IA1

IB1

IC1

IA2

IB2

IC2

Therm OL Trip

Therm OL Alarm

Relay Startup

Thermal Overload

Protection

Figure 47 Thermal overload protection module


Signal Description








Signal Description

Therm OL Trip Thermal overload trip

Therm OL Alarm Thermal overload alarm


4 Setting

Table 73 Settings of thermal overload protection for HV side of transformer

Setting Unit Min.

(Ir:5A/Max.

(Ir:5A/Default setting

Description


139

1A) 1A) (Ir:5A/1A)

HV I_Therm OL Trip A 0.1Ir 5Ir 2 Setting for HV-side thermal

overload trip-stage current

HV I_Therm OL Alarm A 0.1Ir 5Ir 2

Setting for HV-side thermal

overload alarm-stage cur-

rent

HV T_Const Therm s 1 9999 10 Time const for HV-side

thermal overload protection

HV T_Const Cool Down

s 1 9999 10 Cool down time delay for

HV-side thermal overload

Table 74 Binary settings of thermal overload protection for HV side of transformer


De-fault set-ting

Description

HV Func_Thermal

OvLd 0 1 0

Thermal overload in HV

side is switched on

0 - OFF, 1 - ON

HV Cold Curve 0 1 0

HV side using hot/cold

curve type

0 – Hot curve, 1 – Cold

curve

HV Thermal Init LV

CBF 0 1 0

HV thermal overload pro-

tection initiate LV side CBF


HV Thermal Init MV

CBF 0 1 0

HV thermal overload pro-

tection initiate MV side

CBF


Table 75 Settings of thermal overload protection for MV side of transformer

Setting Unit Min.

(Ir:5A/1A)

Max. (Ir:5A/

1A)

Default setting (Ir:5A/

1A)

Description

MV I_Therm OL Trip A 0.1Ir 5Ir 2 Setting for MV-side thermal


MV I_Therm OL Alarm

A 0.1Ir 5Ir 2

Setting for MV-side thermal


rent

MV T_Const Therm s 1 9999 10 Time const for MV-side


MV T_Const Cool Down


MV-side thermal overload


140

Table 76 Binary settings of thermal overload protection for MV side of transformer


De-fault set-ting

Description

MV Func_Thermal

OvLd 0 1 0

Thermal overload in MV

side is switched on

0 - OFF, 1 - ON

MV Cold Curve 0 1 0

MV side using hot/cold

curve type

0 – Hot curve, 1 – Cold

curve

MV Thermal Init HV1

CBF 0 1 0

MV thermal overload pro-

tection initiate HV side

CBF


5 Report



HV Therm OL Trip HV Thermal (TEM) Overload(OVLD) tripping (Trip)

MV Therm OL Trip MV Thermal (TEM) Overload(OVLD) tripping (Trip)



HV Therm OL Alm HV Thermal overload Alarm

MV Therm OL Alm MV Thermal overload Alarm



HV Func_Therm On HV thermal overload protection is switched ON (by CW)

HV Func_Therm Off HV thermal overload protection is switched OFF (by CW)

MV Func_Therm On MV thermal overload protection is switched ON (by CW)

MV Func_Therm Off MV thermal overload protection is switched OFF (by CW)


141

6 Technical data

Table 80 Thermal overload protection technical data



Thermal heating time constant 1 to 9999 s

Thermal cooling time constant 1 to 9999 s

IEC cold curve

22

2

ln

II

It

eq

eq

IEC 60255–8, ≤ ±5% setting or +40ms

IEC hot curve

22

22

ln

II

IIt

eq

Peq

IEC 60255–8, ≤ ±5% setting or +40ms


142

Chapter 10 Overload protection

143


About this chapter This chapter describes the protection principle, input and output signals, parameter, IED report and technical data for overload protection function.


144


Overload protection is equipped for each voltage side and LV delta winding. The function is to protect all sides of windings of transformer continuous overload currents.

HV or MV or LV overload protection only comprises a definite time alarm stage.

Load Alarm

HV T_OverLoadHV Func_OverLoad onA

N

DMax(IA,IB,IC)>HV

I_OverLoad

Figure 48 The logic for HV overload protection

The LV winding overload includes one alarm and two definite time tripping stages, namely low-setting tripping stage and high-setting tripping stage. The two tripping stage can be set respective to initiate each side CBF or not

The logic for overload protection is shown in below figure.

LW Load Alarm & T_OverLo

ad

LW Load Low_Stg & LW T_OvLd

Low Trip

LW Load High_Stg & LW T_OvLd High

Trip

LW Func_OvLd Alarm on

LW Func_OvLd Low Trip on

LW Func_OvLd High Trip on

Max(IA,IB,IC)> I_OverLoad

Max(IA,IB,IC)> LW I_OvLd

Low Trip

Max(IA,IB,IC)>LW I_OvLd

High Trip

Figure 49 The logic for LV winding overload protection


145


IA1

IB1

IC1

IA2

IB2

IC2

Overload Alarm

Relay Startup

Overload Protection

Figure 50 Overload protection module for HV, MV, or LV side of transformer

IA

IB

IC

Overload high set trip

Relay Startup

Overload Alarm

Overload low set trip

Delta Winding

Overload Protection

Figure 51 Overload protection module for LV delta winding of transformer


Signal Description








Signal Description

Overload Alarm Overload Alarm



146

3 Setting

Table 83 Setting of overload protection for HV side of transformer

Setting Unit Min.

(Ir:5A/1A)

Max. (Ir:5A/

1A)

De-fault set-ting

(Ir:5A/1A)

Description

HV I_OverLoad A 0.1Ir 4Ir 2 Overcurrent Setting of overload

HV T_OverLoad s 0.1 3600 10 Time setting for overload

Table 84 Binary settings of overload protection for HV side of transformer


De-fault set-ting

Description

HV Func_OverLoad 0 1 0 Overload (LOAD) protection in

HV side is switched ON

1-on; 0-off.

Table 85 Setting of overload protection for MV side of transformer

Setting Unit Min.

(Ir:5A/1A)

Max. (Ir:5A/

1A)

De-fault set-ting

(Ir:5A/1A)

Description

MV I_OverLoad A 0.1Ir 4Ir 2 Overcurrent Setting of overload

MV T_OverLoad s 0.1 3600 10 Time setting for overload

Table 86 Binary settings of overload protection for MV side of transformer


De-fault set-ting

Description

MV Func_OverLoad 0 1 0 Overload (LOAD)in MV side

on

Table 87 Setting of overload protection for LV side of transformer

Setting Unit Min.

(Ir:5A/1A)

Max. (Ir:5A/

1A)

De-fault set-ting

(Ir:5A/1A)

Description

LV I_OverLoad A 0.1Ir 4Ir 2 Overcurrent Setting of overload


147

LV T_OverLoad s 0.1 3600 10 Time setting for overload

Table 88 Binary settings of overload protection for LV side of transformer


De-fault set-ting

Description

LV Func_OverLoad 0 1 0 Overload (LOAD)in LV side on

Table 89 Setting of overload protection for LV delta winding of transformer

Setting Unit Min.

(Ir:5A/1A)

Max. (Ir:5A/

1A)

De-fault set-ting

(Ir:5A/1A)

Description

LW I_OvLd Alarm A 0.1Ir 4Ir 20 Alarm current setting of LV delta

winding overload protection

LW T_OvLd Alarm s 0.1 3600 10 Alarm time setting of LV delta

winding overload protection

LW I_OvLd Low Trip

A 0.1Ir 4Ir 20 Low stage tripping current setting

LW T_OvLd Low Trip

s 0.1 3600 10 Low stage tripping time setting

LW I_OvLd High Trip

A 0.1Ir 4Ir 20 High stage tripping current setting

LW T_OvLd High Trip

s 0.1 3600 10 High stage tripping time setting

Table 90 Binary settings of overload protection for LV delta winding of transformer


De-fault set-ting

Description

LW Func_OvLd

Alarm 0 1 0

Alarm stage of LV delta wind-ing (LWIND) overload (LOAD) protection is switched ON. 1-on; 0-off.

LW Func_OvLd Low

Trip 0 1 0

Low-setting trip stage of LV delta winding overload protec-tion is switched ON. 1-on; 0-off.

LW Func_OvLd High

Trip 0 1 0

High-setting trip stage of LV delta winding overload protec-tion is switched ON. 1-on; 0-off.

Low Trip Init HV1 CBF 0 1 0

Low-setting trip stage of LV

delta winding overload protec-

tion initiate HV1 side CBF



148

High Trip Init HV1 CBF 0 1 0

High-setting trip stage of LV


tion initiate HV1 side CBF


Low Trip Init MV CBF 0 1 0



tion initiate MV side CBF


High Trip Init MV CBF 0 1 0




- initiate, 1 – not initiate

4 Report



LW Load Low_Stg LV delta winding (LWIND) overload (LOAD) protection low setting trip

LW Load High_Stg LV delta winding (LWIND) overload (LOAD) protection high setting trip



HV Load Alarm HV overload Alarm

MV Load Alarm MV overload Alarm

LV Load Alarm LV overload Alarm



HV Func_OL On HV overload protection is switched ON (by CW)

HV Func_OL Off HV overload protection is switched OFF (by CW)

MV Func_OL On MV overload protection is switched ON (by CW)

MV Func_OL Off MV overload protection is switched OFF (by CW)

LV Func_OL On LV overload protection is switched ON (by CW)

LV Func_OL Off LV overload protection is switched OFF (by CW)

Chapter 11 Overvoltage protection

149



signals, parameter, IED report and technical data used for over-

voltage protection.


150

5 Introduction

Voltage protection has the function to protect electrical equipment against

overvoltage condition. Abnormally high voltages often occur e.g. in low

loaded, long distance transmission lines, in islanded systems when generator

voltage regulation fails, or after full load shutdown of a generator from the

system. Even if compensation reactors are used to avoid line overvoltage by

compensation of the line capacitance and thus reduction of the overvoltage,

the overvoltage will endanger the insulation if the reactors fail (e.g. fault

clearance). The line must be disconnected within very short time.

The protection provides the following features:

Two definite time stages

Each stage can be set to alarm or trip

Measuring voltage between phase-earth voltage and phase-phase (se-

lectable)

Settable dropout ratio


6.1 Phase to phase overvoltage protection

All the three phase voltages are measured continuously, and compared with

the corresponding setting value. If a phase voltage exceeds the set thresh-

olds, “HV U_OV1” or “HV U_OV2” for HV said, “MV U_OV1” or “MV U_OV2”

for MV said, after expiry of the time delays, “HV T_OV1’ or “HV T_OV2”, and

“MV T_OV1’ or “MV T_OV2”, the protection IED will issue alarm signal or trip

command according to the user’s requirement.

There are two stages included in overvoltage protection, each stage can be

set to alarm or trip separately in binary setting, and the time delay for each

stage can be individually set. Thus, the alarming or tripping can be

time-coordinated based on how severe the voltage increase, e.g. in case of

high overvoltage, the trip command will be issued with a short time delay,

whereas for the less severe overvoltage, trip or alarm signal can be issued

with a longer time delay.


151

Additionaly, the dropout ratio of the overvoltage protection can be set in set-

ting “Dropout_OV”. Therefore, the trip command of overvoltage is reset if the

measured voltage comes bellow the ratio value mentioned in this setting.

6.2 Phase to earth overvlotage protection

The phase to earth overvoltage protection operates just like the phase to

phase protection except that it detects phase to earth voltages.

7 Logic diagram

HV OV Chk PE on

HV OV Chk PE off

HV OV1 Trip on

HV OV1 Trip off

Ua>HV U_OV1

Ub>HV U_OV1 O

RUc>HV U_OV1

Uab>HV U_OV1

Ubc>HV U_OV1 O

RUca>HV U_OV1

O

RHV T_OV1

Trip

Alarm

Figure 52 Logic diagram for overvoltage protection


UA

UB

UC

Relay Startup

OV1 Trip

OV2 Trip

OV1 Alarm

OV2 Alarm

Overvoltage Protection

Figure 53 Oervoltage protection module


Signal Description


152

Signal Description





Signal Description

OV1 Trip OV stage 1trip

OV2 Trip OV stage 2trip

OV1 Alarm OV stage 1 alarm

OV2 Alarm OV stage 2 alarm


9 Setting

Table 96 Function setting list for overvoltage protection for HV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

HV U_OV1 V 40 200 200 HV voltage setting for stage 1

of overvoltage protection

HV T_OV1 s 0 60 60 HV time setting for stage 1 of

overvoltage protection

HV U_OV2 V 40 200 200 HV voltage setting for stage 2


HV T_OV2 s 0 60 60 HV time setting for stage 2 of


HV Dropout_OV 0.9 0.99 0.95 HV dropout ratio for overvolt-

age protection

Table 97 Binary setting list for overvoltage protection for HV side of transformer


setting Description

HV Func_OV1 0 1 0 HV overvoltage stage 1 enabled


153


setting Description

or disabled

HV Func_OV2 0 1 0

HV overvoltage stage 1 trip or

alarm

HV Func_OV2 0 1 0

HV overvoltage stage 2 enabled

or disabled

HV OV2 Trip 0 1 0

HV overvoltage stage 2 trip or

alarm

HV OV Chk PE

0 1 0

HV phase to phase voltage or

phase to earth measured for


Table 98 Function setting list for overvoltage protection for MV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

MV U_OV1 V 40 200 200 MV voltage setting for stage 1


MV T_OV1 s 0 60 60 MV time setting for stage 1 of


MV U_OV2 V 40 200 200 MV voltage setting for stage 2


MV T_OV2 s 0 60 60 MV time setting for stage 2 of


MV Dropout_OV 0.9 0.99 0.95 MV dropout ratio for overvolt-

age protection

Table 99 Binary setting list for overvoltage protection for MV side of transformer


setting Description

MV Func_OV1 0 1 0

MV overvoltage stage 1 enabled

or disabled

MV Func_OV2 0 1 0

MV overvoltage stage 1 trip or

alarm

MV Func_OV2 0 1 0

MV overvoltage stage 2 enabled

or disabled

MV OV2 Trip 0 1 0

MV overvoltage stage 2 trip or

alarm

MV OV Chk PE 0 1 0

MV phase to phase voltage or

phase to earth measured for


154


setting Description


10 Report



HV OV1 Trip HV overvoltage stage 1 trip


MV OV1 Trip MV overvoltage stage 1 trip




HV OV1 Alarm HV overvoltage stage 1 alarm

HV OV2 Alarm HV overvoltage stage 2 alarm

MV OV1 Alarm MV overvoltage stage 1 alarm

MV OV2 Alarm MV overvoltage stage 2 alarm


Description of event comment

HV Func_OV On HV overvoltage protection is switched ON (by CW)

HV Func_OV Off HV overvoltage protection is switched OFF (by CW)

MV Func_OV On MV overvoltage protection is switched ON (by CW)

MV Func_OV Off MV overvoltage protection is switched OFF (by CW)

11 Technical data

Table 103 Technical data for overvoltage protection


Voltage connection Phase-to-phase voltages or

phase-to-earth voltages

≤ ±3 % setting or ±1 V


155

Phase to earth voltage 40 to 100 V, step 1 V ≤ ±3 % setting or ±1 V

Phase to phase voltage 80 to 200 V, step 1 V ≤ ±3 % setting or ±1 V

Reset ratio 0.90 to 0.99, step 0.01 ≤ ±3 % setting

Time delay 0.00 to 60.00 s, step 0.01s ≤ ±1 % setting or +50 ms, at

120% energizing setting

Reset time <40ms


156

Chapter 12 Circuit breaker failure protection

157

Chapter 12 Circuit breaker failure

protection


signals, parameter, IED report and technical data for circuit

breaker failure protection function.


158

1 Introduction

The circuit breaker failure (CBF) protection function monitors proper tripping

of the relevant circuit breaker. There are two separate CBF protection inte-

grated in the IED. They are dedicated to HV and MV sides of the protected

transformer.


Normally, the circuit breaker should be tripped and therefore interrupt the fault

current whenever a short circuit protection function issues a trip command.

The circuit breaker failure protection provides rapid back-up fault clearance,

in the event of circuit breaker malfunction to respond to a trip command. This

feature can be enabled or disabled at each side of the protected transformer

via Binary settings “HV1 CBF ON”, “MV CBF ON”. If setting “1-On” is applied

at these Binary settings, respective CBF protection will be switched on. In this

case, by operation of a protection function, and subsequent CBF initiation by

respective protection function, a report nominated as “HV1 CBF INIT” or “MV

CBF INIT” is generated by the IED. Furthermore, CBF initiation causes a

programmed timer to run toward a preset time delay limit. This time delay is

set by user under the settings “HV1 T1_CBF” or “MV1 T1_CBF”. If the circuit

breaker has not been opened after expiration of the preset time limit, the cir-

cuit breaker failure protection issues a command to trip circuit breaker (e.g.

via a second trip coil). Furthermore, event report of “HV1 CBF T1” or “MV

CBF T1”is generated by the device. If the circuit breaker doesn’t respond to

the repeated trip command, until another preset delay time which is set at

“HV1 T2_CBF” or “MV1 T2_CBF”, the protection issues a trip command to

isolate the fault by tripping other surrounding backup circuit breakers (e.g. the

other CBs connected to the same bus section as the faulty CB). Furthermore,

event report of “HV1 CBF T2” or “MV CBF T2” is generated in this case.

Initiation of CBF protection can be carried out by both the internal and exter-

nal protection functions. If it is desired to initiate the CBF protection by means

of external protection functions, they should be marshaled to Binary input (BI)

of “HV1 CBF EXT. INT” or “MV CBF EXT. INT” for HV or MV CBF protection

respectively. Internal protection functions can initiate the CBF protection in-

tegrated in IED (HV and/or MV CBF), according to the mapping shown in

below table.


159

Table 104 Internal functions mapping to initiate CBF protection

PROTECTION FUNCTIONS CBF INITIATION

HV1 MV

Percent Differential Protection Trip [IDIFF>] ● ● ●

High-Set Differential Protection Trip [IDIFF>>] ● ● ●

HV Restricted Earth Fault Protection Trip ● ● ●

MV Restricted Earth Fault Protection Trip ● ● ●

LV Restricted Earth Fault Protection Trip ● - ●

Overexcitation Protection INV Trip ● ● ●

Overexcitation Protection DEF Trip [U/f >>] ● ● ●

HV Thermal Overload Protection Trip ● CW

[0/1] CW

[0/1]

MV Thermal Overload Protection Trip CW

[0/1] ● -

LV Thermal Overload Protection Trip CW

[0/1] - ●

HV Overcurrent Protection Trip [INV / DEF (Stage-1,2)] ● CW

[0/1] CW

[0/1]

MV Overcurrent Protection Trip [INV / DEF (Stage-1,2)]

CW [0/1]

● -

LV Overcurrent Protection Trip [INV / DEF (Stage-1,2)] CW

[0/1] - ●

HV Earth Fault Protection Trip [INV / DEF (Stage-1,2)] ● CW

[0/1] CW

[0/1]

MV Earth Fault Protection Trip [INV / DEF (Stage-1,2)] CW

[0/1] ● -

LV Earth Fault Protection Trip [INV / DEF (Stage-1,2)] CW

[0/1] - ●

HV Neutral Current Protection Trip [INV / DEF (Stage-1,2)]

● CW

[0/1] CW

[0/1]

MV Neutral Current Protection Trip [INV / DEF (Stage-1,2)]

CW [0/1]

● -

LV Neutral Current Protection Trip [INV / DEF (Stage-1,2)]

CW [0/1]

- ●

Overload Protection for LV Winding Low-Stage Trip (Inside Delta)

CW [0/1]

CW [0/1]

-


160

Over Load Protection for LV Winding High-Stage Trip (Inside Delta)

CW [0/1]

CW [0/1]

-

DI1 Trip CW

[0/1] CW

[0/1] CW

[0/1]

DI2 Trip CW

[0/1] CW

[0/1] CW

[0/1]

In above table,

● :means that the protection function working at a given side of the protected

transformer always initiate the CBF protection applied in specified side of the

power transformer. As can be seen, differential, restricted earth fault and

overexcitation protection functions initiate CBF protection in each side of

protected transformer with no additional settings.

The statement CW [0/1] means that the protection function can initiate CBF

protection according to the setting which is applied at respective Binary set-

ting. The setting includes “1: Initiate the CBF” and “0: Don’t initiate the CBF”.

Related Binary settings are available for specific functions which include

thermal overload, overcurrent, earth fault and neutral earth fault protections.

Furthermore, the dash sign means that it is not possible to initiate CBF pro-

tection of respective side by operation of a protection function working at a

given side of the protected transformer.

There are two criteria for breaker failure detection: the first one is to check

whether the actual current flow effectively disappeared after a tripping com-

mand had been issued. The second one is to evaluate the circuit breaker

auxiliary contact status. Since circuit breaker is supposed to be open when

current disappears from the circuit, the first criterion (current monitoring) is

the most reliable means for relay to be informed about proper operation of

circuit breaker. Therefore, current monitoring is applied to detect circuit

breaker failure condition. In this context, the monitored current of each phase

is compared with the pre-defined setting. The settings are applied at “HV1

I_CBF OC” or “MV I_CBF OC”, for HV or MV CBF protection.

Furthermore, it is possible to implement current checking in case of ze-

ro-sequence and negative-sequence currents via Binary setting “HV1 3I0/3I2

Check On”, “MV1 3I0/3I2 Check On”. If setting “1-On” is applied at these Bi-

nary settings, zero-sequence and negative-sequence currents are calculated

and compared with user-defined settings. Corresponding

settings include “HV 3I0_CBF ZS” and “MV 3I0_CBF ZS” for zero-sequence

current, and “HV 3I2_CBF NS” and “MV 3I2_CBF NS” for negative-sequence

current.


161

For protection functions where the tripping criterion is not dependent on cur-

rent, current flow is not a suitable criterion for proper operation of the breaker.

In this case, the position of the circuit breaker auxiliary contact should be

used to determine if the circuit breaker properly operated. It is possible to

evaluate the circuit breaker operation from its auxiliary contact status. To do

so, Binary settings “HV1 CB Status Check On” or “MV CB Status Check On”

should be set to “1-On” to integrate circuit breaker auxiliary contacts into CBF

function..

It should be noted that evaluation of circuit breaker auxiliary contacts is car-

ried out in CBF function only when the current flow monitoring has not picked

up. Once the current flow criterion has picked up during the running time of

CBF timers, the circuit breaker is assumed to be open as soon as the current

disappears, even if the associated auxiliary contacts don’t indicate that the

circuit breaker has opened. This gives preference to the more reliable current

criterion and avoids over functioning due to a defect e.g. in the auxiliary con-

tact mechanism or circuit.

3 Logic diagram

O

R

BI_HV1 CB EXT.INT

Inter 3Ph Init CBFInit HV CBF

Figure 54 Internal and external initiation


162

HV 3I0/3I2 Check Off

HV 3I0/3I2 Check On


HV 3I0/3I2 Check On


HV 3I0/3I2 Check On

Ia > HV1 I_CBF OC

3I0 > HV1 3I0_CBF ZS

3I2 > HV1 3I2_CBF NS

Ib >HV1 I_CBF OC

Ic > HV1 I_CBF OC

O

R

Ib >HV1 I_CBF OC



Ic > HV1 I_CBF OC

Ia >HV1 I_CBF OC

O

R

A

N

D

A

N

D

Ic >HV1 I_CBF OC



Ib > HV1 I_CBF OC

Ia > HV1 I_CBF OC

O

R

A

N

D

O

R

O

R

O

R

O

R Curr. Crit.

Figure 55 Circuit breaker auxiliary contact evaluation

Init HV CBF

CBF Curr. Crit. 3P

A

N

D

A

N

DO

R

CB is closed

BI_HV1 CB Open A

BI_HV1 CB Open B

BI_HV1 CB Open C

A

N

D

Figure 56 The logic for CB close


163

T1_CBF

T2_CBF

CB Status Check On

CB is closed

Curr. crit.

Init HV CBF

O

RA

N

D

Func_CBF on

CBF stg1

CBF stg2

Figure 57 The logic for CBF protection


IA

IB

IC

CB Pole A Open

CB Pole B Open

CB Pole C Open

EXT. INT CBF

CBF Stage 1 Trip

CBF Stage 2 Trip

Relay Startup

Circuit Breaker

Failure Proteciton

Figure 58 Circuit breaker protection module


Signal Description

IA Phase A current input

IB Phase B current input

IC Phase C current input

Table 106 Binary intput list

Signal Description

CB Pole A Open Circuit breaker(CB) pole A is open


164

Signal Description

CB Pole B Open Circuit breaker(CB) pole A is open

CB Pole COpen Circuit breaker(CB) pole A is open

EXT.INT CBF initiate the CBF protection by external protection


Signal Description

CBF Stage1 Trip CBF protection stage 1 trip

CBF Stage2 Trip CBF protection stage 1 trip


5 Setting

Table 108 Settings of CBF protection for HV side of transformer

Setting Unit Min.

(Ir:5A/1A)

Max.

(Ir:5A/1A)

Default

setting

(Ir:5A/1A)

Description

HV I_CBF

OC A 0.05Ir 20Ir 5

Phase current setting value for

HVcircuit breaker failure (CBF)

protection

HV

3I2_CBF

NS

A 0.05Ir 20Ir 5

Negative sequence (NS) cur-

rent setting 23I value for HV

CBF protection

HV

3I0_CBF

ZS

A 0.05Ir 20Ir 5

Zero sequence (ZS) current

setting 03I value for HV1

CBF protection

HV T1_CBF s 0 32 10 Time setting value of Stage 1,

for HV CBF protection

HV T2_CBF s 0.1 32 10 Time setting value of Stage 2,



165

Table 109 Binary settings of CBF protection for HV side of transformer


De-

fault

setting

Description

HV Func_CBF 0 1 0

HV Circuit breaker failure (CBF)


1-on; 0-off.

HV 3I0/3I2 Check

On 0 1 0

HV CBF protection detect nega-

tive or zero sequence current

3I0 or 3I2.

1-Detect; 0- Not Detect

HV CB Status

Check On 0 1 0

HV CBF protection detect HV1

CB status


Table 110 Settings of CBF protection for MV side of transformer

Setting Unit Min.

(Ir:5A/1A)

Max.

(Ir:5A/1A)

Default

setting

(Ir:5A/1A)

Description

MVI_CBF

OC A 0.05Ir 20Ir 5


MV CBF protection

MV

3I2_CBF

NS

A 0.05Ir 20Ir 5


rent setting 23I value for MV

CBF protection

MV

3I0_CBF

ZS

A 0.05Ir 20Ir 5


setting 03I value for MV CBF

protection

MV T1_CBF s 0 32 10 Time setting value of Stage 1,

for MV CBF protection

MV T2_CBF s 0.1 32 10 Time setting value of Stage 2,


Table 111 Binary settings of CBF protection for MV side of transformer


De-

fault

setting

Description


166

MV Func_CBF 0 1 0

MV Circuit breaker failure (CBF)


1-on; 0-off.

MV 3I0/3I2 Check

On 0 1 0

MV CBF protection detect nega-


3I0 or 3I2.


MV CB Status

Check On 0 1 0

MV CBF protection detect MV

CB status


Table 112 Settings of CBF protection for LV side of transformer

Setting Unit Min.

(Ir:5A/1A)

Max.

(Ir:5A/1A)

Default

setting

(Ir:5A/1A)

Description

LV I_CBF

OC A 0.05Ir 20Ir 5


LV CBF protection

LV 3I2_CBF

NS A 0.05Ir 20Ir 5


rent setting 23I value for LV

CBF protection

LV 3I0_CBF

ZS A 0.05Ir 20Ir 5


setting 03I value for LV CBF

protection

LV T1_CBF s 0 32 10 Time setting value of Stage 1,

for LV CBF protection

LV T2_CBF s 0.1 32 10 Time setting value of Stage 2,


Table 113 Binary settings of CBF protection for LV side of transformer


De-

fault

setting

Description

LV Func_CBF 0 1 0

LV Circuit breaker failure (CBF)


1-on; 0-off.

LV 3I0/3I2 Check

On 0 1 0

LV CBF protection detect nega-


3I0 or 3I2.


167


LV CB Status

Check On 0 1 0

LV CBF protection detect LV CB

status


6 Report



HV CBF1 Trip HV circuit breaker failure protection stage 1 trip


HV CBF Init Internal or external initiate HV circuit breaker failure protection

MV CBF1 Trip MV circuit breaker failure protection stage 1 trip


MV CBF Init Internal or external initiate MV circuit breaker failure protection

LV CBF1 Trip LV circuit breaker failure protection stage 1 trip


LV CBF Init Internal or external initiate LV circuit breaker failure protection


Description of event comment

HV Func_CBF On HV circuit breaker failure protection is switched ON (by CW)

HV Func_CBF Off HV circuit breaker failure protection is switched OFF (by CW)

MV Func_CBF On MV circuit breaker failure protection is switched ON (by CW)

MV Func_CBF Off MV circuit breaker failure protection is switched OFF (by CW)

LV Func_CBF On LV circuit breaker failure protection is switched ON (by CW)

LV Func_CBF Off LV circuit breaker failure protection is switched OFF (by CW)

7 Technical data


phase current

Negative sequence current

zero sequence current

0.08 Ir to 20.00 Ir ≤ ±3% setting or ±0.02Ir

Time delay of stage 1 0.00s to 32.00 s, step 0.01s ≤ ±1% setting or +25 ms, at


168

Time delay of stage 2 0.00s to 32.00 s, step 0.01s 200% energizing setting

Reset ratio >0.95

Reset time < 25ms

Chapter 13 Dead zone protection

169


About this chapter

This chapter describes the protection principle, input and output

signals, parameter, IED report and technical data used for dead

zone (short zone) protection function.


170

1 Introduction

The IED provides this protection function to protect dead zone, namely the

area between circuit breaker and CT in the case that CB is open. Therefore,

by occurrence of a fault in dead zone, the short circuit current is measured by

protection relay while CB auxiliary contacts indicate the CB is open.

Internal/ external initiation

Self-adaptive for bus side CT or line side CT

When one bus side CT of feeder is applied, once a fault occurs in the dead

zone, the IED trips the relevant busbar zone. Tripping logic is illustrated in

below figure.


In the case of feeders with bus side CTs, once a fault occurs in the dead zone,

the IED trips the relevant busbar zone CBs. Tripping concept is illustrated in

the below figure.

Bus2

IFAULT

Trip

T1

L1Ln

Bus1

Bus3

Opened CB

Closed CB

Legend:

Bus2

IFAULT

trip

T1

L1Ln

Bus1

Bus3

Opened CB

Closed CB

Legend:


171

Figure 59 Tripping logic for applying bus side CT and for applying line side CT

2.1 Function description

Internal/external initiation

Self-adaptive for bus side CT or line side CT. For bus side CTs, the dead

zone protection will select to trip breakers on other lines connected to the

same busbar. For line side CTs, the dead zone protection will select trip op-

posite side breakers on the same line.

3 Logic diagram

Func_Dead Zone On

CBF.Curr. Crit.

Init HV CBF

A

N

D

T_Dead Zone Dead Zone Trip

BI_HV PhA CB Open

A

N

D

BI_HV 3Ph CB Close

BI_HV PhB CB Open

BI_HV PhC CB Open

A

N

D

Func_HV CBF

On

Figure 60 Dead zone protection logic


172


DZ Trip

Relay Startup

CB Pole A Open

CB Pole B Open

CB Pole C Open

CB 3 Poles Close

IA

IB

IC

Dear Zone

Protection

Figure 61 Dead zone protection module


Signal Description




Table 117 Binary input list

Signal Description


CB Pole B Open Circuit breaker(CB) pole B is open

CB Pole C Open Circuit breaker(CB) pole C is open

CB 3 Poles Close 3 poles of circuit breaker(CB) is close


Signal Description

DZ Trip dead zone protection trip



173

5 Setting

Table 119 Dead zone protection function setting list for HV side of transformer

Setting Unit

Min.

(Ir:5A/1A

)

Max.

(Ir:5A/1A

)

Default

setting

(Ir:5A/1A

)

Description

HV T_Dead Zone

s 0 32 10

Time delay setting for HV

dead zone protection

Table 120 Dead zone protection binary setting list for HV side of transformer

Setting Uni

t

Min

.

Max

.

Default set-

ting Description

HV Func_Dead

Zone 0 1 0

Dead zone protection is switched

ON

1-on; 0-off.

Table 121 Dead zone protection function setting list for MV side of transformer

Setting Unit

Min.

(Ir:5A/1A

)

Max.

(Ir:5A/1A

)

Default

setting

(Ir:5A/1A

)

Description

MV T_Dead Zone

s 0 32 10

Time delay setting for MV


Table 122 Dead zone protection binary setting list for MV side of transformer

Setting Uni

t

Min

.

Max

.

Default set-

ting Description

MV Func_Dead

Zone 0 1 0

Dead zone protection is switched

ON

1-on; 0-off.

Table 123 Dead zone protection function setting list for LV side of transformer

Setting Unit

Min.

(Ir:5A/1A

)

Max.

(Ir:5A/1A

)

Default

setting

(Ir:5A/1A

)

Description

LV T_Dead Zone s 0 32 10 Time delay setting for LV


174


Table 124 Dead zone protection binary setting list for LV side of transformer

Setting Uni

t

Min

.

Max

.

Default set-

ting Description

LV Func_Dead

Zone 0 1 0

Dead zone protection is switched ON

1-on; 0-off.

6 Report



HV Dead Zone HV Dead zone trip

MV Dead Zone MV Dead zone trip

LV Dead Zone LV Dead zone trip



HV Func_DZ On HV DZ function on

HV Func_DZ Off HV DZ function off

MV Func_DZ On MV DZ function on

MV Func_DZ Off MV DZ function off

LV Func_DZ On LV DZ function on

LV Func_DZ Off LV DZ function off

7 Technical data

NOTE: Ir: CT rated secondary current, 1A or 5A;



Time delay 0.00s to 32.00s, step 0.01s ≤ ±1% setting or +40 ms, at


Reset ratio >0.95

Chapter 14 STUB protection

175


About this chapter


signals, parameter, IED report and technical data used for STUB



176

1 Introduction

The STUB protection protects the zone between the CTs and the open

disconnector. The STUB protection is enabled when the open position of the

disconnector is informed to the IED through connected binary input. The

function supports one definite stage with the logic shown inbelow figure.



Fault

CB1

CB3

CB2

CT1-2

CT3-2

CT2-1

Feeder 1 Disconnector

Feeder 2 Disconnector

Feeder1

Feeder2

Busbar A

Busbar B

CT3-1

CT2-2

CT1-1

Figure 62 STUB fault at circuit breaker arrangement

If IED detects short circuit current flowing while the line disconnector is open,

STUB fault is detected for the short circuit in the area between the current

transformers and the line disconnector. Here, the summation of CT1 and CT3

presents the short circuit current.


177

The STUB protection is an overcurrent protection which is only in service if

the status of the line disconnector indicates the open condition. The binary

input must therefore be informed via an auxiliary contact of the disconnector.

In the case of a closed line disconnector, the STUB protection is out of ser-

vice. The STUB protection stage provides one definite time overcurrent stage

with settable delay time. This protection function can be enabled or disabled

via the binary setting “Func_STUB”. Corresponding current setting value can

be inserted in “I_STUB” setting. The IED generate trip command whenever

the time setting “T_STUB” is elapsed.

3 Logic diagram

Func_STUB

Ia>I_STUB

T_STUB

Output Disconnector Open

A

N

D

Permanent trip

Ib>I_STUB

Ic>I_STUB

O

R

Figure 63 Logic diagram for STUB protection


IA1

IB1

IC1

IA2

IB2

IC2

STUB Trip

Relay Startup

STUB Protection

Figure 64 STUB protection module


178


Signal Description








Signal Description

Output disconnector open Transformer output feeder disconnector is

open, to enable the STUB protection


Signal Description

STUB Trip STUB Trip


5 Setting

Table 130 Setting value list for STUB protection for HV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

HV I_STUB A 0.05Ir 20Ir 100 current threshold of STUB protec-

tion

HV T_STUB s 0 60 60 delay time of STUB protection


179

Table 131 Binary setting list for STUB protection for HV side of transformer


setting Description

HV Func_STUB 0 1 0

Enable or disable STUB

protection

HV STUB Init LV

CBF 0 1 0

STUB protection initiate

LV side CBF


HV STUB Init MV

CBF 0 1 0


HV side CBF


Table 132 Setting value list for STUB protection for MV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

MV I_STUB A 0.05Ir 20Ir 100 current threshold of STUB protec-

tion

MV T_STUB s 0 60 60 delay time of STUB protection

Table 133 Binary setting list for STUB protection for MV side of transformer


setting Description

MV Func_STUB 0 1 0


protection

MV STUB Init LV

CBF 0 1 0


LV side CBF


MV STUB Init MV

CBF 0 1 0


MV side CBF


Table 134 Setting value list for STUB protection for LV side of transformer

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

LV I_STUB A 0.05Ir 20Ir 100 current threshold of STUB protec-


180

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

tion

LV T_STUB s 0 60 60 delay time of STUB protection

Table 135 Binary setting list for STUB protection for LV side of transformer


setting Description

LV Func_STUB 0 1 0


protection

LV STUB Init LV

CBF 0 1 0


LV side CBF


LV STUB Init MV

CBF 0 1 0


LV side CBF


6 Report



HV STUB Trip HV STUB protection trip

MV STUB Trip MV STUB protection trip

LV STUB Trip LV STUB protection trip



HV Func_STUB On HV STUB function on

HV Func_STUB Off HV STUB function Off

MV Func_STUB On MV STUB function on

MV Func_STUB Off MV STUB function Off

LV Func_STUB On LV STUB function on

LV Func_STUB Off LV STUB function Off


181

7 Technical data


Table 138 Technical data for STUB protection





Reset ratio >0.95


182

Chapter 15 Poles discordance protection

183

Chapter 15 Poles discordance

protection

About this chapter


signals, parameter, IED report and technical data for poles dis-

cordance protection.


184

1 Introdcution

Under normal operating condition, all three poles of the circuit breaker must be closed or open at the same time. The phase separated operating circuit breakers can be in different positions (close-open) due to electrical or me-chanical failures. This can cause negative and zero sequence currents which gives thermal stress on rotating machines and can cause unwanted operation of zero sequence or negative sequence current functions.

Single pole opening of the circuit breaker is permitted only in the short period related to single pole dead times, otherwise the breaker is tripped three pole to resolve the problem. If the problem still remains, the remote end can be intertripped via circuit breaker failure protection function to clear the unsym-metrical load situation.

The pole discordance function operates based on information from auxiliary contacts of the circuit breaker for the three phases with additional criteria from unsymmetrical phase current.



The CB position signals are connected to IED via binary input in order to monitor the CB status. Poles discordance condition is established when bi-nary setting “HV Func_PD” for HV said, or “MV Func_PD” for MV said is set to “1/on”, and at least one pole is open and at the same time not all three poles are closed. The auxiliary contacts of the circuit breakers are checked with corresponding phase currents for plausibility check. Error alarm “CB Err Blk PD” is reported after 5 sec whenever CB auxiliary contacts indicate that one pole is open but at the same time current is flowing through the pole.

Additionally the function can be informed via binary setting “HV PD Chk 3I0/3I2” and “MV PD Chk 3I0/3I2”for additionaly zero and negative sequence current as well as current criteria involved in CBF protection. Pole discord-ance can be detected when current is not flowing through all three poles. When current is flowing through all three poles, all three poles must be closed even if the breaker auxiliary contacts indicate a different status.


185

3 Logic diagram

5s

Func_PD On

PD Chk 3I0/3I2 on

BI_CB Open A A

N

DIa > 0.06Ir

BI_CB Open B A

N

DIb > 0.06Ir

BI_CB Open C A

N

DIc > 0.06Ir

BI_CB Open A

A

N

D

BI_CB Open B

BI_CB Open C

BI_CB Open A A

N

DIa < 0.06Ir

BI_CB Open B A

N

DIb < 0.06Ir

BI_CB Open C A

N

DIc< 0.06Ir

O

R

3I2 > 3I2_PD

3I0 >3I0_PDA

N

DCBF Curr. Crit. A

A

N

D

CBF Curr. Crit. B

CBF Curr. Crit. C

PD Chk 3I0/3I2 off

O

R

O

R

A

N

D

CB Err Blk PD

A

N

D

PD Trip

T_PD

Figure 65 Logic diagram for poles discordance protection


186


INBK

IA

IB

IC

CB Pole A Open

CB Pole B Open

CB Pole C Open

PD Trip

Relay Startup

Pole Discordance

Protection

Figure 66 Poles discordance protection module


Signal Description




INBK Neutral current input


Signal Description


CB Pole B Open Circuit breaker(CB) pole B is open

CB Pole C Open Circuit breaker(CB) pole C is open


Signal Description

PD Trip PD Trip



187

5 Setting

Table 142 Function setting list for poles discordance protection for HV side of tranformer


De-fault set-ting

Description

HV 3I0_PD A 0.05Ir 20Ir 5 zero sequence current threshold of pole discordance protection

HV 3I2_PD A 0.05Ir 20Ir 5 negative sequence current thresh-old of pole discordance protection

HV T_PD s 0 60 10 delay time of pole discordance protection

Table 143 Binary setting list for poles discordance protection for HV side of tranformer

Setting Unit Min. Max. Default setting

Description

MV Func_PD 0 1 0 Enable or disable MV poles discordance protection

MV PD Chk 3I0/3I2

0 1 0 Enable or disable 3I0/3I2 criteria

Table 144 Function setting list for poles discordance protection for MV side of tranformer


De-fault set-ting

Description

MV 3I0_PD A 0.05Ir 20Ir 5 zero sequence current threshold of pole discordance protection

MV 3I2_PD A 0.05Ir 20Ir 5 negative sequence current thresh-old of pole discordance protection

MV T_PD s 0 60 10 delay time of pole discordance protection

Table 145 Binary setting list for poles discordance protection for MV side of tranformer

Setting Unit Min. Max. Default setting

Description

MV Func_PD 0 1 0 Enable or disable MV poles discordance protection

MV PD Chk 3I0/3I2

0 1 0 Enable or disable 3I0/3I2 criteria


188

6 Report



HV PD Trip HV poles discordance protection trip

MV PD Trip MV poles discordance protection trip



CB Err Blk PD Circuit breaker error block poles discordance protection



HV Func_PD On HV poles discordance function on

HV Func_PD Off HV poles discordance function off

MV Func_PD On MV poles discordance function on

MV Func_PD Off MV poles discordance function off

7 Technical data


Table 149 Technical data for pole discordance





Reset ratio >0.95

Chapter 16 Secondary system supervision

189


About this chapter This chapter describes the protection principle, input and output signals, parameter, IED report and technical data for secondary system supervision function.


190

1 VT failure supervision function

In the event of a measured voltage failure due to a broken conductor or a short circuit fault in the secondary circuit of voltage transformer, those protec-tion functions which work based on voltage criteria may mistakenly see a voltage of zero. VT failure supervision function is provided to inform those functions about a voltage failure.

2 Function principle

VT failure supervision function can be enabled or disabled in each side through Binary setting “HV VT Fail Detect”, “MV VT Fail Detect” and “LV VT Fail Detect”. By applying setting “1-On” to these Binary settings, respective VT failure supervision function would monitor the voltage transformer circuit of corresponding side. Each VT failure supervision function is able to detect single-phase broken, two-phase broken or three-phase broken faults in re-spective voltage transformer. There are three main criteria for VT failure de-tection; from them the first one is dedicated to detect three-phase broken faults. The second and third one is dedicated to detect single or two-phase broken faults in solid earthed and isolated/resistance earthed systems, re-spectively. A precondition to meet these three criteria is that the relay should not be picked up and the calculated zero sequence and negative sequence currents should be less than setting of “HV I_VT Fail”, “MV I_VT Fail” or “LV I_VT Fail”. These criteria are as follows:

The calculated zero sequence voltage 3U0 as well as maximum of three phase-to-earth voltages of respective side of the protected transformer are less than the setting of “HV Upe_VT Fail”, “MV Upe_VT Fail” or “LV Upe_VT Fail” and at the same time, maximum of three phase currents of respective side is higher than setting of “HV I_VT Fail”, “MV I_VT Fail” or “LV I_VT Fail”. This condition may correspond to three phase broken fault in secondary cir-cuit of the voltage transformer in respective side of the protected transformer.

The calculated zero sequence voltage 3U0 of respective side of the protected transformer is more than the setting of “HV Upe_VT Fail”, “MV Upe_VT Fail” or “LV Upe_VT Fail”. This condition may correspond to single or two-phase broken fault in secondary circuit of the voltage transformer in respective side of the protected transformer, if the system starpoint is solidly earthed.

The calculated zero sequence voltage 3U0 of respective side of the protected transformer is more than the setting of “HV Upe_VT Fail”, “MV Upe_VT Fail” or “LV Upe_VT Fail”, and at the same time, the difference between the max-imum and minimum phase-to-phase voltages of respective side is more than the setting of “HV Upp_VT Fail”, “MV Upp_VT Fail” or “LV Upp_VT Fail”. This condition may correspond to single or two-phase broken fault in secondary circuit of the voltage transformer in respective side of the protected trans-former, if the system starpoint is isolated or resistance earthed.

In addition to the mentioned conditions, the device has the capability to be


191

informed about the VT MCB failure through its binary inputs. These inputs in-clude “HV MCB FAIL BI”, “MV MCB FAIL BI” and “LV MCB FAIL BI”. In this context, VT fail is detected in corresponding side, if the respective binary in-puts are active.

If VT failure supervision detects a failure in voltage transformer secondary circuit, either by means of the above mentioned criteria or reception of a VT MCB fail indication, all the protection functions which operate based on di-rection determination would be blocked in corresponding side of the protected transformer, depending on the setting. Furthermore, an alarm report of “HV VT Fail”, “MV VT Fail” or “LV VT Fail”, is issued after 10s delay time. The blocking condition would be removed if one of the following conditions is met within the 10s delay time.

Minimum phase voltage of corresponding side of the protected transformer becomes more than setting of “HV Upe_VT Normal”, “MV Upe_VT Normal” or “LV Upe_VT Normal” for 500ms.

Minimum phase voltage of corresponding side becomes more than setting of “HV Upe_VT Normal”, “MV Upe_VT Normal” or “LV Upe_VT Normal” and at the same time, the calculated zero sequence and negative sequence current of corresponding side becomes more than the setting of “HV 3I02_VT Fail”, “MV 3I02_VT Fail” or “LV 3I02_VT Fail”.

Subsequent to reporting VT fail alarm, the blocking condition of respective protection functions would be removed if the minimum phase voltage of cor-responding side becomes more than the setting of “HV Upe_VT Normal”, “MV Upe_VT Normal” or “LV Upe_VT Normal” for a duration more than 10s.

Below figure shows logic diagram of VT failure supervision as it is imple-mented in the IED.


192

Max(Ia,Ib,Ic)>I_ VT Fail

Max{Ua,Ub,Uc}<Upe_VT Fail

3U0 < （ Upe_VT Fail-1（

Max{Uab,Ubc,Uca}-

Min{Uab,Ubc,Uca}>

Upp_VT Fail

3U0 >= （ Upe_VT Fail-1)

Min{Ua,Ub,Uc}>Upe_VT Normal

3I0>3I02_VT Fail or

3I2>3I02_VT Fail

min{Ua,Ub,Uc}>Upe_VT Normal

A

N

D

A

N

D

O

R

A

N

D

A

N

D

O

R

A

N

D

A

N

D

A

N

D

500ms

A

N

D

A

N

D

10s

O

RNo VT Fail

VT Fail

Detected10s Alarm report

Solid Earth on

Solid Earth off

A

N

D

Relay Pickup

BI MCB Fail

HV VT Fail Detect on

VT Fail Detected

Figure 67 Logic of VT Failure supervision


193


IA1

IB1

IC1

IA2

IB2

IC2

UA

UB

UC

VT Failure

Relay Startup

V3P MCB Fail

VT Secondary

Circuit Supervision

Figure 68 VT Failure supervision module


Signal Description











Signal Description

V3P MCB Fail VT failure informed by BI


194


Signal Description

VT Failure VT Failure


4 Setting

Table 153 Settings of VT failure supervision for HV side of transformer

Setting Title Unit Min. Max. Default setting

Comment

HV I_VT Fail A 0.05Ir 0.2Ir 0.05 Minimum Current of VT failure for HV side

HV 3I02_ VT Fail A 0.05Ir 0.2Ir 0.5 Minimum zero or negative Cur-rent of HV VT fail

HV Upe_VT Fail V 7 20 8 Maximum phase to earth voltage of HV VT fail

HV Upp_VT Fail V 10 30 16 Maximum phase to phase volt-age of HV VT fail

HV Upe_VT Normal V 40 65 40

Minimum phase to phase volt-age of HV VT normal

Table 154 Binary settings of VT failure supervision for HV side of transformer

Setting Title Unit De-fault

Min. Max. Comment

HV VT FAIL Detect 0 0 1 HV VT Failure Detection On/Off 1-On, 0-Off.

HV Solid Earth 0 0 1

HV Earthing mode: 1: Solid earthed system ; 0: isolated system or re-sistance earthed.

Table 155 Settings of VT failure supervision for MV side of transformer


Comment

MV I_VT Fail A 0.05Ir 0.2Ir 0.05 Minimum Current of VT failure for MV side

MV 3I02_VT Fail A 0.05Ir 0.2Ir 0.5 Minimum zero or negative Cur-rent of MV VT fail

MV Upe_VT Fail V 7 20 8 Maximum phase to earth voltage of MV VT fail

MV Upp_VT Fail V 10 30 16 Maximum phase to phase volt-age of MV VT fail

MV Upe_VT Normal

V 40 65 40 Minimum phase to phase volt-age of MV VT normal


195

Table 156 Binary settings of VT failure supervision for MV side of transformer


Min. Max. Comment

MV VT FAIL Detect 0 0 1 MV VT Failure Detection On/Off 1-On, 0-Off.

MV Solid Earth 0 0 1

MV Earthing mode: 1: Solid earthed system ; 0: isolated system or re-sistance earthed.

Table 157 Settings of VT failure supervision for LV side of transformer


Comment

LV I_VT Fail A 0.05Ir 0.2Ir 0.05 Minimum Current of VT failure for LV side

LV 3I02_VT Fail A 0.05Ir 0.2Ir 0.5 Minimum zero or negative Cur-rent of LV VT fail

LV Upe_VT Fail V 7 20 8 Maximum phase to earth voltage of LV VT fail

LV Upp_VT Fail V 10 30 16 Maximum phase to phase volt-age of LV VT fail

LV Upe_VT Normal

V 40 65 40 Minimum phase to phase volt-age of LV VT normal

Table 158 Binary settings of VT failure supervision for LV side of transformer


Min. Max. Comment

LV VT FAIL Detect 0 0 1 LV VT Failure Detection On/Off 1-On, 0-Off.

LV Solid Earth 0 0 1

LV Earthing mode: 1: Solid earthed system ; 0: isolated system or re-sistance earthed.

5 Report



HV VT Fail HV VT Fail alarm

MV VT Fail MV VT Fail alarm

LV VT Fail LV VT Fail alarm



HV Func_VT On HV VT failure supervision function on

HV Func_VT Off HV VT failure supervision function off

MV Func_VT On MV VT failure supervision function on


196


MV Func_VT Off MV VT failure supervision function off

LV Func_VT On LV VT failure supervision function on

LV Func_VT Off LV VT failure supervision function off

6 Technical data

Item Range or value Tolerances

Minimum current 0.08Ir to 0.20Ir, step 0.01A ≤ ±3% setting or ±0.02Ir

Minimum zero or negative se-

quence current

0.08Ir to 0.20Ir, step 0.01A ≤ ±5% setting or ±0.02Ir

Maximum phase to earth voltage 7.0V to 20.0V, step 0.01V ≤ ±3% setting or ±1 V

Maximum phase to phase volt-

age

10.0V to 30.0V, step 0.01V ≤ ±3% setting or ±1 V

Normal phase to earth voltage 40.0V to 65.0V, step 0.01V ≤ ±3% setting or ±1 V

Chapter 17 External Bis to trip BOs

197

Chapter 17 External BIs to trip BOs

About this chapter This chapter describes the protection principle, input and output signals, parameter, IED report and technical data for external BIs to trip BOs function.


198

1 Introduction

Two special binary inputs (BI_Config1, BI_Config2) are provided which can be used to activate respective binary outputs (BO1 and BO2), according to the setting applied at Binary settings “BI1 Enable BO1” and “BI2 Enable BO2”. By applying setting “1-enable” to these Binary settings, BO1 will be activated if BI1 is energized. Similarly, BO2 will be activated if BI2 is energized. Fur-thermore, 7th LED in front plate of the device would be lighted when BO1 or BO2 is activated.

2 Function principle

The external BIs can be used in conjunction with the mechanical protections of the protected transformer (such as Buchholz, Winding temperature, and so on). In this context, trip commands of the main and backup mechanical pro-tections can be marshaled to BI1 and BI2, respectively. By doing so, the output trip commands would be provided at BO1 and BO2 respectively.

Since the trip command of mechanical protection has latched nature, two operating modes are provided for the Bos activation. The operating modes include direct and pulse tripping modes. In direct tripping mode, each BO contact is active as long as respective BI is energized, and after BI disap-pearance 20ms the BO contacts are deactivated. Whereas in pulse tripping mode, by each up-edge of BI, respective BO contacts remain active during a settable pulse time, and after the settable time, the BO contacts are inactive. The tripping modes can be selected for the BOs by Binary settings “BO1 Pulse Tripping” and “BO2 Pulse Tripping”. Pulse tripping mode would be possible if setting “1-Pulse Tripping” is applied to the Binary settings. Similarly, setting “0-Direct Tripping” activates direct tripping mode for respective BOs. The logic is shown in below figure.

Pulse Tripping Time

0

1

1

0

0

1

BI Enable BO on

BO Pulse Tripping

A

N

D

A

N

D

A

N

D

A

N

D

BIx up edge

BI trip BO

BI trip BO


199

Figure 69 Logic of external BIs to trip BOs

Furthermore, it is possible to set BIs to initiate CBF protection in HV, MV or LV sides of protected transformer via a number of Binary settings. The Binary settings include “BI1 Init HV CBF”, “BI1 Init MV CBF” and “BI1 Init LV CBF” on for the first BI. Similarly, Binary settings “BI2 Init HV CBF”, “BI2 Init MV CBF” and “BI2 Init LV CBF” correspond to the second BI.

3 BI Trigger Record

In the IED, it is possible for Binary inputs (BIs) to trigger disturbance record (DR). The exceptions are “Switch SetGroup”, “Blk Rem Access”, “Relay Test” and “Reset”. In this context, each Binary input can be set independently whether it can trigger DR or not. Further, it is possible to set whether BI trig-gers DR in its up or down edge. Example logic of BI “HV CB Open Status” triggering DR is given in below figure. The same logic is applied for the other BIs.

Equipment parameter

“HV1 CB OPEN STATUS DOWN” = 1

BI “HV1 CB Open A”

Change from “1”to “0” A

N

D

BI “HV1 CB OPEN STATUS ENABLE”

=1

BI “HV1 CB Open Status”

Change from “0”to “1”

Equipment parameter

“HV1 CB OPEN STATUS DOWN” = 0

(meaning UP edge)

A

N

D

O

R

Trigger

Record

Figure 70 Logic of BI trigger record


200

4 BI Switch SetGroup

BI “Switch SetGroup” is used to switch setting group of the device. Both “BI

SetGrp Switch”and “Normal Set Switch” are selected by making change in the

content of special Binary setting “BI SetGrp Switch” which can be set under

“Common Para” submenu. When the Binary setting is set to 1, BI setting

group switch mode is applied, on the contrary, Normal setting group switch

mode (shortcut key or operate through the menu) is applied. For “BI SetGrp

Switch” mode, When BI “Switch SetGroup” is deactivated, the content of Bi-

nary setting “BI SetGrp Switch” is set to 0 and it means that no switching in

setting groups is desired. In this case, Group 1 is applied to the device. When

the BI is activated, the content of Binary setting “BI SetGrp Switch” is set to 1

and it means that “BI SetGrp Switch” mode is applied. Thus, the current set-

ting-value would automatically be switched to Group 2. For the other switch

mode, whether the BI is activated or not, setting group change is valid for

shortcut key or operate through the menu.

5 BI “Blk Rem Access” and “RELAY TEST”

There are two methods to block remote access to the device, BI “Blk Rem

Access” or making change in the content of special Binary setting “NOT Blk

Remote Access” which can be set under “Common Para” submenu.

When BI “Blk Rem Access” is activated, or the content of Binary setting “NOT

Blk Remote Access” is set to 0, SCADA remote access is blocked to the de-

vice and therefore, only local operation is permitted.

When BI “Blk Rem Access” is deactivated, and the content of Binary setting

“NOT Blk Remote Access” is set to 1, both SCADA commands and local op-

eration can be executed by the device.

Similarly, there are two methods to select test or normal operating mode of

the device, BI “Relay Test” or making change in the content of special Binary

setting “Relay Test Mode” which can be set under “Common Para” submenu.

When BI “Relay Test” is activated, or the content of Binary setting “Relay Test

Mode” is set to 1, the relay is in test mode.

When BI “Relay Test” is deactivated, and the content of Binary setting “Relay

Test Mode” is set to 0, the relay is in normal operation mode


201

6 BI “BI_Config1~ BI_Config2” and “BI TRIGGER DR1~ 10”

Both “BI_Config1~ BI_Config2” and “BI Trigger DR1~ BI Trigger DR10” are

binary inputs which can be recorded. BI_Config1~ BI_Config2 can operate to

binary output X10 and X11. The names of these BIs can be modified by

CSPC tools according to actual situation.

7 Setting

Table 161 Setting of external BIs to trip BOs

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

T_Pulse

Tripping s 0.2 5 5 delay time of STUB protection

Table 162 Binary settings of external DIs to trip DOs

Setting Title Setting

options

Default

setting Comment

BI1 Enable

BO1 1/0 0

To select whether the 1st binary input (BI1) trip

the 1st binary output (BO1) or not.

1-enable, 0-disable

BO1 Pulse

Tripping 1/0 0

To select BO1 tripping in pulse mode or in direct

mode

0- BO1 Direct Tripping, without delay

1- BO1 Pulse Tripping, with preset delay time

BI2 Enable

BO2 1/0 0

To select whether the 2nd

binary input (BI2) trip

the 2nd

binary output (BO2) or not.

1-enable, 0-disable

BO2 Pulse

Tripping 1/0 0

To select BO2 tripping in pulse mode or in direct

mode

0- BO2 Direct Tripping, without delay

1- BO2 Pulse Tripping, with preset delay time

BI1 Init HV

CBF 1/0 0

whether BI1 initiate HV side CBF or not


BI1 Init MV

CBF 1/0 0 whether BI1 initiate MV side CBF or not


202

Setting Title Setting

options

Default

setting Comment


BI1 Init LV

CBF 1/0 0

whether BI1 initiate LV side CBF or not


BI2 Init HV

CBF 1/0 0

whether BI2 initiate HV side CBF or not


BI2 Init MV

CBF 1/0 0

whether BI2 initiate MV side CBF or not


BI2 Init LV

CBF 1/0 0

whether BI2 initiate LV side CBF or not


Chapter 18 Station communication

203


About this chapter

This chapter describes the communication possibilities in a

SA-system.


204

1 Overview

Each IED is provided with a communication interface, enabling it to connect to

one or many substation level systems or equipment.

The following communication protocols are available:

LON communication protocol

IEC 61850-8-1 communication protocol

60870-5-103 communication protocol

The IED is able to connect to one or more substation level systems or

equipments simultaneously, through the communication ports and supported

protocols.

1.1 Protocol

1.1.1 LON communication protocol

The LON protocol is specified in the LonTalkProtocol Specification Version 3

from Echelon Corporation. This protocol is designed for communication in

control networks and is a peer-to-peer protocol where all the devices con-

nected to the network can communicate with each other directly.

1.1.2 IEC61850-8 communication protocol

IEC 61850-8-1 allows two or more intelligent electronic devices (IEDs) from

one or several vendors to exchange information and to use it in the perfor-

mance of their functions and for correct co-operation.

GOOSE (Generic Object Oriented Substation Event), which is a part of IEC

61850-8-1 standard, allows the IEDs to communicate state and control in-

formation amongst themselves, using a publish-subscribe mechanism. That

is, upon detecting an event, the IED(s) use a multi-cast transmission to notify

those devices that have registered to receive the data. An IED can, by pub-

lishing a GOOSE message, report its status. It can also request a control ac-

tion to be directed at any device in the network.


205

1.1.3 IEC60870-5-103 communication protocol

The IEC 60870-5-103 communication protocol is mainly used when a protec-

tion IED communicates with a third party control or monitoring system. This

system must have software that can interpret the IEC 60870-5-103 commu-

nication messages.

The IEC 60870-5-103 is an unbalanced (master-slave) protocol for coded-bit

serial communication exchanging information with a control system. In IEC

terminology a primary station is a master and a secondary station is a slave.

The communication is based on a point-to-point principle. The master must

have software that can interpret the IEC 60870-5-103 communication mes-

sages. For detailed information about IEC 60870-5-103, refer to the

“IEC60870 standard” part 5: “Transmission protocols”, and to the section 103:

“Companion standard for the informative interface of protection equipment”.

1.2 Communication port

1.2.1 Front communication port

There is a serial RS232 port on the front plate of all IEDs. Through this port,

the IED can be connected to the personal computer for setting, testing, and

configuration using the dedicated Sifang software tool.

1.2.2 RS485 communication ports

Up to 2 isolated electrical RS485 communication ports are provided to con-

nect with substation automation system. These two ports can work in parallel

for IEC60870-5-103.

1.2.3 Ethernet communication ports

Up to 3 electrical or optical Ethernet communication ports are provided to

connect with substation automation system. These two out of three ports can

work in parallel for protocol, IEC61850 or IEC60870-5-103.

1.3 Technical data


206

Front communication port

Item Data

Number 1

Connection Isolated, RS232; front panel

9-pin subminiature connector, for CSmart

Communication speed 9600 baud

Max. length of communication cable 15 m

RS485 communication port

Item Data

Number 0~2

Connection 2-wire connector

Rear port in communication module

Max. length of communication cable 1.0 km


Communication speed Factory setting 9600 baud

Min. 1200 baud, Max. 19200 baud

Ethernet communication port

Item Data

Electrical communication port

Number 0 ~ 3

Connection RJ45 connector


Max. length of communication cable 100m

IEC 61850 protocol

Communication speed 100 Mbit/s



Optical communication port ( optional )

Number 0 ~ 3

Connection SC connector



207

Item Data

Optical cable type Multi-mode

Max. length of communication cable 2.0km

IEC 61850 protocol




Time synchronization

Item Data

Mode Pulse mode

IRIG-B signal format IRIG-B000



Voltage levels differential input


208

2 Typicalcommunication scheme

2.1 Typical substation communication scheme

Gateway

or

converter

Work Station 3

Server or

Work Station 1

Server or

Work Station 2

Work Station 4

Net 2: IEC61850/IEC103,Ethernet Port B

Net 3: IEC103, RS485 Port A

Net 4: IEC103, RS485 Port B

Net 1: IEC61850/IEC103,Ethernet Port A

Gateway

or

converter

SwitchSwitch Switch

Switch

Switch

Switch

Figure 71 Connection example for multi-networks of station automation system

2.2 Typical time synchronizing scheme

All IEDs feature a permanently integrated electrical time synchronization port.

It can be used to feed timing telegrams in IRIG-B or pulse format into the

IEDs via time synchronization receivers. The IED can adapt the second or

minute pulse in the pulse mode automatically.

Meanwhile, SNTP network time synchronization can be applied.

Below figure illustrates the optional time synchronization modes.


209

SNTP IRIG-B Pulse

Ethernet port IRIG-B port Binary input

Figure 72 Time synchronizing modes


210

Chapter 19 Hardware

211

Chapter 19 Hardware

About this chapter

This chapter describes the IED hardware.

Chapter 19 Hardware

212

3 Introduction

3.1 IED structure

The enclosure for equipment is 19 inches in width and 4U in height according

to IEC 60297-3.

The equipment is flush mounting with panel cutout and cabinet.

Connection terminals to other system on the rear.

The front panel of equipment is aluminium alloy by founding in integer

and overturn downwards. LCD, LED and setting keys are mounted on the

panel. There is a serial interface on the panel suitable for connecting to PC.

Draw-out modules for serviceability are fixed by lock component.

The modules can be combined through the bus on the rear board. Both

the equipment and the other system can be combined through the rear in-

terfaces.

3.2 IED appearance

Figure 73 Protection IED front view

Chapter 19 Hardware

213

3.3 IED module arrangement

X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13

AIM AIM AIM AIM COM BIM BOM1 BOM2 BOM3 BOM4 PSM

An

alo

gu

e In

pu

t mod

ule

An

alo

gu

e In

pu

t mod

ule

An

alo

gu

e In

pu

t mod

ule

Spa

re s

lot

Co

mm

unic

atio

n m

od-

ule

Bin

ary

inpu

t mod

ule

Spa

re s

lot

Bin

ary

outp

ut m

odu

le 1

Bin

ary

outp

ut m

odu

le 2

Bin

ary

outp

ut m

odu

le 3

Bin

ary

outp

ut m

odu

le 4

Spa

re s

lot

Po

we

r su

pp

ly m

odu

le

Figure 74 Module arrangement （front view, when open the front panel）

3.4 The rear view of the protection IED

Test port

X5

COM

X6X8X9X12 X1

AIM

X13

PSM

X2

AIM

X7 X3

AIM

X11 X10

For BIM and BOM Ethernet ports

Figure 75 Rear view of the protection IED

Chapter 19 Hardware

214

4 Local human-machine interface

Setting operation and interrogation of numerical protection systems can be

carried out via the integrated membrane keyboard and display panel located

on the front plate. All the necessary operating parameters can be entered and

all the information can be read out from here,e.g. display, main menu, de-

bugging menu. Operation is, additionally, possible via interface socket by

means of a personal computer or similar.

4.1 Human machine interface

Front panel adopts little arc streamline and beelines sculpt, and function keys

for MMI are reasonably distributed in faceplate. Panel layout are shown as

below figures.

Chapter 19 Hardware

215

2

1

3

45

68

7

CSC-326

Figure 76 Front panel layout for 8 LEDs

2

1

3

45

68

7

CSC-326

Figure 77 Front panel layout for 20 LEDs

4.2 LCD

The member of keyboard and display panel is externally arranged similar to a

pocked calculator.

4.3 Keypad

The keypad is used to monitor and operate the IED. The keypad has the

Chapter 19 Hardware

216

same look and feel in all IEDs in the CSC series. LCD screens and other

details may differ but the way the keys function is identical. The keys used to

operate the IED are described below.

Table 163 function of keys of the keypad

Key function

SET

SET key:

Enters main menu or sub-menu, and confirms the setting changes

QUIT

QUIT key:

Navigates backward the upper menu.

Cancels current operation and navigates backward the upper

menu.

Returns normal rolling display mode

Locks and unlocks current display in the normal scrolling display

mode; (the locked display mode is indicated by a key type icon

on the upright corner of LCD.)

Right arrow key:

Moves right in menu.

Left arrow key:

Moves left in menu.

Up arrow key:

Moves up in menu

Page up between screens

Increases value of setting.

Down arrow key

Moves down in menu

Page down between screens

Decreases the value of setting.

RESET

RESET key:

Reset LEDs

Return to normal scrolling display mode directly

4.4 Shortcut keys and functional keys

The shortcut keys and functional keys are below the LCD on the front panel. These

keys are designated to execute the frequent menu operations for user’s convenience.

The keys used to operate the IED are described below.

Table 164 function of Shortcut keys and functional keys

Key function

Chapter 19 Hardware

217

F1 Reserved

F2 Reserved

F3 Reserved

F4 Reserved

+ Plus key:

Switch next setting group forward as active setting group， meaning

the number of setting group plus one.

_ Minus key

Switch next setting group backward as active setting group , mean-

ing the number of setting group subtracted one.

4.5 LED

The definitions of the LEDs are fixed and descrbed below.

Table 165 Definition of 8 LEDs

No LED Color Description

1 Run Green Steady lighting: Operation normally

Flashing: IED startup

8 Alarm Red

Steady lighting: Alarm II, meaning abnormal situation,

only the faulty function is out of service. Power supply

for tripping output is not blocked.

Flashing: Alarm I, meaning severe internal fault, all

protections are out of service. And power supply for

tripping outputs is blocked as well.

The definitions of the LEDs are fixed and described below for 20 LEDs.

Table 166 Definition of 20 LEDs


1 Run Green Steady lighting: Operation normally

Flashing: IED startup

11 Alarm Red Steady lighting: Alarm II, meaning abnormal situation,

only the faulty function is out of service. Power supply

Chapter 19 Hardware

218


for tripping output is not blocked.

Flashing: Alarm I, meaning severe internal fault, all

protections are out of service. And power supply for

tripping outputs is blocked as well.

The other LEDs which are not described above can be configured.

4.6 Front communication port

There is a serial RS232 port on the front plate of all the IEDs. Through this

port, the IED can be connected to the personal computer for setting, testing,

and configuration using the dedicated Sifang software tool.

Chapter 19 Hardware

219

5 Analog input module

5.1 Introduction

The analogue input module is used to galvanically separate and transform the

secondary currents and voltages generated by the measuring transformers.

There are two types of current transformer: Rated current 5A with linearity

range 50mA～150A and rated current 1A with linearity range 100mA～30A

(please indicate clearly when order the product).

5.2 Terminals of Analogue Input Module (AIM)

b01 a01

b02 a02

b03 a03

a04b04

a05b05

a06b06

a07b07

a08b08

a09b09

a10b10

a11b11

ab

a12b12

Figure 78 Terminals arrangement of AIM E

Table 167 Description of terminals of AIM E

Terminal Analogue Remark

Chapter 19 Hardware

220

Input

a01 IA Star point

b01 I’A

a02 IB Star point

b02 I’B

a03 IC Star point

b03 I’C

a04 I’N

b04 IN Star point

a05 I’NM

b05 INM Star point

a06 Null

b06 Null Star point

a07 Null

b07 Null Star point

a08 Null

b08 Null Star point

a09 Null

b09 Null

a10 U4 Star point

b10 U’4

a11 UB Star point

b11 UC Star point

a12 UA Star point

b12 UN

5.3 Technical data

5.3.1 Internal current transformer

Item Standard Data

Rated current Ir IEC 60255-1 1 or 5 A

Nominal current range 0.05 Ir to 30 Ir

Nominal current range of sensitive 0.005 to 1 A

Chapter 19 Hardware

221

CT

Power consumption (per phase) ≤ 0.1 VA at Ir = 1 A;

≤ 0.5 VA at Ir = 5 A

≤ 0.5 VA for sensitive CT

Thermal overload capability IEC 60255-1

IEC 60255-27

100 Ir for 1 s

4 Ir continuous

Thermal overload capability for

sensitive CT

IEC 60255-27

DL/T 478-2001

100 A for 1 s

3 A continuous

5.3.2 Internal voltage transformer

Item Standard Data

Rated voltage Vr (ph-ph) IEC 60255-1 100 V /110 V

Nominal range (ph-e) 0.4 V to 120 V

Power consumption at Vr = 110 V IEC 60255-27

DL/T 478-2001

≤ 0.1 VA per phase

Thermal overload capability

(phase-neutral voltage)

IEC 60255-27

DL/T 478-2001

2 Vr, for 10s

1.5 Vr, continuous

Chapter 19 Hardware

222

6 Communication module

6.1 Introduction

The communication module performs communication between the internal

protection system and external equipments such as HMI, engineering work-

station, substation automation system, RTU, etc., to transmit remote metering,

remote signaling, SOE, event reports and record data.

Up to 3 channels isolated electrical or optical Ethernet ports and up to 2

channels RS485 serial communication ports can be provided in communica-

tion module to meet the communication demands of different substation au-

tomation system and RTU at the same time.

The time synchronization port is equipped, which can work in pulse mode or

IRIG-B mode. SNTP mode can be applied through communication port.

In addition, a series printer port is also reserved.

6.2 Substaion communication port


There is a serial RS232 port on the front plate of all the IEDs. Through this

port, the IED can be connected to the personal computer for setting, testing,

and configuration using the dedicated Sifang software tool.


Up to 2 isolated electrical RS485 communication ports are provided to con-

nect with substation automation system. These two ports can work in parallel

for IEC60870-5-103.

6.2.3 Ethernet communication ports

Up to 3 electrical or optical Ethernet communication ports are provided to

connect with substation automation system. Two out of these three ports can

Chapter 19 Hardware

223

work in parallel for protocol, IEC61850 or IEC60870-5-103.

6.2.4 Time synchronization port

All IEDs feature a permanently integrated electrical time synchronization port.

It can be used to feed timing telegrams in IRIG-B or pulse format into the

IEDs via time synchronization receivers. The IED can adapt the second or

minute pulse in the pulse mode automatically.

Meanwhile, SNTP network time synchronization can also be applied.

6.3 Terminals of Communication Module

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

Ethernet port B

Ethernet port A

Ethernet port C

Figure 79 Terminals arrangement of COM

Table 168 Definition of terminals of COM

Terminal Definition

01 Null

02 Null

03 Null

04 Null

Chapter 19 Hardware

224

05 Optional RS485 port - 2B

06 Optional RS485 port - 2A

07 Optional RS485 port - 1B

08 Optional RS485 port - 1A

09 Time synchronization

10 Time synchronization GND

11 Null

12 Null

13 Null

14 Null

15 Null

16 Null

Ethernet

Port A

Optional optical fiber or RJ45

port for station automation sys-

tem

Ethernet

Port B



tem

Ethernet

Port C



tem

6.4 Operating reports


DI Comm Fail DI communication error

DO Comm Fail DO communication error

6.5 Technical data

6.5.1 Front communication port

Item Data

Number 1

Connection Isolated, RS232; front panel,

9-pin subminiature connector, for software tools

Chapter 19 Hardware

225

Communication speed 9600 baud

Max. length of communication cable 15 m

6.5.2 RS485 communication port

Item Data

Number 0 to 2



Max. length of communication cable 1.0 km

Test voltage 500 V AC against earth

For IEC 60870-5-103 protocol

Communication speed Factory setting 9600 baud,

Min. 1200 baud, Max. 19200 baud

6.5.3 Ethernet communication port

Item Data

Electrical communication port

Number 0 to 3

Connection RJ45 connector


Max. length of communication cable 100m

For IEC 61850 protocol


For IEC 60870-5-103 protocol


Optical communication port ( optional )

Number 0 to 2

Connection SC connector


Optical cable type Multi-mode

Max. length of communication cable 2.0km

IEC 61850 protocol




Chapter 19 Hardware

226

6.5.4 Time synchronization

Item Data

Mode Pulse mode

IRIG-B signal format IRIG-B000



Voltage levels differential input

Chapter 19 Hardware

227

7 Binary input module

7.1 Introduction

The binary input module is used to connect the input signals and alarm sig-

nals such as the auxiliary contacts of the circuit breaker (CB), etc.

The negative terminal of power supply for BI module, 220V or 110V, should

be connected to the terminal.

7.2 Terminals of Binary Input Module (BIM)

c02 a02

c04 a04

c06 a06

a08c08

a10c10

a12c12

a14c14

a16c16

a18c18

a20c20

a22c22

a24c24

a26c26

a28c28

a30c30

a32c32

ac

DC -DC -

Figure 80: Terminals arrangement of BIM A

Chapter 19 Hardware

228

Table 169 Definition of terminals of BIM A

Terminal Definition Remark

a02 BI1 BI group 1

c02 BI2 BI group 2

a04 BI3 BI group 1

c04 BI4 BI group 2

a06 BI5 BI group 1

c06 BI6 BI group 2

a08 BI7 BI group 1

c08 BI8 BI group 2

a10 BI9 BI group 1

c10 BI10 BI group 2

a12 BI11 BI group 1

c12 BI12 BI group 2

a14 BI13 BI group 1

c14 BI14 BI group 2

a16 BI15 BI group 1

c16 BI16 BI group 2

a18 BI17 BI group 1

c18 BI18 BI group 2

a20 BI19 BI group 1

c20 BI20 BI group 2

a22 BI21 BI group 1

c22 BI22 BI group 2

a24 BI23 BI group 1

c24 BI24 BI group 2

a26 BI25 BI group 1

c26 BI26 BI group 2

a28 BI27 BI group 1

c28 BI28 BI group 2

a30 BI29 BI group 1

c30 BI30 BI group 2

a32 DC - Input Common terminal of BI group 1

c32 DC - Input Common terminal of BI group 2

Chapter 19 Hardware

229

7.3 Technical data

Item Standard Data

Input voltage range IEC60255-1 110/125 V DC

220/250 V DC

Threshold1: guarantee oper-

ation

IEC60255-1 154V, for 220/250V DC

77V, for 110V/125V DC

Threshold2: uncertain opera-

tion

IEC60255-1 132V, for 220/250V DC;

66V, for 110V/125V DC

Response time/reset time IEC60255-1 Software provides de-bounce

time

Power consumption, ener-

gized

IEC60255-1 Max. 0.2 W/input, 24V DC

Max. 0.5 W/input, 110V DC

Max. 1 W/input, 220V DC

Chapter 19 Hardware

230

8 Binary output module

8.1 Introduction

The binary output modules mainly provide tripping output contacts, initiating

output contacts and signaling output contacts. All the tripping output relays

have contacts with a high switching capacity and are blocked by protection

startup elements.

Each output relay can be configured to satisfy the demands of users.

8.2 Terminals of Binary Output Module (BOM)

8.2.1 Binary Output Module A

The module provides 16 output relays for tripping or initiating, with total 16 contacts.

Chapter 19 Hardware

231

a02

R

1

a04

a06

a08

a10

a12

a14

a16

a18

a20

a22

a24

a26

a28

a30

a32

ac

c02

c04

c06

c08

c10

c12

c14

c16

c18

c20

c22

c24

c26

c28

c30

c32

R

3

R

5

R

7

R

9

R

11

R

13

R

15

R

16

R

2

R

4

R

6

R

8

R

10

R

12

R

14

Figure 81 Terminals arrangement of BOM A

Chapter 19 Hardware

232

Table 170 Definition of terminals of BOM A

Terminal Definition Related relay

a02 Trip contact 1-0 Output relay 1

c02 Trip contact 1-1 Output relay 1































Chapter 19 Hardware

233

8.2.2 Binary Output Module C

The module provides 16 output relays for signal, with total 19 contacts.

a02

a04

a06

a08

a10

a12

a14

a16

a18

a20

a22

a24

a26

a28

a30

a32

ac

c02

c04

c06

c08

c10

c12

c14

c16

c18

c20

c22

c24

c26

c28

c30

c32

R

4

R

5

R

1

R

2

R

3

R

6

R

7

R

16

R

9

R

10

R

11

R

12

R

13

R

14

R

15

R

8

Figure 82 Terminals arrangement of BOM C

Table 171 Definition of terminals of BOM C

Terminal Definition Related relay

a02 Signal 1-0, Common terminal of signal contact group 1

c02 Signal 2-0, Common terminal of signal contact group 2

Chapter 19 Hardware

234

a04 Signal contact 1-1 Output relay 1

c04 Signal contact 2-1 Output relay 1





a10 Signal 3-0, Common terminal of signal contact group 3

c10 Signal 4-0, Common terminal of signal contact group 4























8.3 Technical data

Item Standard Data

Chapter 19 Hardware

235

Item Standard Data

Max. system voltage IEC60255-1 250V DC/AC

Current carrying capacity IEC60255-1 5 A continuous,

42A，1s ON, 9s OFF

Making capacity IEC60255-1 1100 W(DC) at inductive load

with L/R>40 ms

1000 VA(AC)

Breaking capacity IEC60255-1 ≥1000 cycles ，

DC220V, 0.15A， t=L/R≤40 ms

DC110V, 0.30A， t=L/R≤40 ms

Unloaded mechanical endur-

ance

IEC60255-1 50,000,000 cycles (3 Hz

switching frequency)

Specification state verification IEC60255-1

IEC60255-23

IEC61810-1

UL/CSA、TŰV

Contact circuit resistance

measurement

IEC60255-1

IEC60255-23

IEC61810-1

30mΩ

Open Contact insulation test

(AC Dielectric strength)

IEC60255-1

IEC60255-27

AC1000V 1min

Maximum temperature of parts

and materials

IEC60255-1 55℃

Chapter 19 Hardware

236

9 Power supply module

9.1 Introduction

The power supply module is used to provide the correct internal voltages and

full isolation between the terminal and the battery system. Its power input is

DC 220V or 110V (according to the order code), and its outputs are five

groups of power supply.

(1) ＋24V two groups provided: Power for inputs of the corresponding bi-

nary inputs of the CPU module

(2) ±12V: Power for A/D

(3) + 5V: Power for all micro-chips

9.2 Terminals of Power Supply Module (PSM)

c02 a02

c04 a04

c06 a06

a08c08

a10c10

a12c12

a14c14

a16c16

a18c18

a20c20

a22c22

a24c24

a26c26

a28c28

a30c30

a32c32

ac

DC 24V +

OUTPUTS

DC 24V -

OUTPUTS

AUX.DC +

INPUT

AUX. DC -

INPUT

Chapter 19 Hardware

237

Figure 83 Terminals arrangement of PSM

Table 172 Definition of terminals of PSM

Terminal Definition

a02 AUX.DC 24V+ output 1

c02 AUX.DC 24V+ output 2

a04 AUX.DC 24V+ output 3

c04 AUX.DC 24V+ output 4

a06 Isolated terminal, not wired

c06 Isolated terminal, not wired

a08 AUX.DC 24V- output 1

c08 AUX.DC 24V- output 2





a14 Alarm contact A1, for AUX.DC power input failure

c14 Alarm contact A0, for AUX.DC power input failure

a16 Alarm contact B1, for AUX.DC power input failure

c16 Alarm contact B0, for AUX.DC power input failure



a20 AUX. power input 1, DC +

c20 AUX. power input 2, DC +

a22 AUX. power input 3, DC +

c22 AUX. power input 4, DC +



a26 AUX. power input 1, DC -

c26 AUX. power input 2, DC -

a28 AUX. power input 3, DC -

c28 AUX. power input 4, DC -



a32 Terminal for earthing

Chapter 19 Hardware

238

c32 Terminal for earthing

9.3 Technical data

Item Data

Rated auxiliary voltage Vaux 110~250V DC

Permissible tolerance ±%20 Uaux

Power consumption

Normal operation ≤ 30 W

Tripping condition ≤ 50 W

Chapter 19 Hardware

239

10 Techinical data

10.1 Basic data

10.1.1 Frequency

Item Data

System rated frequency 50 Hz or 60Hz

10.1.2 Internal current transformer

Item Data

Rated current Ir 1 or 5 A

Nominal current range (0.05 – 20)x Ir

Power consumption (per phase) ≤ 0.1 VA at Ir = 1 A;

≤ 0.5 VA at Ir = 5 A

Thermal overload capability 100 x Ir for 1 s

4 x Ir continuous

10.1.3 Internal voltage transformer

Item Data

Rated voltage Vr (ph-ph) 100-120

Nominal range (ph-e) 0.4 V to 120 V

Power consumption at Vr = 110 V ≤ 0.1 VA per phase

Thermal overload capability (phase-neutral

voltage)

2Vr, for 10s

1.5Vr, continuous

10.1.4 Auxiliary voltage

Item Standard Data

Rated auxiliary voltage Vaux IEC60255-1 110 to 250V DC

Permissible tolerance IEC60255-1 ±%20 Uaux

Chapter 19 Hardware

240

Item Standard Data

Power consumption at quies-

cent state

IEC60255-1 ≤ 50 W

Power consumption at maxi-

mum load

IEC60255-1 ≤ 60 W

Inrush Current IEC60255-1 T ≤ 10 ms/I≤ 25 A

10.1.5 Binary inputs

Item Standard Data

Input voltage range IEC60255-1 110/125 V DC

220/250 V DC

Threshold1: guarantee oper-

ation

IEC60255-1 154V, for 220/250V DC

77V, for 110V/125V DC

Threshold2: uncertain opera-

tion

IEC60255-1 132V, for 220/250V DC;

66V, for 110V/125V DC

Response time/reset time IEC60255-1 Software provides de-bounce

time

Power consumption, ener-

gized

IEC60255-1 Max. 0.2 W/input, 24V DC

Max. 0.5 W/input, 110V DC

Max. 1 W/input, 220V DC

10.1.6 Binary outputs

Item Standard Data

Max. system voltage IEC60255-1 250V DC/AC

Current carrying capacity IEC60255-1 5 A continuous,

42A，1s ON, 9s OFF

Making capacity IEC60255-1 1100 W(DC) at inductive load

with L/R>40 ms

1000 VA(AC)

Breaking capacity IEC60255-1 ≥1000 cycles ，

DC220V, 0.15A， t=L/R≤40 ms

DC110V, 0.30A， t=L/R≤40 ms

Unloaded mechanical endur-

ance

IEC60255-1 50,000,000 cycles (3 Hz

switching frequency)

Specification state verification IEC60255-1

IEC60255-23

UL/CSA、TŰV

Chapter 19 Hardware

241

Item Standard Data

IEC61810-1

Contact circuit resistance

measurement

IEC60255-1

IEC60255-23

IEC61810-1

30mΩ

Open Contact insulation test

(AC Dielectric strength)

IEC60255-1

IEC60255-27

AC1000V 1min

Maximum temperature of parts

and materials

IEC60255-1 55℃

10.2 Type tests

10.2.1 Product safety-related Tests

Item Standard Data

Over voltage category IEC60255-27 Category III

Pollution degree IEC60255-27 Degree 2

Insulation IEC60255-27 Basic insulation

Degree of protection (IP) IEC60255-27

IEC 60529

Front plate: IP40

Rear, side, top and bottom: IP

30

Power frequency high voltage

withstand test

IEC 60255-5

ANSI C37.90

GB/T 15145-2001

DL/T 478-2001

2KV, 50Hz

2.8kV DC

between the following circuits:

auxiliary power supply

CT / VT inputs

binary inputs

binary outputs

case earth

500V, 50Hz

between the following circuits:

Communication ports to

case earth

time synchronization ter-

minals to case earth

Impulse voltage test IEC60255-5

IEC 60255-27

5kV (1.2/50μs, 0.5J)

if Ui≥63V

Chapter 19 Hardware

242

Item Standard Data

ANSI C37.90

GB/T 15145-2001

DL/T 478-2001

1kV if Ui<63V

Tested between the following

circuits:


CT / VT inputs

binary inputs

binary outputs

case earth

Note: Ui: Rated voltage

Insulation resistance IEC60255-5

IEC 60255-27

ANSI C37.90

GB/T 15145-2001

DL/T 478-2001

≥ 100 MΩ at 500 VDC

Protective bonding resistance IEC60255-27 ≤ 0.1Ω

Fire withstand/flammability IEC60255-27 Class V2

10.2.2 Electromagnetic immunity tests

Item Standard Data

1 MHz burst immunity test IEC60255-22-1

IEC60255-26

IEC61000-4-18

ANSI/IEEE C37.90.1

class III

2.5 kV CM ; 1 kV DM

Tested on the following circuits:


CT / VT inputs

binary inputs

binary outputs

1 kV CM ; 0 kV DM


communication ports

Electrostatic discharge IEC 60255-22-2

IEC 61000-4-2

Level 4

8 kV contact discharge;

15 kV air gap discharge;

both polarities; 150 pF; Ri = 330

Ω

Radiated electromagnetic field

disturbance test

IEC 60255-22-3 frequency sweep:

80 MHz – 1 GHz; 1.4 GHz – 2.7 GHz

spot frequencies:

Chapter 19 Hardware

243

Item Standard Data

80 MHz; 160 MHz; 380 MHz;

450 MHz; 900 MHz; 1850 MHz;

2150 MHz

10 V/m

AM, 80%, 1 kHz

Radiated electromagnetic field

disturbance test

IEC 60255-22-3 pulse-modulated

10 V/m, 900 MHz; repetition rate

200 Hz, on duration 50 %

Electric fast transient/burst im-

munity test

IEC 60255-22-4,

IEC 61000-4-4

ANSI/IEEE C37.90.1

class A, 4KV



CT / VT inputs

binary inputs

binary outputs

class A, 2KV


communication ports

Surge immunity test IEC 60255-22-5

IEC 61000-4-5

4.0kV L-E

2.0kV L-L



CT / VT inputs

binary inputs

binary outputs

2.0kV L-E


communication ports

Conduct immunity test IEC 60255-22-6

IEC 61000-4-6

frequency sweep: 150 kHz – 80

MHz

spot frequencies: 27 MHz and

68 MHz

10 V

AM, 80%, 1 kHz

Power frequency immunity test IEC60255-22-7 Class A

300 V CM

150 V DM

Power frequency magnetic field

test

IEC 61000-4-8 level 4

30 A/m cont. / 300 A/m 1 s to 3 s

100 kHz burst immunity test IEC61000-4-18 2.5 kV CM ; 1 kV DM

Chapter 19 Hardware

244

Item Standard Data



CT / VT inputs

binary inputs

binary outputs

1 kV CM ; 0 kV DM


communication ports

10.2.3 DC voltage interruption test

Item Standard Data

DC voltage dips IEC 60255-11 100% reduction 80 ms

60% reduction 200 ms

30% reduction 500 ms

DC voltage interruptions IEC 60255-11 100% reduction 5 s

DC voltage ripple IEC 60255-11 15%, twice rated frequency

DC voltage gradual shut–down

/start-up

IEC 60255-11 60 s shut down ramp

5 min power off

60 s start-up ramp

DC voltage reverse polarity IEC 60255-11 1 min

10.2.4 Electromagnetic emission test

Item Standard Data

Radiated emission IEC60255-25

CISPR22

30MHz to 1GHz ( IT device may

up to 5 GHz)

Conducted emission IEC60255-25

CISPR22

0.15MHz to 30MHz

10.2.5 Mechanical tests

Item Standard Data

Sinusoidal Vibration response

test

IEC60255-21-1 class 1

10 Hz to 60 Hz: 0.075 mm

60 Hz to 150 Hz: 1 g

Chapter 19 Hardware

245

Item Standard Data

1 sweep cycle in each axis

Relay energized

Sinusoidal Vibration endur-

ance test

IEC60255-21-1 class 1

10 Hz to 150 Hz: 1 g

20 sweep cycle in each axis

Relay non-energized

Shock response test IEC60255-21-2 class 1

5 g, 11 ms duration

3 shocks in both directions of 3

axes

Relay energized

Shock withstand test IEC60255-21-2 class 1

15 g, 11 ms duration

3 shocks in both directions of 3

axes

Relay non-energized

Bump test IEC60255-21-2 class 1

10 g, 16 ms duration

1000 shocks in both directions of

3 axes

Relay non-energized

Seismic test IEC60255-21-3 class 1

X-axis 1 Hz to 8/9 Hz: 7.5 mm

X-axis 8/9 Hz to 35 Hz :2 g

Y-axis 1 Hz to 8/9 Hz: 3.75 mm

Y-axis 8/9 Hz to 35 Hz :1 g

1 sweep cycle in each axis,

Relay energized

10.2.6 Climatic tests

Item Standard Data

Cold test - Operation IEC60255-27

IEC60068-2-1

-10°C, 16 hours, rated load

Cold test – Storage IEC60255-27

IEC60068-2-1

-25°C, 16 hours

Dry heat test – Operation [IEC60255-27

IEC60068-2-2

+55°C, 16 hours, rated load

Chapter 19 Hardware

246

Item Standard Data

Dry heat test – Storage IEC60255-27

IEC60068-2-2

+70°C, 16 hours

Change of temperature IEC60255-27

IEC60068-2-14

Test Nb, figure 2, 5 cycles

-10°C / +55°C

Damp heat static test IEC60255-27

IEC60068-2-78

+40°C, 93% r.h. 10 days, rated

load

Damp heat cyclic test IEC60255-27

IEC60068-2-30

+55°C, 93% r.h. 6 cycles, rated

load

10.2.7 CE Certificate

Item Data

EMC Directive EN 61000-6-2 and EN61000-6-4 (EMC

Council Directive 2004/108/EC)

Low voltage directive EN 60255-27 (Low-voltage directive 2006/95

EC).

10.3 IED design

Item Data

Case size 4U×19inch

Weight ≤ 8kg

Chapter 20 Appendix

247

Chapter 20 Appendix

Chapter 20 Appendix

248

1 General setting list

1.1 Function setting list

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

HV Wind Conn/Y

0 1 0 Connection for HV winding,


connection

MV Wind Conn/Y

0 1 0 Connection for MV winding,


connection

LV Wind Conn/Y

0 1 1 Connection for LV winding,


connection

Vet Grp Angle MVA 1.000 3000. 120.0 Vector Group Angle( VET

GRP ANGLE)

SN kV 1.000 1000. 220.0 Capacity of the transformer

HV VT Ratio MVA 1.000 9999. 2200.0 Voltage transformer(VT) Ra-

tio in HV side

HV CT Pri A 50.00 9999. 1200.0 CT Primary(PRI) current in

HV side

HV CT Sec A 1.000 5.000 1.0 CT Secondary(SEC) current

in HV side

HV Voltage Chan

Sel

1 3 1 HV voltage channel location

MV Voltage Chan

Sel

1 3 2 MV voltage channel loca-

tion

HV NCT Pri(REF)



for REF

HV NCT Sec(REF)


ary(SEC) current in HV side

for REF

HV NCT Pri(BU) A 50.00 9999. 1200.0 Neutral CT (NCT) Prima-

Chapter 20 Appendix

249

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description



HV NCT Sec(BU)


ary(PRI) current in HV side


MV UN kV 1.000 1000. 110.0 Nominal voltage (UN) in

Middle voltage (MV)side

MV VT Ratio 1.000 9999. 1100.0 Voltage transformer(VT) Ra-

tio in MV side

MV CT Pri A 50.00 9999. 1200.0 CT Primary(PRI) current in

MV side

MV CT Sec A 1.000 5.000 1.0 CT Secondary(SEC) current

in MV side

MV NCT Pri(REF)



for REF

MV NCT Sec(REF)


ary(SEC) current in MV

side for REF

MV NCT Pri(BU)




MV NCT Sec(BU)


ary(PRI) current in MV side


LV UN kV 1.000 1000. 10.50 Nominal voltage (UN) in Low

voltage (LV)side

LV VT Ratio 1.000 9999. 105.0 Voltage transformer(VT) Ra-

tio in LV side

LV CT Pri A 50.00 9999. 3000.0 CT Primary(PRI) current in

LV side

LV CT Sec A 1.000 5.000 1.0 CT Secondary(SEC) current

in LV side

LV Sec Inside

Delta

A 1.000 5.000 1.0 CT Secondary(SEC) cur-

rent in LV inside delta

HV Rated Cur Pri A 0 9999 Rated primary current for

Chapter 20 Appendix

250

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description


read only)

HV Rated Cur Sec

A 0 9999 Rated secondary current for


read only)

Ratio Factor KTAH

0 9999 HV ratio factor for differen-


value, read only)

Ratio Factor KTAM

0 9999 MV ratio factor for differen-


value, read only)

Ratio Factor KTAL

0 9999 LV ratio factor for differential

protection (calculated

value, read only)

Ratio REF KTAH

0 9999 HV ratio factor, with ze-




only)

Ratio REF KNH

0 9999 HV ratio factor with ze-




read only)

Ratio REF KTAM

0 9999 MV ratio factor, with ze-




only)

Ratio REF KNM

0 9999 MV ratio factor with ze-




read only)

I_Inst Diff A 0.5Ir 20Ir 20 Instantaneous Differential

(ID>>) current setting

Chapter 20 Appendix

251

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

I_Percent Diff A 0.08Ir 4Ir 2.1 Percentage Differential

(ID>) current setting

I_ResPoint1 Diff A 0.1Ir Ir 2 The 1st breakpoint restraint

current (IR1)

I_ResPoint2 Diff A 0.1Ir 10Ir 2 The 2nd breakpoint re-

straint current (IR2)

Slope1_Diff 0 0.2 0.2 the 1st slope

Slope2_Diff 0.2 0.7 0.5 the 2nd slope

Slope3_Diff 0.25 0.95 0.7 the 3rd slope

Ratio_2nd Harm 0.05 0.80 0.15 2nd harmonic(HAR) ratio

Ratio_3/5th Harm 0.05 0.80 0.35 3rd / 5th harmonic(HAR)

ratio

T_2nd Harm Block

s 0 20 20 Within the delay 2nd har-




blocked.

T_3/5th Harm

Block

s 0 20 20 Within the delay 5th har-




blocked.

HV 3I0_REF

A 0.08Ir 2Ir 2 Current setting for HV Re-

stricted Earth Fault protec-

tion

HV Slope_REF

0.2 0.95 0.5 Slope setting for HV Re-


tion

HV T_REF Trip s 0 60 0.03 HV Restricted Earth Fault

trip time setting

HV 3I0_REF Alarm A 0.08Ir 2Ir 2 HV Restricted Earth Fault

alarm current setting

HV T_REF Alarm s 0 60 0.03 HV Restricted Earth Fault

alarm time setting

MV 3I0_REF A 0.08Ir 2Ir 2 Current setting for MV Re-

Chapter 20 Appendix

252

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description


tion

MV Slope_REF

0.2 0.95 0.5 Slope setting for MV Re-


tion

MV T_REF Trip s 0 60 0.03 MV Restricted Earth Fault

trip time setting

MV 3I0_REF

Alarm

A 0.08Ir 2Ir 2 MV Restricted Earth Fault


MV T_REF Alarm s 0 60 0.03 MV Restricted Earth Fault

alarm time setting

LV 3I0_REF

A 0.08Ir 2Ir 2 Current setting for LV Re-


tion

LV Slope_REF

0.2 0.95 0.5 Slope setting for LV Re-


tion

LV T_REF Trip s 0 60 0.03 LV Restricted Earth Fault

trip time setting

LV 3I0_REF Alarm A 0.08Ir 2Ir 2 LV Restricted Earth Fault


LV T_REF Alarm s 0 60 0.03 LV Restricted Earth Fault

alarm time setting

Reference Voltage V 40 130 57.3 Nominal phase voltage in

HV side

V/F_Definite Alarm 1 1.5 1.1 Alarming setting of

volt/hertz

T_Definite Alarm s 0.1 9999 10 Timer setting for volt/hertz

alarming stage

V/F_Definite Trip 1 1.5 1.2 Tripping setting of definite

volt/hertz stage

T_Definite Trip s 0.1 9999 1 Timer setting for definite

volt/hertz stage

T1_Inverse

V/F=1.05

s 0.1 9999 10 Timer setting for

volt/hertz=1.05

T2_Inverse s 0.1 9999 90 Timer setting for

Chapter 20 Appendix

253

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

V/F=1.10 volt/hertz=1.10

T3_Inverse

V/F=1.15


volt/hertz=1.15

T4_Inverse

V/F=1.20


volt/hertz=1.20

T5_Inverse

V/F=1.25


volt/hertz=1.25

T6_Inverse

V/F=1.30


volt/hertz=1.30

T7_Inverse

V/F=1.35


volt/hertz=1.35

T8_Inverse

V/F=1.40


volt/hertz=1.40

T9_Inverse

V/F=1.45


volt/hertz=1.45

T10_Inverse

V/F=1.50


volt/hertz=1.50

T_Cool Down s 0.1 9999 25 Cool down time delay for

overexcitation protection

HV I_OC1 A 0.05Ir 20Ir 5 HV overcurrent (O/C) cur-

rent setting for Stage 1

HV T_OC1 s 0 60 60 Time setting for HV OC,

Stage 1

HV I_OC2 A 0.05Ir 20Ir 5 HV overcurrent (O/C) cur-


HV T_OC2 s 0 60 60 Time setting for HV OC,

Stage 2

HV Curve_OC Inv

1 12 1 Ref to IEC and ANSI

Curves

HV I_OC Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI

Curves

HV K_OC Inv 0.05 999 1 Ref to IEC and ANSI

Curves

HV A_OC Inv s 0 200 0.14 Ref to IEC and ANSI

Curves

Chapter 20 Appendix

254

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

HV B_OC Inv s 0 60 0 Ref to IEC and ANSI

Curves

HV P_OC Inv 0 10 0.02 Ref to IEC and ANSI

Curves

HV Angle_OC ° 0 90 45 The angle setting for volt-

age ahead of current.

HV

Imax_2H_UnBlk

A 0.25Ir 20Ir 5 The maximum 1st

-harmonic current setting to

remove the inrush block, in

HV O/C protection

HV Ratio_I2/I1

0.07 0.5 0.2 Inrush 2nd harmonic ratio

setting for blocking HV O/C

protection

HV T2h_Cross_Blk

s 0 60 20 Inrush 2nd harmonic

cross-block time for HV O/C

protection

MV I_OC1 A 0.05Ir 20Ir 5 MV overcurrent (O/C) cur-


MV T_OC1 s 0 60 60 Time setting for MV OC,

Stage 1

MV I_OC2 A 0.05Ir 20Ir 5 MV overcurrent (O/C) cur-


MV T_OC2 s 0 60 60 Time setting for MV OC,

Stage 2

MV Curve_OC Inv


Curves

MV I_OC Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI

Curves

MV K_OC Inv 0.05 999 1 Ref to IEC and ANSI

Curves

MV A_OC Inv s 0 200 0.14 Ref to IEC and ANSI

Curves

MV B_OC Inv s 0 60 0 Ref to IEC and ANSI

Curves

MV P_OC Inv 0 10 0.02 Ref to IEC and ANSI

Curves

Chapter 20 Appendix

255

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

MV Angle_OC ° 0 90 45 The angle setting for volt-


MV

Imax_2H_UnBlk




MV O/C protection

MV Ratio_I2/I1


setting for blocking MV O/C

protection

MV

T2h_Cross_Blk

s 0 60 20 Inrush 2nd harmonic

cross-block time for MV O/C

protection

LV I_OC1 A 0.05Ir 20Ir 5 LV overcurrent (O/C) cur-


LV T_OC1 s 0 60 60 Time setting for LV OC,

Stage 1

LV I_OC2 A 0.05Ir 20Ir 5 LV overcurrent (O/C) cur-


LV T_OC2 s 0 60 60 Time setting for LV OC,

Stage 2

MV Curve_OC Inv


Curves

LV I_OC Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI

Curves

LV K_OC Inv 0.05 999 1 Ref to IEC and ANSI

Curves

LV A_OC Inv s 0 200 0.14 Ref to IEC and ANSI

Curves

LV B_OC Inv s 0 60 0 Ref to IEC and ANSI

Curves

LV P_OC Inv 0 10 0.02 Ref to IEC and ANSI

Curves

LV Angle_OC 0 90 45 The angle setting for volt-


LV

Imax_2H_UnBlk

0.25Ir 20Ir 5 The maximum 1st


Chapter 20 Appendix

256

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description


LV O/C protection

LV Ratio_I2/I1


setting for blocking LV O/C

protection

LV T2h_Cross_Blk

0 60 20 Inrush 2nd harmonic

cross-block time for LV O/C

protection

HV 3I0_EF1

A 0.05Ir 20Ir 5 HV earth fault (E/F) protec-

tion current setting for Stage

1

HV T_EF1 s 0 60 60 Time setting for HV E/F,

Stage 1

HV 3I0_EF2 A 0.05Ir 20Ir 5 HV earth fault (E/F) current

setting for Stage 2

HV T_EF2 s 0 60 60 Time setting for HV E/F,

Stage 2

HV Curve_EF Inv 1 12 1 Ref to IEC and ANSI

Curves

HV 3I0_EF Inv A 0.05Ir 20Ir 1.2 Ref to IEC and ANSI

Curves

HV K_EF Inv 0.05 999 1 Ref to IEC and ANSI

Curves

HV A_EF Inv s 0 200 0.14 Ref to IEC and ANSI

Curves

HV B_EF Inv s 0 60 0 Ref to IEC and ANSI

Curves

HV P_EF Inv 0 10 0.02 Ref to IEC and ANSI

Curves

HV Angle_EF ° 0 90 45 The angle setting for volt-


HV

Imax_2H_UnBlk_E

F




HV EF protection

HV Ratio_I2/I1_EF 0.07 0.5 0.2 The maximum 1st

Chapter 20 Appendix

257

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description



HV EF protection

MV 3I0_EF1

A 0.05Ir 20Ir 5 MV earth fault (E/F) protec-


1

MV T_EF1 s 0 60 60 Time setting for MV E/F,

Stage 1

MV 3I0_EF2 A 0.05Ir 20Ir 5 MV earth fault (E/F) current

setting for Stage 2

MV T_EF2 s 0 60 60 Time setting for MV E/F,

Stage 2

MV Curve_EF Inv 1 12 1 Ref to IEC and ANSI

Curves

MV 3I0_EF Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI

Curves

MV K_EF Inv 0.05 999 1 Ref to IEC and ANSI

Curves

MV A_EF Inv s 0 200 0.14 Ref to IEC and ANSI

Curves

MV B_EF Inv s 0 60 0 Ref to IEC and ANSI

Curves

MV P_EF Inv 0 10 0.02 Ref to IEC and ANSI

Curves

MV Angle_EF ° 0 90 45 The angle setting for volt-


MV

Imax_2H_UnBlk_E

F




MV E/F protection

MV Ratio_I2/I1_EF


setting for blocking MV E/F

protection

LV 3I0_EF1

A 0.05Ir 20Ir 5 LV earth fault (E/F) protec-


1

Chapter 20 Appendix

258

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

LV T_EF1 s 0 60 60 Time setting for LV E/F,

Stage 1

LV 3I0_EF2 A 0.05Ir 20Ir 5 LV earth fault (E/F) current

setting for Stage 2

LV T_EF2 s 0 60 60 Time setting for LV E/F,

Stage 2

LV Curve_EF Inv 1 12 1 Ref to IEC and ANSI

Curves

LV 3I0_EF Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI

Curves

LV K_EF Inv 0.05 999 1 Ref to IEC and ANSI

Curves

LV A_EF Inv s 0 200 0.14 Ref to IEC and ANSI

Curves

LV B_EF Inv s 0 60 0 Ref to IEC and ANSI

Curves

LV P_EF Inv 0 10 0.02 Ref to IEC and ANSI

Curves

LV Angle_EF ° 0 90 45 The angle setting for volt-


LV

Imax_2H_UnBlk_E

F




LV E/F protection

LV Ratio_I2/I1_EF


setting for blocking LV E/F

protection

HV 3I0_Neutral

OC1

A 0.05Ir 20Ir 5 HV neutral over-current

(NOC) protection current

setting for Stage 1

HV T_Neutral OC1 s 0 60 60 Time setting for HV NOC,

Stage 1

HV 3I0_Neutral

OC2

A 0.05Ir 20Ir 5 HV neutral over-current


setting for Stage 2

HV T_Neutral OC2 s 0 60 60 Time setting for HV NOC,

Chapter 20 Appendix

259

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

Stage 1

HV Curve_NOC

Inv


Curves

HV 3I0_NOC Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI

Curves

HV K_NOC Inv 0.05 999 1 Ref to IEC and ANSI

Curves

HV A_NOC Inv s 0 200 0.14 Ref to IEC and ANSI

Curves

HV B_NOC Inv s 0 60 0 Ref to IEC and ANSI

Curves

HV P_NOC Inv 0 10 0.02 Ref to IEC and ANSI

Curves

HV Angle_NOC ° 0 90 45 The angle setting for volt-


HV

Imax_2H_UnBlk_

NOC




HV NOC protection

HV Ra-

tio_I2/I1_NOC


setting for blocking HV NOC

protection

MV 3I0_Neutral

OC1

A 0.05Ir 20Ir 5 MV neutral over-current


setting for Stage 1

MV T_Neutral OC1 s 0 60 60 Time setting for MV NOC,

Stage 1

MV 3I0_Neutral

OC2

A 0.05Ir 20Ir 5 MV neutral over-current


setting for Stage 2

MV T_Neutral OC2 s 0 60 60 Time setting for MV NOC,

Stage 1

MV Curve_NOC

Inv


Curves

MV 3I0_NOC Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI

Curves

Chapter 20 Appendix

260

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

MV K_NOC Inv 0.05 999 1 Ref to IEC and ANSI

Curves

MV A_NOC Inv s 0 200 0.14 Ref to IEC and ANSI

Curves

MV B_NOC Inv s 0 60 0 Ref to IEC and ANSI

Curves

MV P_NOC Inv 0 10 0.02 Ref to IEC and ANSI

Curves

MV Angle_NOC ° 0 90 45 The angle setting for volt-


MV

Imax_2H_UnBlk_

NOC




MV NOC protection

MV Ra-

tio_I2/I1_NOC


setting for blocking MV

NOC protection

LV 3I0_Neutral

OC1

A 0.05Ir 20Ir 5 LV neutral over-current


setting for Stage 1

LV T_Neutral OC1 s 0 60 60 Time setting for LV NOC,

Stage 1

LV 3I0_Neutral

OC2

A 0.05Ir 20Ir 5 LV neutral over-current


setting for Stage 2

LV T_Neutral OC2 s 0 60 60 Time setting for LV NOC,

Stage 1

LV Curve_NOC Inv 1 12 1 Ref to IEC and ANSI

Curves

LV 3I0_NOC Inv A 0.05Ir 20Ir 5 Ref to IEC and ANSI

Curves

LV K_NOC Inv 0.05 999 1 Ref to IEC and ANSI

Curves

LV A_NOC Inv s 0 200 0.14 Ref to IEC and ANSI

Curves

LV B_NOC Inv s 0 60 0 Ref to IEC and ANSI

Chapter 20 Appendix

261

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

Curves

LV P_NOC Inv 0 10 0.02 Ref to IEC and ANSI

Curves

LV Angle_NOC ° 0 90 45 The angle setting for volt-


LV

Imax_2H_UnBlk_

NOC




LV NOC protection

LV Ra-

tio_I2/I1_NOC


setting for blocking LV NOC

protection

HV I_Therm OL

Trip

A 0.1Ir 5Ir 2 Setting for HV-side thermal


HV I_Therm OL

Alarm

A 0.1Ir 5Ir 2 Setting for HV-side thermal


rent

HV T_Const

Therm

s 1 9999 10 Time const for HV-side


HV T_Const Cool

Down


HV-side thermal overload

MV I_Therm OL

Trip

A 0.1Ir 5Ir 2 Setting for MV-side thermal


MV I_Therm OL

Alarm

A 0.1Ir 5Ir 2 Setting for MV-side thermal


rent

MV T_Const

Therm

s 1 9999 10 Time const for MV-side


MV T_Const Cool

Down


MV-side thermal overload

HV I_OverLoad A 0.1Ir 4Ir 2 Overcurrent Setting of

overload

HV T_OverLoad s 0.1 3600 10 Time setting for overload

MV I_OverLoad A 0.1Ir 4Ir 2 Overcurrent Setting of

overload

Chapter 20 Appendix

262

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

MV T_OverLoad s 0.1 3600 10 Time setting for overload

LV I_OverLoad A 0.1Ir 4Ir 2 Overcurrent Setting of

overload

LV T_OverLoad s 0.1 3600 10 Time setting for overload

LW I_OvLd Alarm

A 0.1Ir 4Ir 20 Alarm current setting of LV

delta winding overload pro-

tection

LW T_OvLd Alarm

s 0.1 3600 10 Alarm time setting of LV


tection

LW I_OvLd Low

Trip

A 0.1Ir 4Ir 20 Low stage tripping current

setting

LW T_OvLd Low

Trip

s 0.1 3600 10 Low stage tripping time set-

ting

LW I_OvLd High

Trip

A 0.1Ir 4Ir 20 High stage tripping current

setting

LW T_OvLd High

Trip

s 0.1 3600 10 High stage tripping time

setting

HV U_OV1 V 40 200 200 HV voltage setting for stage

1 of overvoltage protection

HV T_OV1 s 0 60 60 HV time setting for stage 1


HV U_OV2 V 40 200 200 HV voltage setting for stage


HV T_OV2 s 0 60 60 HV time setting for stage 2


HV Dropout_OV 0.9 0.99 0.95 HV dropout ratio for over-

voltage protection

MV U_OV1 V 40 200 200 MV voltage setting for stage


MV T_OV1 s 0 60 60 MV time setting for stage 1


MV U_OV2 V 40 200 200 MV voltage setting for stage


MV T_OV2 s 0 60 60 MV time setting for stage 2


Chapter 20 Appendix

263

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

MV Dropout_OV 0.9 0.99 0.95 MV dropout ratio for over-

voltage protection

HV I_CBF OC

A 0.05Ir 20Ir 5 Phase current setting value

for HVcircuit breaker failure

(CBF) protection

HV 3I2_CBF NS

A 0.05Ir 20Ir 5 Negative sequence (NS)

current setting 23I value


HV 3I0_CBF ZS

A 0.05Ir 20Ir 5 Zero sequence (ZS) current

setting 03I value for HV1

CBF protection

HV T1_CBF s 0 32 10 Time setting value of Stage

1, for HV CBF protection

HV T2_CBF s 0.1 32 10 Time setting value of Stage

2, for HV CBF protection

MVI_CBF OC A 0.05Ir 20Ir 5 Phase current setting value


MV 3I2_CBF NS




MV 3I0_CBF ZS


setting 03I value for MV

CBF protection

MV T1_CBF s 0 32 10 Time setting value of Stage

1, for MV CBF protection

MV T2_CBF s 0.1 32 10 Time setting value of Stage

2, for MV CBF protection

LV I_CBF OC A 0.05Ir 20Ir 5 Phase current setting value


LV 3I2_CBF NS




Chapter 20 Appendix

264

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

LV 3I0_CBF ZS


setting 03I value for LV

CBF protection

LV T1_CBF s 0 32 10 Time setting value of Stage

1, for LV CBF protection

LV T2_CBF s 0.1 32 10 Time setting value of Stage

2, for LV CBF protection

HV T_Dead Zone

s 0 32 10 Time delay setting for HV


MV T_Dead Zone

s 0 32 10 Time delay setting for MV


LV T_Dead Zone

s 0 32 10 Time delay setting for LV


HV I_STUB A 0.05Ir 20Ir 100 current threshold of STUB

protection

HV T_STUB s 0 60 60 delay time of STUB protec-

tion

MV I_STUB A 0.05Ir 20Ir 100 current threshold of STUB

protection

MV T_STUB s 0 60 60 delay time of STUB protec-

tion

LV I_STUB A 0.05Ir 20Ir 100 current threshold of STUB

protection

LV T_STUB s 0 60 60 delay time of STUB protec-

tion

HV 3I0_PD

A 0.05Ir 20Ir 5 zero sequence current

threshold of pole discord-

ance protection

HV 3I2_PD

A 0.05Ir 20Ir 5 negative sequence current


ance protection

HV T_PD s 0 60 10 delay time of pole discord-

ance protection

MV 3I0_PD A 0.05Ir 20Ir 5 zero sequence current


Chapter 20 Appendix

265

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

ance protection

MV 3I2_PD

A 0.05Ir 20Ir 5 negative sequence current


ance protection

MV T_PD s 0 60 10 delay time of pole discord-

ance protection

HV I_VT Fail A 0.05Ir 0.2Ir 0.05 Minimum Current of VT

failure for HV side

HV 3I02_ VT Fail A 0.05Ir 0.2Ir 0.5 Minimum zero or negative

Current of HV VT fail

HV Upe_VT Fail V 7 20 8 Maximum phase to earth

voltage of HV VT fail

HV Upp_VT Fail V 10 30 16 Maximum phase to phase

voltage of HV VT fail

HV Upe_VT Nor-

mal

V 40 65 40 Minimum phase to phase

voltage of HV VT normal

MV I_VT Fail A 0.05Ir 0.2Ir 0.05 Minimum Current of VT

failure for MV side

MV 3I02_VT Fail A 0.05Ir 0.2Ir 0.5 Minimum zero or negative

Current of MV VT fail

MV Upe_VT Fail V 7 20 8 Maximum phase to earth

voltage of MV VT fail

MV Upp_VT Fail V 10 30 16 Maximum phase to phase

voltage of MV VT fail

MV Upe_VT Nor-

mal


voltage of MV VT normal

LV I_VT Fail A 0.05Ir 0.2Ir 0.05 Minimum Current of VT

failure for LV side

LV 3I02_VT Fail A 0.05Ir 0.2Ir 0.5 Minimum zero or negative

Current of LV VT fail

LV Upe_VT Fail V 7 20 8 Maximum phase to earth

voltage of LV VT fail

LV Upp_VT Fail V 10 30 16 Maximum phase to phase

voltage of LV VT fail

LV Upe_VT Nor-

mal


voltage of LV VT normal

Chapter 20 Appendix

266

Setting Unit

Min.

(Ir:5A/1

A)

Max.

(Ir:5A/1

A)

Default

setting

(Ir:5A/1

A)

Description

T_Pulse Tripping s 0.2 5 5 delay time of STUB protec-

tion

1.2 Binary setting list


setting Description

Auto Trans 0 1 0

Autotransformer not comm

on transformer

1-autotransformer ;

0- not autotransformer

Two-Wind Trans

0 1 0

Two-winding(TWO WIND )

not three -winding trans-

former (TRANS)

1-two-winding trans;

0-three-winding trans

CT Fail Detect 0 1 0

VT Failure Detection On/Off

1-On, 0-Off.


Default

setting Description

Func_Inst Diff 0 1 0

Instantaneous differential

protection ON 1-on; 0-off.

Func_Percent Diff 0 1 0

Percentage differential pro-

tection ON 1-on; 0-off.

Block Diff at Inrush

0 1 0

Inrush block differential pro-

tection


2nd Harm Not

Wave

0 1 0

2nd harmonic (HAR) inhibit

not the fuzzy recognition

based on the wave-

form(WAVE)

1-2nd harmonic on; 0-

waveform on

Block Diff at

Overexcit 0 1 0

Overexcitation block differ-

ential protection


Overexcit 3rd NOT

5th 0 1 0

Overexcitation stabilization

judgement

Chapter 20 Appendix

267


setting Description

3rd or 5th harmonic (HAR)

inhibit on

1-3rd harmonic; 0-5th har-

monic.

Func_Diff Alarm

0 1 0

Differential current (DIFF)

Alarming on

1-on; 0-off.

Block Diff at

CT_Fail 0 1 0

Block differential protection

when there is CT failure


HV D_side Elimi-

nate I0 0 1 0


when HV side winding is



MV D_side Elimi-

nate I0 0 1 0


when MV side winding is



LV D_side Elimi-

nate I0 0 1 0


when LV side winding is



Diff Includes LV

Cur

0 1 0

LV current is included in

calculation of the differential

protection.

1- Diff Includes LV Cur;

0-Diff NOT Includes LV Cur

HV Func_REF Trip

0 1 0


trip-stage ON

1-on; 0-off.

HV Func_REF

Alarm 0 1 0


Alarm-stage ON

1-on; 0-off.

Block HV REF at

HV CT_Fail 0 1 0

Block HV REF when CT

failure,

1-Block;0-unblock

MV Func_REF Trip 0 1 0


trip-stage ON 1-on; 0-off.

MV Func_REF

Alarm 0 1 0


Alarm-stage ON

1-on; 0-off.

Chapter 20 Appendix

268


setting Description

Block MV REF at

MV CT_Fail 0 1 0

Block MV REF when CT

failure,

1-Block;0-unblock

LV Func_REF Trip 0 1 0


trip-stage ON 1-on; 0-off.

LV Func_REF

Alarm 0 1 0


Alarm-stage ON

1-on; 0-off.

Block LV REF at

LV CT_Fail 0 1 0

Block LV REF when CT fail-

ure,

1-Block;0-unblock

HV

Func_Overexcit 0 1 0

HV Overexcitation (V/F) on

1-on; 0-off.

MV

Func_Overexcit 0 1 0

MV Overexcitation (V/F) on

1-on; 0-off.

LV Func_Overexcit 0 1 0

LV Overexcitation (V/F) on

1-on; 0-off.

Func_Overexcit

Alarm Def 0 1 0

Definite Overexcitation (V/F)

Alarming on

1-on; 0-off.

Func_Overexcit

Trip Def 0 1 0

Definite (DEF)Overexcitation

(V/F) on

1-on; 0-off.

Func_Overexcit

Trip Inv 0 1 0

Inverse (IVR)Overexcitation

(V/F) on

1-on; 0-off.

V/F Volt-

age(0-VPP,1-VPN)

0 1 0

Overexcitation protection

uses phase-to-phase volt-

age (VPP) or phase-to-earth

voltage (VPN)

0-VPP; 1-VPN.

HV Func_OC1

0 1 0

The 1st stage of HV OC

(OC_1) protection is

switched ON

1-on; 0-off.

HV OC1 Direction

0 1 0

Direction (DIR) detection of

HV OC Stage 1 is switched

ON

1-on; 0-off.

HV OC1 Dir To Sys 0 1 0

Direction unit of HV OC


Chapter 20 Appendix

269


setting Description

0 - point to the protected

transformer

1- point to system

HV OC1 Inrush

Block 0 1 0

Inrush 2nd harmonic detec-

tion HV OC Stage 1 is

switched ON

1-on; 0-off.

HV Func_OC2

0 1 0

The 2nd stage of HV OC


switched ON

1-on; 0-off.

HV OC2 Direction

0 1 0


HV OC Stage 2 is switched

ON

1-on; 0-off.

HV OC2 Dir To Sys

0 1 0




transformer

1- point to system

HV OC2 Inrush

Block 0 1 0


tion HV OC Stage 2 is

switched ON

1-on; 0-off.

HV Func_OC Inv

0 1 0

The IDMTL inverse time

stage of HV OC protection is

switched ON

1-on; 0-off.

HV OC Inv Direc-

tion 0 1 0


HV OC IDMTL inverse time

is switched ON

1-on; 0-off.

HV OC Inv Dir To

Sys

0 1 0


IDMTL inverse time points to

system


transformer

1- point to system

HV OC Inv Inrush

Block 0 1 0


tion HV OC IDMTL inverse

time is switched ON

Chapter 20 Appendix

270


setting Description

1-on; 0-off.

Block HV OC at

HV VT_Fail

0 1 0

Select to block HV OC pro-

tection or exit direction unit,

when HV VT fails

0- HV Direct OK at HV VT

Fail

1- Blk HV OC at HV VT Fail

HV OC Initiate LV

CBF 0 1 0

HV OC protection initiate LV

side CBF


HV OC Initiate MV

CBF 0 1 0

HV OC protection initiate MV

side CBF


MV Func_OC1

0 1 0

The 1st stage of MV OC


switched ON

1-on; 0-off.

MV OC1 Direction

0 1 0


MV OC Stage 1 is switched

ON

1-on; 0-off.

MV OC1 Dir To

Sys

0 1 0

Direction unit of MV OC



transformer

1- point to system

MV OC1 Inrush

Block 0 1 0


tion MV OC Stage 1 is

switched ON

1-on; 0-off.

MV Func_OC2

0 1 0

The 2nd stage of MV OC


switched ON

1-on; 0-off.

MV OC2 Direction

0 1 0


MV OC Stage 2 is switched

ON

1-on; 0-off.

MV OC2 Dir To

Sys 0 1 0




Chapter 20 Appendix

271


setting Description

transformer

1- point to system

MV OC2 Inrush

Block 0 1 0


tion MV OC Stage 2 is

switched ON

1-on; 0-off.

MV Func_OC Inv

0 1 0


stage of MV OC protection is

switched ON

1-on; 0-off.

MV OC Inv Direc-

tion 0 1 0


MV OC IDMTL inverse time

is switched ON

1-on; 0-off.

MV OC Inv Dir To

Sys

0 1 0



system


transformer

1- point to system

MV OC Inv Inrush

Block 0 1 0


tion MV OC IDMTL inverse

time is switched ON

1-on; 0-off.

Block MV OC at

MV VT_Fail

0 1 0

Select to block MV OC pro-


when MV VT fails

0- MV Direct OK at MV VT

Fail

1- Blk MV OC at MV VT Fail

MV OC Initiate

HV1 CBF 0 1 0

MV OC protection initiate

HV1 side CBF


LV Func_OC1

0 1 0

The 1st stage of LV OC


switched ON

1-on; 0-off.

LV OC1 Direction

0 1 0


LV OC Stage 1 is switched

ON

1-on; 0-off.

Chapter 20 Appendix

272


setting Description

LV OC1 Dir To Sys

0 1 0

Direction unit of LV OC



transformer

1- point to system

LV OC1 Inrush

Block 0 1 0


tion LV OC Stage 1 is

switched ON

1-on; 0-off.

LV Func_OC2

0 1 0

The 2nd stage of LV OC


switched ON

1-on; 0-off.

LV OC2 Direction

0 1 0


LV OC Stage 2 is switched

ON

1-on; 0-off.

LV OC2 Dir To Sys

0 1 0




transformer

1- point to system

LV OC2 Inrush

Block 0 1 0


tion LV OC Stage 2 is

switched ON

1-on; 0-off.

LV Func_OC Inv

0 1 0


stage of LV OC protection is

switched ON

1-on; 0-off.

LV OC Inv Direc-

tion 0 1 0


LV OC IDMTL inverse time is

switched ON

1-on; 0-off.

LV OC Inv Dir To

Sys

0 1 0



system


transformer

1- point to system

LV OC Inv Inrush 0 1 0 Inrush 2nd harmonic detec-

Chapter 20 Appendix

273


setting Description

Block tion LV OC IDMTL inverse

time is switched ON

1-on; 0-off.

Block LV OC at LV

VT_Fail

0 1 0

Select to block LV OC pro-


when LV VT fails

0- LV Direct OK at LV VT Fail

1- Blk LV OC at LV VT Fail

LV OC Initiate HV1

CBF 0 1 0

LV OC protection initiate

HV1 side CBF


HV Func_EF1

0 1 0

The 1st stage of HV earth

fault (EF_1) protection is

switched ON

1-on; 0-off.

HV EF1 Direction

0 1 0


HV EF Stage 1 is switched

ON

1-on; 0-off.

HV EF1 Dir To Sys

0 1 0

Direction unit of HV EF



transformer

1- point to system

HV EF1 Inrush

Block 0 1 0


tion HV EF Stage 1 is

switched ON

1-on; 0-off.

HV Func_EF2

0 1 0

The 2nd stage of HV earth


switched ON

1-on; 0-off.

HV EF2 Direction

0 1 0


HV EF Stage 2 is switched

ON

1-on; 0-off.

HV EF2 Dir To Sys

0 1 0




transformer

1- point to system

Chapter 20 Appendix

274


setting Description

HV EF2 Inrush

Block 0 1 0


tion HV EF Stage 2 is

switched ON

1-on; 0-off.

HV Func_EF Inv

0 1 0


stage of HV EF protection is

switched ON

1-on; 0-off.

HV EF Inv Direc-

tion 0 1 0


HV EF IDMTL inverse time is

switched ON

1-on; 0-off.

HV EF Inv Dir To

Sys

0 1 0



system


transformer

1- point to system

HV EF Inv Inrush

Block 0 1 0


tion HV EF IDMTL inverse

time is switched ON

1-on; 0-off.

Block HV EF at HV

VT_Fail

0 1 0

Select to block HV EF pro-


when HV VT fails

0 - HV Direct OK at HV VT

Fail

1 - Blk HV EF at HV VT Fail

Block HV EF at HV

CT_Fail 0 1 0

Block HV EF when there is

HV CT failure


HV EF Initiate LV

CBF 0 1 0

HV EF protection initiate LV

side CBF


HV EF Initiate MV

CBF 0 1 0

HV EF protection initiate MV

side CBF


MV Func_EF1

0 1 0

The 1st stage of MV earth


switched ON

1-on; 0-off.

Chapter 20 Appendix

275


setting Description

MV EF1 Direction

0 1 0


MV EF Stage 1 is switched

ON

1-on; 0-off.

MV EF1 Dir To Sys

0 1 0

Direction unit of MV EF



transformer

1- point to system

MV EF1 Inrush

Block 0 1 0


tion MV EF Stage 1 is

switched ON

1-on; 0-off.

MV Func_EF2

0 1 0

The 2nd stage of MV earth


switched ON

1-on; 0-off.

MV EF2 Direction

0 1 0


MV EF Stage 2 is switched

ON

1-on; 0-off.

MV EF2 Dir To Sys

0 1 0




transformer

1- point to system

MV EF2 Inrush

Block 0 1 0


tion MV EF Stage 2 is

switched ON

1-on; 0-off.

MV Func_EF Inv

0 1 0


stage of MV EF protection is

switched ON

1-on; 0-off.

MV EF Inv Direc-

tion 0 1 0


MV EF IDMTL inverse time

is switched ON

1-on; 0-off.

MV EF Inv Dir To

Sys 0 1 0



system

Chapter 20 Appendix

276


setting Description


transformer

1- point to system

MV EF Inv Inrush

Block 0 1 0


tion MV EF IDMTL inverse

time is switched ON

1-on; 0-off.

Block MV EF at

MV VT_Fail

0 1 0

Select to block MV EF pro-


when MV VT fails

0 - MV Direct OK at MV VT

Fail

1 - Blk MV EF at MV VT Fail

Block MV EF at

MV CT_Fail 0 1 0

Block MV EF when there is

MV CT failure


MV EF Initiate HV

CBF 0 1 0

MV EF protection initiate

HV1 side CBF


LV Func_EF1

0 1 0

The 1st stage of LV earth


switched ON

1-on; 0-off.

LV EF1 Direction

0 1 0


LV EF Stage 1 is switched

ON

1-on; 0-off.

LV EF1 Dir To Sys

0 1 0

Direction unit of LV EF Stage

1 points to system


transformer

1- point to system

LV EF1 Inrush

Block 0 1 0


tion LV EF Stage 1 is

switched ON

1-on; 0-off.

LV Func_EF2

0 1 0

The 2nd stage of LV earth


switched ON

1-on; 0-off.

LV EF2 Direction 0 1 0 Direction (DIR) detection of

Chapter 20 Appendix

277


setting Description

LV EF Stage 2 is switched

ON

1-on; 0-off.

LV EF2 Dir To Sys

0 1 0

Direction unit of LV EF Stage

2 points to system


transformer

1- point to system

LV EF2 Inrush

Block 0 1 0


tion LV EF Stage 2 is

switched ON

1-on; 0-off.

LV Func_EF Inv

0 1 0


stage of LV EF protection is

switched ON

1-on; 0-off.

LV EF Inv Direction

0 1 0


LV EF IDMTL inverse time is

switched ON

1-on; 0-off.

LV EF Inv Dir To

Sys

0 1 0

Direction unit of LV EF


system


transformer

1- point to system

LV EF Inv Inrush

Block 0 1 0


tion LV EF IDMTL inverse

time is switched ON

1-on; 0-off.

Block LV EF at LV

VT_Fail

0 1 0

Select to block LV EF pro-


when LV VT fails

0 - LV Direct OK at LV VT

Fail

1 - Blk LV EF at LV VT Fail

Block LV EF at LV

CT_Fail 0 1 0

Block LV EF when there is

LV CT failure


LV EF Initiate HV

CBF 0 1 0

LV EF protection initiate HV1

side CBF

Chapter 20 Appendix

278


setting Description


HV Func_Neu

OC1 0 1 0

The 1st stage of HV neutral

OC (OC_1) protection is

switched ON

1-on; 0-off.

HV Neu OC1 Di-

rection 0 1 0



switched ON

1-on; 0-off.

HV Neu OC1 Dir

To Sys

0 1 0

Direction unit of HV neutral

OC Stage 1 points to system


transformer

1- point to system

HV Neu OC1 In-

rush Block 0 1 0


tion HV neutral OC Stage 1

is switched ON

1-on; 0-off.

HV Func_Neu

OC2 0 1 0

The 2nd stage of HV neutral


switched ON

1-on; 0-off.

HV Neu OC2 Di-

rection 0 1 0



switched ON

1-on; 0-off.

HV Neu OC2 Dir

To Sys

0 1 0




transformer

1- point to system

HV Neu OC2 In-

rush Block 0 1 0


tion HV neutral OC Stage 2

is switched ON

1-on; 0-off.

HV Func_Neu OC

Inv 0 1 0


stage of HV neutral OC pro-


1-on; 0-off.

HV Neu OC Inv

Direction 0 1 0


HV neutral OC IDMTL in-

Chapter 20 Appendix

279


setting Description

verse time stage is switched

ON

1-on; 0-off.

HV Neu OC Inv Dir

To Sys

0 1 0


OC IDMTL inverse time

stage points to system


transformer

1- point to system

HV Neu OC Inv

Inrush Block

0 1 0


tion HV neutral OC IDMTL

inverse time stage is

switched ON

1-on; 0-off.

Block HV NOC at

HV VT_Fail

0 1 0

Select to block HV neutral

OC protection or exit direc-

tion unit, when HV VT fails

0 - HV Direct OK at HV VT

Fail

1 - Blk HV NOC at HV VT

Fail

HV Neu OC Init

MV CBF 0 1 0

HV neutral OC protection

initiate LV side CBF


MV Func_Neu

OC1 0 1 0

The 1st stage of MV neutral


switched ON

1-on; 0-off.

MV Neu OC1 Di-

rection 0 1 0



switched ON

1-on; 0-off.

MV Neu OC1 Dir

To Sys

0 1 0

Direction unit of MV neutral



transformer

1- point to system

MV Neu OC1 In-

rush Block 0 1 0


tion MV neutral OC Stage 1

is switched ON

1-on; 0-off.

Chapter 20 Appendix

280


setting Description

MV Func_Neu

OC2 0 1 0

The 2nd stage of MV neutral


switched ON

1-on; 0-off.

MV Neu OC2 Di-

rection 0 1 0



switched ON

1-on; 0-off.

MV Neu OC2 Dir

To Sys

0 1 0




transformer

1- point to system

MV Neu OC2 In-

rush Block 0 1 0


tion MV neutral OC Stage 2

is switched ON

1-on; 0-off.

MV Func_Neu OC

Inv 0 1 0


stage of MV neutral OC


1-on; 0-off.

MV Neu OC Inv

Direction

0 1 0


MV neutral OC IDMTL in-


ON

1-on; 0-off.

MV Neu OC Inv Dir

To Sys

0 1 0





transformer

1- point to system

MV Neu OC Inv

Inrush Block

0 1 0


tion MV neutral OC IDMTL


switched ON

1-on; 0-off.

Block MV NOC at

MV VT_Fail 0 1 0

Select to block MV neutral


tion unit, when MV VT fails

0 - MV Direct OK at MV VT

Chapter 20 Appendix

281


setting Description

Fail

1 - Blk MV NOC at MV VT

Fail

MV Neu OC Init

MV CBF 0 1 0

MV neutral OC protection



LV Func_Neu OC1

0 1 0

The 1st stage of LV neutral


switched ON

1-on; 0-off.

LV Neu OC1 Di-

rection 0 1 0



switched ON

1-on; 0-off.

LV Neu OC1 Dir To

Sys

0 1 0

Direction unit of LV neutral



transformer

1- point to system

LV Neu OC1 In-

rush Block 0 1 0


tion LV neutral OC Stage 1 is

switched ON

1-on; 0-off.

LV Func_Neu OC2

0 1 0

The 2nd stage of LV neutral


switched ON

1-on; 0-off.

LV Neu OC2 Di-

rection 0 1 0



switched ON

1-on; 0-off.

LV Neu OC2 Dir To

Sys

0 1 0




transformer

1- point to system

LV Neu OC2 In-

rush Block 0 1 0


tion LV neutral OC Stage 2 is

switched ON

1-on; 0-off.

LV Func_Neu OC 0 1 0 The IDMTL inverse time

Chapter 20 Appendix

282


setting Description

Inv stage of LV neutral OC pro-


1-on; 0-off.

LV Neu OC Inv

Direction

0 1 0


LV neutral OC IDMTL in-


ON

1-on; 0-off.

LV Neu OC Inv Dir

To Sys

0 1 0





transformer

1- point to system

LV Neu OC Inv

Inrush Block

0 1 0


tion LV neutral OC IDMTL


switched ON

1-on; 0-off.

Block LV NOC at

LV VT_Fail

0 1 0

Select to block LV neutral


tion unit, when LV VT fails

0 - LV Direct OK at LV VT

Fail

1 - Blk LV NOC at LV VT Fail

LV Neu OC Init LV

CBF 0 1 0

LV neutral OC protection



HV Func_Thermal

OvLd 0 1 0

Thermal overload in HV side

is switched on

0 - OFF, 1 - ON

HV Cold Curve

0 1 0

HV side using hot/cold curve

type

0 – Hot curve, 1 – Cold curve

HV Thermal Init LV

CBF 0 1 0

HV thermal overload protec-

tion initiate LV side CBF


HV Thermal Init

MV CBF 0 1 0

HV thermal overload protec-



MV Func_Thermal 0 1 0 Thermal overload in MV side

Chapter 20 Appendix

283


setting Description

OvLd is switched on

0 - OFF, 1 - ON

MV Cold Curve

0 1 0

MV side using hot/cold curve

type

0 – Hot curve, 1 – Cold curve

MV Thermal Init

HV1 CBF 0 1 0

MV thermal overload protec-

tion initiate HV side CBF


HV

Func_OverLoad 0 1 0

Overload (LOAD) protection

in HV side is switched ON

1-on; 0-off.

MV

Func_OverLoad 0 1 0

Overload (LOAD)in MV side

on

LV

Func_OverLoad 0 1 0

Overload (LOAD)in LV side

on

LW Func_OvLd

Alarm

0 1 0

Alarm stage of LV delta

winding (LWIND) overload

(LOAD) protection is

switched ON.

1-on; 0-off.

LW Func_OvLd

Low Trip 0 1 0



tection is switched ON.

1-on; 0-off.

LW Func_OvLd

High Trip 0 1 0



tection is switched ON.

1-on; 0-off.

Low Trip Init HV1

CBF 0 1 0



tection initiate HV1 side CBF


High Trip Init HV1

CBF 0 1 0



tection initiate HV1 side CBF


Low Trip Init MV

CBF 0 1 0



tection initiate MV side CBF


Chapter 20 Appendix

284


setting Description

High Trip Init MV

CBF 0 1 0



tection initiate MV side CBF

- initiate, 1 – not initiate

HV Func_OV1 0 1 0

HV overvoltage stage 1 en-

abled or disabled

HV Func_OV2 0 1 0

HV overvoltage stage 1 trip

or alarm

HV Func_OV2 0 1 0

HV overvoltage stage 2 en-

abled or disabled

HV OV2 Trip 0 1 0

HV overvoltage stage 2 trip

or alarm

HV OV Chk PE

0 1 0

HV phase to phase voltage

or phase to earth measured

for overvoltage protection

MV Func_OV1 0 1 0

MV overvoltage stage 1 en-

abled or disabled

MV Func_OV2 0 1 0

MV overvoltage stage 1 trip

or alarm

MV Func_OV2 0 1 0

MV overvoltage stage 2 en-

abled or disabled

MV OV2 Trip 0 1 0

MV overvoltage stage 2 trip

or alarm

MV OV Chk PE

0 1 0

MV phase to phase voltage

or phase to earth measured

for overvoltage protection

HV Func_CBF

0 1 0

HV Circuit breaker failure

(CBF) protection is switched

ON

1-on; 0-off.

HV 3I0/3I2 Check

On 0 1 0

HV CBF protection detect

negative or zero sequence

current 3I0 or 3I2.


HV CB Status

Check On 0 1 0

HV CBF protection detect

HV1 CB status


MV Func_CBF

0 1 0

MV Circuit breaker failure


ON

1-on; 0-off.

Chapter 20 Appendix

285


setting Description

MV 3I0/3I2 Check

On 0 1 0

MV CBF protection detect


current 3I0 or 3I2.


MV CB Status

Check On 0 1 0

MV CBF protection detect

MV CB status


LV Func_CBF

0 1 0

LV Circuit breaker failure


ON

1-on; 0-off.

LV 3I0/3I2 Check

On 0 1 0

LV CBF protection detect


current 3I0 or 3I2.


LV CB Status

Check On 0 1 0

LV CBF protection detect LV

CB status


HV Func_Dead

Zone 0 1 0

Dead zone protection is

switched ON

1-on; 0-off.

MV Func_Dead

Zone 0 1 0


switched ON

1-on; 0-off.

LV Func_Dead

Zone 0 1 0


switched ON

1-on; 0-off.

HV Func_STUB 0 1 0


protection

HV STUB Init LV

CBF 0 1 0

STUB protection initiate LV

side CBF


HV STUB Init MV

CBF 0 1 0

STUB protection initiate HV

side CBF


MV Func_STUB 0 1 0


protection

MV STUB Init LV

CBF 0 1 0


side CBF


Chapter 20 Appendix

286


setting Description

MV STUB Init MV

CBF 0 1 0

STUB protection initiate MV

side CBF


LV Func_STUB 0 1 0


protection

LV STUB Init LV

CBF 0 1 0


side CBF


LV STUB Init MV

CBF 0 1 0


side CBF


MV Func_PD 0 1 0

Enable or disable MV poles

discordance protection

MV PD Chk 3I0/3I2 0 1 0

Enable or disable 3I0/3I2

criteria

MV Func_PD 0 1 0

Enable or disable MV poles

discordance protection

MV PD Chk 3I0/3I2 0 1 0

Enable or disable 3I0/3I2

criteria

HV VT FAIL Detect

0 0 1

HV VT Failure Detection

On/Off

1-On, 0-Off.

HV Solid Earth

0 0 1

HV Earthing mode:

1: Solid earthed system ;

0: isolated system or re-

sistance earthed.

MV VT FAIL Detect

0 0 1

MV VT Failure Detection

On/Off

1-On, 0-Off.

MV Solid Earth

0 0 1

MV Earthing mode:



sistance earthed.

LV VT FAIL Detect

0 0 1

LV VT Failure Detection

On/Off

1-On, 0-Off.

LV Solid Earth

0 0 1

LV Earthing mode:



sistance earthed.

Chapter 20 Appendix

287


setting Description

BI1 Enable BO1 0 0 1

To select whether the 1st

binary input (BI1) trip the 1st


1-enable, 0-disable

BO1 Pulse Trip-

ping 0 0 1

To select BO1 tripping in

pulse mode or in direct mode

0- BO1 Direct Tripping,

without delay

1- BO1 Pulse Tripping, with

preset delay time

BI2 Enable BO2 0 0 1

To select whether the 2nd

binary input (BI2) trip the 2nd


1-enable, 0-disable

BO2 Pulse Trip-

ping 0 0 1

To select BO2 tripping in

pulse mode or in direct mode

0- BO2 Direct Tripping,

without delay

1- BO2 Pulse Tripping, with

preset delay time

BI1 Init HV CBF 0 0 1

whether BI1 initiate HV side

CBF or not


BI1 Init MV CBF 0 0 1

whether BI1 initiate MV side

CBF or not


BI1 Init LV CBF 0 0 1

whether BI1 initiate LV side

CBF or not


BI2 Init HV CBF 0 0 1

whether BI2 initiate HV side

CBF or not


BI2 Init MV CBF 0 0 1

whether BI2 initiate MV side

CBF or not


BI2 Init LV CBF 0 0 1

whether BI2 initiate LV side

CBF or not


Chapter 20 Appendix

288

2 General report list

Table 173 event report list


Relay startup The relay is initiated by startup elements

Per Diff Trip A

Treble slope percent Differential protection (ID>) trip for phase A/B/C Per Diff Trip B

Per Diff Trip C

Inst Diff Trip A

Instantaneous Differential protection (ID>>) trip for phase A/B/C Inst Diff Trip B

Inst Diff Trip C

HV REF Trip HV Restricted Earth fault (REF) protection trip

MV REF Trip MV Restricted Earth fault (REF) protection trip

LV REF Trip LV Restricted Earth fault (REF) protection trip

Def V/F Trip Overexcitation protection(V/F) tripping (Trip) with definite (DEF) and

inverse(IVR) time characteristic Inv V/F Trip

HV OC Inv Trip Inverse time stage of HV overcurrent protection trip



MV OC Inv Trip Inverse time stage of MV overcurrent protection trip



LV OC Inv Trip Inverse time stage of LV overcurrent protection trip



HV EF Inv Trip Inverse time stage of HV earth fault protection trip



MV EF Inv Trip Inverse time stage of MV earth fault protection trip



Chapter 20 Appendix

289


LV EF Inv Trip Inverse time stage of LV earth fault protection trip



HV NOC Inv Trip Inverse time stage of neutral OC protection trip



MV EF Inv Trip Inverse time stage of MV neutral OC protection trip



LV EF Inv Trip Inverse time stage of LV neutral OC protection trip



HV Therm OL Trip HV Thermal (TEM) Overload(OVLD) tripping (Trip)

MV Therm OL Trip MV Thermal (TEM) Overload(OVLD) tripping (Trip)







HV CBF Init Internal or external initiate HV circuit breaker failure protection



MV CBF Init Internal or external initiate MV circuit breaker failure protection



LV CBF Init Internal or external initiate LV circuit breaker failure protection

HV Dead Zone HV Dead zone trip

MV Dead Zone MV Dead zone trip

LV Dead Zone LV Dead zone trip

HV STUB Trip HV STUB protection trip

Chapter 20 Appendix

290


MV STUB Trip MV STUB protection trip

LV STUB Trip LV STUB protection trip

HV PD Trip HV poles discordance protection trip

MV PD Trip MV poles discordance protection trip

HV VT Fail HV VT Fail alarm

MV VT Fail MV VT Fail alarm

LV VT Fail LV VT Fail alarm


No Abbr. (LCD Display) Description

1 Battery Off Battery off

2 BI Breakdown Binary input breakdown

3 BI Check Err Binary input checking is error

4 BI Comm Fail Binary input communication fail

5 BI Config Err Binary input configuration is error

6 BI EEPROM Err The EEPROM of binary input is error

7 BI Input Err Binary input error

8 BI_CBF Err Binary input error of CBF

9 BO Breakdown Binary output breakdown

10 BO Comm Fail Binary output communication fail

11 BO EEPROM Err The EEPROM of binary output is error

12 BO No Response No response of binary output

13 BOConfig Err Binary output configuration is error

14

CB Err Blk PD

CB auxiliary contacts indicate that one

pole is open but at the same time current is

flowing through the pole.

15 CB Open A Err Binary input error of CB Open A

16 CB Open B Err Binary input error of CB Open B

Chapter 20 Appendix

291

17 CB Open C Err Binary input error of CB Open C

18 CB Status Err CB Status Error

19 Def V/F Alarm Def V/F Alarm

20

Diff 2har Blk Inrush detection impose a blocking condi-

tion to differential protection

21

Diff 3/5har Blk 3rd or 5th harmonic detection impose a

blocking condition to differential protection

22

Diff Cur Alarm Differential current exceeds the threshold

value

23 EquipPara Err Equipment parameter is error

24 FLASH Check Err FLASH checking is error

25 H BI MCB VT Fail Binary input error of VT fail of MCB

26 H BI_V3P_MCB Err Binary input error of three phase MCB

27 HV 3U0 Alarm HV 3U0 Alarm

28 HV BLK VOL REGU Block tap changer control of transformer

29

HV Inrush Blk BU a blocking condition is imposed to backup

protection by inrush condition detection

30 HV Load Alarm HV Load Alarm

31 HV OV1 Alarm Stage 1 of overvoltage protection alarm

32 HV OV2 Alarm Stage 2 of overvoltage protection alarm

33 HV REF 3I0 Alarm HV REF 3I0 Alarm

34 HV Therm OL Alm HV Thermal Overload Alarm

35 HV VT Fail HV VT Fail

36

HV1 I2 Alarm Negative-sequence current exceeds a thresh-

old

37

HV2 I2 Alarm Negative-sequence current exceeds a thresh-

old

38 L BI MCB VT Fail Binary input error of VT fail of MCB

39 L BI_V3P_MCB Err Binary input error of three phase MCB

40 LV 3U0 Alarm LV 3U0 Alarm

Chapter 20 Appendix

292

41

LV I2 Alarm Negative-sequence current exceeds a thresh-

old

42

LV Inrush Blk BU a blocking condition is imposed to backup


43 LV Load Alarm LV Load Alarm

44 LV REF 3I0 Alarm LV REF 3I0 Alarm

45 LV Therm OL Alm

LV Thermal Overload Alarm

46 LV VT Fail LV VT Fail

47 LW Load Alarm LW Load Alarm

48 M BI MCB VT Fail Binary input error of VT fail of MCB

49 M BI_V3P_MCB Err Binary input error of three phase MCB

50 MV 3U0 Alarm MV 3U0 Alarm

51 MV BLK VOL REGU Block tap changer control of transformer

52

MV I2 Alarm Negative-sequence current exceeds a thresh-

old

53

MV Inrush Blk BU a blocking condition is imposed to backup


54 MV Load Alarm MV Load Alarm

55 MV OV1 Alarm Stage 1 of overvoltage protection alarm

56 MV OV2 Alarm Stage 2 of overvoltage protection alarm

57 MV REF 3I0 Alarm MV REF 3I0 Alarm

58 MV Therm OL Alm

MV Thermal Overload Alarm

59 MV VT Fail MV VT Fail

60 NO/NC Discord NO/NC discord

61 Ph_A CT Fail Phase A CT Fail

62 Ph_B CT Fail Phase B CT Fail

63 Ph_C CT Fail Phase C CT Fail

64 ROM Verify Err ROM verifying is error

65 Sampling Err Sampling is error

66 Set Group Err Setting group is error

67 Setting Err Setting value is error

68 Soft Version Err Soft version is error

69 SRAM Check Err SRAM checking is error

70 Sys Config Err System configuration is error

Chapter 20 Appendix

293

71 Test BO Un_reset Do not reset after testing binary output

72

V or F Exceed Voltage or frequency is out of the permissible

range

Table 175 operation report list

No Information Description

1 Func_Diff On Differential protection is switched ON (by CW)

2 Func_Diff Off Differential protection is switched OFF (by CW)

3 HV Func_REF On HV REF protection is switched ON (by CW)

4 HV Func_REF Off HV REF protection is switched OFF (by CW)

5 MV Func_REF On MV REF protection is switched ON (by CW)

6 MV Func_REF Off MV REF protection is switched OFF (by CW)

7 LV Func_REF On LV REF protection is switched ON (by CW)

8 LV Func_REF Off LV REF protection is switched OFF (by CW)

9 Func_Overexc On Overexcitation protection is switched ON (by CW)

10 Func_Overexc Off Overexcitation protection is switched OFF (by CW)

11 HV Func_OC On

Overcurrent protection of HV side is switched ON

(by CW)

12 HV Func_OC Off

Overcurrent protection of HV side is switched OFF

(by CW)

13 MV Func_OC On

Overcurrent protection of MV side is switched ON

(by CW)

14 MV Func_OC Off

Overcurrent protection of MV side is switched OFF

(by CW)

15 LV Func_OC On

Overcurrent protection of LV side is switched ON (by

CW)

16 LV Func_OC Off

Overcurrent protection of LV side is switched OFF

(by CW)

17 HV Func_EF On

Earth fault protection of HV side is switched ON (by

CW)

18 HV Func_EF Off

Earth fault protection of HV side is switched OFF (by

CW)

19 MV Func_EF On

Earth fault protection of MV side is switched ON (by

CW)

20 MV Func_EF Off

Earth fault protection of MV side is switched OFF

(by CW)

21 LV Func_EF On

Earth fault protection of LV side is switched ON (by

CW)

Chapter 20 Appendix

294


22 LV Func_EF Off

Earth fault protection of LV side is switched OFF (by

CW)

23 HV Func_NOC On NOC protection of HV side is switched ON (by CW)

24 HV Func_NOC Off NOC protection of HV side is switched OFF (by CW)

25 MV Func_NOC On NOC protection of MV side is switched ON (by CW)

26 MV Func_NOC Off NOC protection of MV side is switched OFF (by CW)

27 LV Func_NOC On NOC protection of LV side is switched ON (by CW)

28 LV Func_NOC Off NOC protection of LV side is switched OFF (by CW)

29 HV Func_Therm On

HV thermal overload protection is switched ON (by

CW)

30 HV Func_Therm Off

HV thermal overload protection is switched OFF (by

CW)

31 MV Func_Therm On

MV thermal overload protection is switched ON (by

CW)

32 MV Func_Therm Off

MV thermal overload protection is switched OFF (by

CW)

33 HV Func_OL On HV overload protection is switched ON (by CW)

34 HV Func_OL Off HV overload protection is switched OFF (by CW)

35 MV Func_OL On MV overload protection is switched ON (by CW)

36 MV Func_OL Off MV overload protection is switched OFF (by CW)

37 LV Func_OL On LV overload protection is switched ON (by CW)

38 LV Func_OL Off LV overload protection is switched OFF (by CW)

39 HV Func_OV On HV overvoltage protection is switched ON (by CW)

40 HV Func_OV Off HV overvoltage protection is switched OFF (by CW)

41 MV Func_OV On MV overvoltage protection is switched ON (by CW)

42 MV Func_OV Off MV overvoltage protection is switched OFF (by CW)

43 HV Func_DZ On HV DZ function on

44 HV Func_DZ Off HV DZ function off

45 MV Func_DZ On MV DZ function on

46 MV Func_DZ Off MV DZ function off

47 LV Func_DZ On LV DZ function on

48 LV Func_DZ Off LV DZ function off

49 HV Func_STUB On HV STUB function on

50 HV Func_STUB Off HV STUB function Off

51 MV Func_STUB On MV STUB function on

52 MV Func_STUB Off MV STUB function Off

53 LV Func_STUB On LV STUB function on

54 LV Func_STUB Off LV STUB function Off

Chapter 20 Appendix

295


55 HV Func_PD On HV poles discordance function on

56 HV Func_PD Off HV poles discordance function off

57 MV Func_PD On MV poles discordance function on

58 MV Func_PD Off MV poles discordance function off

59 HV Func_VT On HV VT failure supervision function on

60 HV Func_VT Off HV VT failure supervision function off

61 MV Func_VT On MV VT failure supervision function on

62 MV Func_VT Off MV VT failure supervision function off

63 LV Func_VT On LV VT failure supervision function on

64 LV Func_VT Off LV VT failure supervision function off

3 Time inverse characteristic

3.1 11 kinds of IEC and ANSI inverse time characteristic curves

In the setting, if the curve number is set for inverse time characteristic, which

is corresponding to the characteristic curve in the following tabel. Both IEC

and ANSI based standard curves are available.

Table 176 11 kinds of IEC and ANSI inverse time characteristic

Curves No. IDMTL Curves Parameter A Parameter P Parameter B

1 IEC INV. 0.14 0.02 0

2 IEC VERY INV. 13.5 1.0 0

3 IEC EXTERMELY INV. 80.0 2.0 0

4 IEC LONG INV. 120.0 1.0 0

5 ANSI INV. 8.9341 2.0938 0.17966

6 ANSI SHORT INV. 0.2663 1.2969 0.03393

7 ANSI LONG INV. 5.6143 1 2.18592

8 ANSI MODERATELY 0.0103 0.02 0.0228

Chapter 20 Appendix

296

INV.

9 ANSI VERY INV. 3.922 2.0 0.0982

10 ANSI EXTERMELY INV. 5.64 2.0 0.02434

11 ANSI DEFINITE INV. 0.4797 1.5625 0.21359

3.2 User defined characteristic

For the inverse time characteristic, also can be set as user defined

characteristic if the setting is set to 12.

K

Equation 39

where:

A: Time factor for inverse time stage

B: Delay time for inverse time stage

P: index for inverse time stage

K: Set time multiplier for step n

4 CT Requirement

4.1 Overview

In practice, the conventional magnetic- core current transformer (hereinafter

as referred CT) is not able to transform the current signal accurately in whole

fault period of all possible faults because of manufactured cost and installa-

tion space limited. CT Saturation will cause distortion of the current signal

and can result in a failure to operate or cause unwanted operations of some

functions. Although more and more protection IEDs have been designed to

permit CT saturation with maintained correct operation, the performance of

protection IED is still depended on the correct selection of CT.

4.2 Current transformer classification

The conventional CTs are usually manufactured in accordance with the

standard, IEC 60044, ANSI / IEEE C57.13, ANSI / IEEE C37.110 or other

Chapter 20 Appendix

297

comparable standards, which CTs are specified in different protection class.

Currently, the CT for protection are classified according to functional per-

formance as follows:

Class P CT

Accuracy limit defined by composite error with steady symmetric primary

current. No limit for remanent flux.

Class PR CT

CT with limited remanence factor for which, in some cased, a value of the

secondary loop time constant and/or a limiting value of the winding re-

sistance may also be specified.

Class PX CT

Low leakage reactance for which knowledge of the transformer second-

ary excitation characteristic, secondary winding resistance, secondary

burden resistance and turns ratio is sufficient to assess its performance

in relation to the protective relay system with which it is to be used.

Class TPS CT

Low leakage flux current transient transformer for which performance is

defined by the secondary excitation characteristics and turns ratio error

limits. No limit for remanent flux

Class TPX CT

Accuracy limit defined by peak instantaneous error during specified tran-

sient duty cycle. No limit for remanent flux.

Class TPY CT

Accuracy limit defined by peak instantaneous error during specified tran-

sient duty cycle. Remanent flux not to exceed 10% of the saturation flux..

Class TPZ CT

Accuracy limit defined by peak instantaneous alternating current com-

ponent error during single energization with maximum d.c. offset at

specified secondary loop time constant. No requirements for d.c. com-

ponent error limit. Remanent flux to be practically negligible.

TPE class CT (TPE represents transient protection and electronic type

CT)

4.3 Abbreviations (according to IEC 60044-1, -6, as defined)

Chapter 20 Appendix

298

Abbrev. Description

Esl Rated secondary limiting e.m.f

Eal Rated equivalent limiting secondary e.m.f

Ek Rated knee point e.m.f

Uk Knee point voltage (r.m.s.)

Kalf Accuracy limit factor

Kssc Rated symmetrical short-circuit current factor

K’ssc

K”ssc

Effective symmetrical short-circuit current factor

based on different Ipcf

Kpcf Protective checking factor

Ks Specified transient factor

Kx Dimensioning factor

Ktd Transient dimensioning factor

Ipn Rated primary current

Isn Rated secondary current

Ipsc Rated primary short-circuit current

Ipcf protective checking current

Isscmax Maximum symmetrical short-circuit current

Rct Secondary winding d.c. resistance at 75 °C /

167 °F (or other specified temperature)

Rb Rated resistive burden

R’b = Rlead + Rrelay = actual connected resistive

burden

Rs Total resistance of the secondary circuit, inclu-

sive of the secondary winding resistance cor-

rected to 75℃, unless otherwise specified, and

inclusive of all external burden connected.

Rlead Wire loop resistance

Zbn Rated relay burden

Zb Actual relay burden

Tp Specified primary time constant

Ts Secondary loop time constant

4.4 General current transformer requirements

4.4.1 Protective checking current

The current error of CT should be within the accuracy limit required at speci-

fied fault current.

To verify the CT accuracy performance, Ipcf, primary protective checking

current, should be chose properly and carefully.

Chapter 20 Appendix

299

For different protections, Ipcf is the selected fault current in proper fault po-

sition of the corresponding fault, which will flow through the verified CT.

To guarantee the reliability of protection relay, Ipcf should be the maximum

fault current at internal fault. E.g. maximum primary three phase short-circuit

fault current or single phase earth fault current depended on system se-

quence impedance, in different positions.

Moreover, to guarantee the security of protection relay, Ipcf should be the

maximum fault current at external fault.

Last but not least, Ipcf calculation should be based on the future possible

system power capacity

Kpcf, protective checking factor, is always used to verified the CT perfor-

mance

To reduce the influence of transient state, Kalf, Accuracy limit factor of CT,

should be larger than the following requirement

Ks, Specified transient factor, should be decided based on actual operation

state and operation experiences by user.

4.4.2 CT class

The selected CT should guarantee that the error is within the required ac-

curacy limit at steady symmetric short circuit current. The influence of short

circuit current DC component and remanence should be considered, based

on extent of system transient influence, protection function characteristic,

consequence of transient saturation and actual operating experience. To ful-

fill the requirement on a specified time to saturation, the rated equivalent

secondary e.m.f of CTs must higher than the required maximum equivalent

secondary e.m.f that is calculated based on actual application.

For the CTs applied to transmission line protection, transformer differential

protection with 330kV voltage level and above, and 300MW and above gen-

Chapter 20 Appendix

300

erator-transformer set differential protection, the power system time constant

is so large that the CT is easy to saturate severely due to system transient

state. To prevent the CT from saturation at actual duty cycle, TP class CT is

preferred.

For TPS class CT, Eal (rated equivalent secondary limiting e.m.f) is generally

determined as follows:

Where

Ks: Specified transient factor

Kssc: Rated symmetrical short-circuit current factor

For TPX, TPY and TPZ class CT, Eal (rated equivalent secondary limiting

e.m.f) is generally determined as follows:

Where

Ktd: Rated transient dimensioning factor

Considering at short circuit current with 100% offset

For C-t-O duty cycle,

t: duration of one duty cycle;

For C-t’-O-tfr-C-t”-O duty cycle,

t’: duration of first duty cycle;

t”: duration of second duty cycle;

tfr: duration between two duty cycle;

For the CTs applied to 110 - 220kV voltage level transmission line protection,

110 - 220kV voltage level transformer differential protection, 100-200MW

generator-transformer set differential protection, and large capacity motor

differential protection, the influence of system transient state to CT is so less

that the CT selection is based on system steady fault state mainly, and leave

Chapter 20 Appendix

301

proper margin to tolerate the negative effect of possible transient state.

Therefore, P, PR, PX class CT can be always applied.

For P class and PR class CT, Esl (the rated secondary limited e.m.f) is gen-

erally determined as follows:

Kalf: Accuracy limit factor

For PX class CT, Ek (rated knee point e.m.f) is generally determined as fol-

lows:

Kx: Demensioning factor

For the CTs applied to protection for110kV voltage level and below system,

the CT should be selected based on system steady fault state condition. P

class CT is always applied.

4.4.3 Accuracy class

The CT accuracy class should guarantee that the protection relay applied is

able to operate correctly even at a very sensitive setting, e.g. for a sensitive

residual overcurrent protection. Generally, the current transformer should

have an accuracy class, which have an current error at rated primary current,

that is less than ±1% (e.g. class 5P).

If current transformers with less accuracy are used it is advisable to check

the actual unwanted residual current during the commissioning.

4.4.4 Ratio of CT

The current transformer ratio is mainly selected based on power system data

like e.g. maximum load. However, it should be verified that the current to the

protection is higher than the minimum operating value for all faults that are to

be detected with the selected CT ratio. The minimum operating current is

different for different functions and settable normally. So each function

should be checked separately.

4.4.5 Rated secondary current

There are 2 standard rated secondary currents, 1A or 5A. Generally, 1 A

Chapter 20 Appendix

302

should be preferred, particularly in HV and EHV stations, to reduce the bur-

den of the CT secondary circuit. Because 5A rated CTs, i.e. I2R is 25x com-

pared to only 1x for a 1A CT. However, in some cases to reduce the CT

secondary circuit open voltage, 5A can be applied.

4.4.6 Secondary burden

Too high flux will result in CT saturation. The secondary e.m.f is directly

proportional to linked flux. To feed rated secondary current, CT need to

generate enough secondary e.m.f to feed the secondary burden. Conse-

quently, Higher secondary burden, need Higher secondary e.m.f, and then

closer to saturation. So the actual secondary burden R’b must be less than

the rated secondary burden Rb of applied CT, presented

Rb > R’b

The CT actual secondary burden R’b consists of wiring loop resistance

Rlead and the actual relay burdens Zb in whole secondary circuit, which is

calculated by following equation

R’b = Rlead + Zb

The rated relay burden, Zbn, is calculated as below:

Where

Sr: the burden of IED current input channel per phase, in VA;

For earth faults, the loop includes both phase and neutral wire, normally

twice the resistance of the single secondary wire. For three-phase faults the

neutral current is zero and it is just necessary to consider the resistance up to

the point where the phase wires are connected to the common neutral wire.

The most common practice is to use four wires secondary cables so it nor-

mally is sufficient to consider just a single secondary wire for the three-phase

case.

In isolated or high impedance earthed systems the phase-to-earth fault is not

the considered dimensioning case and therefore the resistance of the single

secondary wire always can be used in the calculation, for this case.

4.5 Rated equivalent secondary e.m.f requirements

To guarantee correct operation, the current transformers (CTs) must be able

to correctly reproduce the current for a minimum time before the CT will

begin to saturate.

Chapter 20 Appendix

303

4.5.1 Transformer differential protection

It is recommended that the CT of each side could be same class and with

same characteristic to guarantee the protection sensitivity.

For the CTs applied to 330kV voltage level and above step-down transformer,

TPY class CT is preferred for each side.

For the CTs of high voltage side and middle voltage side, Eal should be ver-

ified at external fault C-O-C-O duty cycle.

For the CT of low voltage side in delta connection, Eal should be verified at

external three phase short circuit fault C-O duty cycle.

Eal must meet the requirement based on following equations:

Where

K’td: Recommended transient dimensioning factor for verification, 3

recommended

For 220kV voltage level and below transformer differential protection, P

Class, PR class and PX class is able to be used. Because the system time

constant is less relatively, and then DC component is less, the probability of

CT saturation due to through fault current at external fault is reduced more

and more.

For P Class, PR class CT, Esl can be verified as below:

Where

Ks: Specified transient factor, 2 recommended

For PX class CT, Ek can be verified as below:

Where

Ks: Specified transient factor, 2 recommended

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CSC-326 Transformer Protection IED Technical …...Preface Purpose of this manual This manual describes the functions, operation, installation, and placing into service of device CSC-326