CS64 Lecture15 SequentialLogic · Sequential Logic • Combinatorial Logic – Combining multiple logic blocks – The output is a function only of the present inputs – There is

SequentialLogic

CS64:ComputerOrganizationandDesignLogicLecture#15

ZiadMatni

Dept.ofComputerScience,UCSB

LectureOutline

•  SequentialLogic

•  S-RLatch

•  D-Latch

•  D-FlipFlop

•  Reviewingwhat’sneededforLab8

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AbstractSchematicoftheMIPSCPU

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SequentialLogic

•  CombinatorialLogic–  Combiningmultiplelogicblocks–  Theoutputisafunctiononlyofthepresentinputs–  Thereisnomemoryofpast“states”

•  SequentialLogic–  Combiningmultiplelogicblocks–  Theoutputisafunctionofbothpresentandpastinputs–  Thereexistsamemoryofpast“states”

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TheS-RLatch

•  Onlyinvolves2NORs

•  Theoutputsarefed-backtotheinputs

•  Theresultisthattheoutputstate(eithera1ora0)ismaintainedeveniftheinputchanges!

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HowaLatchWorks•  NotethatifoneNORinputis0,theoutput

becomestheinverseoftheotherinput

•  So,ifoutputQalreadyexistsandifS=0,R=0,thenQwillremainatwhateveritwasbefore!(holdoutputstate)

•  IfS=0,R=1,thenQbecomes0(resetoutput)

•  IfS=1,R=0,thenQbecomes1(setoutput)

•  MakingS=1,R=1isnotallowed(undeterminedoutput)3/8/18 6

S R Q0 Comment0 0 Q* Holdoutput0 1 0 Resetoutput1 0 1 Setoutput1 1 X Undetermined

Consequences?

•  AslongasS=0andR=0,thecircuitoutputholdsmemoryofitspriorvalue(state)

•  Tochangetheoutput,justmakeS=1(butalsoR=0)tomaketheoutput1(set)ORS=0(butalsoR=1)tomaketheoutput0(reset)

•  JustavoidS=1,R=1…

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AboutthatS=1,R=1Case…

•  WhatifweavoideditonpurposebymakingR=NOT(S)?– Where’stheproblem?

•  This,byitself,precludesacasewhenR=S=0–  You’dneedthatifyouwantto

preservethepreviousoutputstate!

•  Solution:theclockedlatchandtheflip-flop

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S/R’

S R Q0 Comment

0 0 Q* Holdoutput

0 1 0 Resetoutput

1 0 1 Setoutput

1 1 X Undetermined

Addingan“Enable”Input:TheGatedSRLatch

•  Createawayto“gate”theDinput–  Dinputgoesthroughonlyifan

“enableinput”(E)is1–  IfEis0,thenholdthestateofthe

previousoutputs

•  So,thetruthtablewouldlooklike:

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S R E Q0 CommentX X 0 Q* Holdoutput0 1 1 0 Resetoutput1 0 1 1 Setoutput

TheGatedDLatch•  ForceSandRinputs

toalwaysbeoppositeofeachother–  Makethemthesameas

aninputD,whereD=Rand!D=S.

•  Createawayto“gate”theDinput–  Dinputgoesthrough

onlyifanenableinput(E)is1–  IfEis0,thenholdthestateofthe

previousoutputs

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DE

SR

QQ

D E Q0 CommentX 0 Q* Holdoutput0 1 0 Resetoutput1 1 1 Setoutput

TheClockedDLatch•  Ifyouapplyaclockon

inputE,yougetaclockedDlatch.

•  Aclockisaninputthatgoes1then0,then1againinasettimeperiod

•  WhenCLKis0,bothSandRinputstothelatchare0too,sotheQholdsitsvalue(Q=Q0)

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DCLK

SR

•  WhenCLKis1,thenifD=1,thenQ=1,butifD=0,thenQ=0

ClockedDLatchasSampler

•  Thisclockedlatchcanbeusedasa“programmable”memorydevicethat“samples”aninputonaregularbasis

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DCLK

QQ

TheClockedLatchByAnyOtherName…

•  Observinginputandoutput“waveforms”

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DCLK

SR

DClockedLatch

DCLK

QQ

TheJoysofSampling…

•  Samplingdatainaperiodicwayisadvantageous–  Icanstartdesigningmorecomplexcircuitsthatcanhelpmedosynchronouslogicalfunctions•  Synchronous:in-time

•  VeryusefulinpipeliningdesignsusedinCPUs–  Pipelining:atechniquethatallowsCPUstoexecuteinstructionsmoreefficiently–inparallel

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Instructionfetch,decode,execute,memoryaccess,registerwrite

TheMostEfficientWaytoSampleInputs

•  Insteadofsamplingtheinputtothelatchusingaleveloftheclock…– Thatis,whentheclockis“1”(or“0”)

•  …sampletheinputattheedgeoftheclock– Thatis,whentheclockistransitioningfrom0à1,calledarisingorpositiveedge(oritcouldbedonefrom1à0, thefallingedgea.k.anegativeedge)

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AnImprovementontheLatch:TheDFlip-Flop

Don’tworryaboutthecircuitimplementationdetails,butunderstandtheuse!TheDFlip-Floponlychangestheoutput(Q)intotheinput(D)atthepositiveedge(the0à1transition)oftheclock

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DFlip-Flop(D-FF)

D>CLK

QQ

DGatedLatch

DCLK

QQ

Asopposedto:

Notethe(slight)differenceinthe2symbols…

TheD-FF

•  Whentheinputclockedgeisrising,theinput(D)iscapturedandplacedontheoutput(Q)–  Risingedgea.k.apositiveedgeFF–  SomeFFarenegativeedgeFF(captureonthefallingedge)

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Latchesvs.FFs•  Latchescapturedataonanentire1or0oftheclock•  FFscapturedataontheedgeoftheclock

–  Thisexampleshowsthepositive(0à1)edgeused

Latchout

FFout

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FFsgiveoutless“glitchy”outputs

PopularUsesforD-FFs

•  Counter

•  Serial-to-Parallelconverter

•  Digitaldelayline

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Again,don’tworryaboutthecircuitimplementationdetails,butunderstandtheuses!

Lab8

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RegisterObjectforLab8

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I/OName I/ODescription

R0Thefirstregistertoread,asasinglebit.If0,thenreg0shouldberead.If1,thenreg1shouldberead.

R1Thesecondregistertoread,asasinglebit.If0,thenreg0shouldberead.If1,thenreg1shouldberead.

WR

“WriteRegister”.Specifieswhichregistertowriteto.If0,thenreg0shouldbewrittento.If1,thenreg1shouldbewrittento.

WThedatathatshouldbewrittentotheregisterspecifiedbyWR.Thisisasinglebit.

WE

“WriteEnable”.If1,thenwewillwritetoaregister.If0,thenwewillnotwritetoaregister.NotethatifWE=0,thentheinputstoWRandWareeffectivelyignored.

O1

Valueofthefirstregisterread.Asdescribedpreviously,thisdependsonwhichregisterwasselectedtoberead,viaR0.

O2

Valueofthesecondregisterread.Asdescribedpreviously,thisdependsonwhichregisterwasselectedtoberead,viaR1.

HintsforTask2

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01S

01S

O1O2

GatedDLatch

DE

QQ

GatedDLatch

DE

QQ

LogicGates

MemoryInterfaceObjectforLab8

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I/OName I/ODescription

A0 Bit0oftheaddress(LSB)

A1 Bit1oftheaddress(MSB)

OE

“OutputEnable”.If1,thenthevalueattheaddressspecifiedbyA0andA1willberead,andsenttotheoutputlineO.If0,thenthememorywillnotbeaccessed,andthevaluesenttotheoutputlineisunspecified(couldbeeither0or1,inanunpredictablefashion).

W Thevaluetowritetomemory.

WE

“WriteEnable”.If1,thenthevaluesentintoWwillbewrittentomemoryattheaddressspecifiedbyA0andA1.If0,thennomemorywriteoccurs(thevaluesenttoWwillbeignored).

O Thevaluereadfrommemory(orunspecifiedifOE=0).

Task3:BuildaMock-CPU!

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Actually, just a small instruction decoder and executor…

OP1 OP0 B0 B1 B2 Human-readableEncoding Description

0 0 0 0 0 xorreg0,reg0,reg0 ComputetheXORofthecontentsofreg0withthecontentsofreg0,storingtheresultinreg0.

0 1 1 0 1 norreg1,reg0,reg1 ComputetheNORofthecontentsofreg0withthecontentsofreg1,storingtheresultinreg1.

1 0 1 0 1 loadreg1,01 Copythebitstoredataddress01(decimal1)intoregisterreg1.

1 1 0 1 0 storereg0,10 Storethecontentsofreg0ataddress10(decimal2)1 1 1 1 1 storereg1,11 Storethecontentsofreg1ataddress11(decimal3)

ThesesaysomethingaboutwhichoperationisbeingdoneThesesaysomethingaboutwhichregistersareused

HintsforTask3•  Designthefinalcircuitinpieces:

–  Onepieceforeachofthe3typesofinstruction:load,store,XOR/NOR

•  Forexample,thestoretask:–  Ifanoutputisn’tused,tieittoapermanent“0”(i.e.ground)–  Ifaninputisn’tused,thenyoucanuse“X”(don’tcare)onit

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WhatregistersamIusing?Whichinstructionbitsgowhere?

WhatcontrolsshouldIuse?Whatvaluesshouldtheybe?

HowdoIbestconnecttheregisterstothememoryinterface?Again,askyourselfifsomeoftheinputshereshouldbeop-codebits.

Istheoutputevenusedinthis“store”task?

TyingInAllThePieces(Task3)

•  Nowseehowtheycanallfittogether–  Youwillhave1registerblock+1memoryinterface–  Youwon’tneedtouseanyadditionallatcheshere–  Youwillneedtousemuxesandregularlogic(andthesimpleALUyoudesignedearlier–seelabinstructionsformoredetails)

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YourToDos

•  Lab#7isdueendofdayFriday

•  Lab#8isdueNEXTweekFriday

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Documents

CS64 Lecture15 SequentialLogic · Sequential Logic • Combinatorial Logic – Combining multiple logic blocks – The output is a function only of the present inputs – There is