B.E./B.Tech.

St. Xavier’s Catholic College of Engineering, Chunkankadai, Nagercoil – 629 003.

Second Semester

Information Technology

CS6201 - Digital Principles & System Design

First Internal Assessment Test, February 2015

Time: 1½ Hours Maximum: 50 marks

ANSWER ALL QUESTIONS

PART – A (09 x 02 = 18 marks)1. State Duality principle?2. Draw the logic diagram for half adder.3. Perform 9’s and 10’s compliment subtraction between 18 and –24?4. Draw the logic diagram for the Boolean expression ((A + B) C)′D using NAND gates.5. Realize XOR gate using only 4 NAND gates?6. Convert (1001010.1101001)2 to base 16 and (23 1.07)8 to base 10?7. What are the limitations of Karnaugh map?8. State and prove Consensus theorem? 9. Design a half subtractor circuit.?

PART – B (02 x 16 = 32 marks)10. (a) Simplify the following Boolean function using Quine-McClusky method F = (A, B, C,D, E)= Σm (0, 1, 3, 7, 13, 14, 21, 26, 8)+ Σd (2, 5, 9, 11, 17, 24). (16)

Or10. (b) i) Prove that ( AB + C + D )(C ′ + D )(C ′ + D + E ) = ABC + D . (4) ii) Simplify the given Boolean function in POS form using K-map and draw the

logic diagram using only NOR gates. F(A, B, C,D)= Σm (0,1, 4,7,8,10,12, 15)+ Σd (2, 6,11,14). (12)

11. a. (i) Explain the gray code to binary converter with the necessary diagram. (10)

(ii) Find the dual and complement of the following Boolean expression.

xyz’+x’yz+z(xy+w). (6)

Or11. b. Design a full adder and subtractor using NAND and NOR Gates (16)

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