CS 61C: Great Ideas in Computer Architecture …cs61c/fa16/lec/11/L11.pdfMIPS Datapath Summary CS 61c Lecture 11: Datapath 47 Phase Action Time Slot Hardware Used 1 Fetch instruction

CS61C:GreatIdeasinComputerArchitecture

Lecture11:Datapath

BernhardBoser&RandyKatz

http://inst.eecs.berkeley.edu/~cs61c

Agenda

• MIPSDatapath− add

§ instruction§ registertransferlevel§ circuit§ timing§ control

− and,…− addi,...− beq,…− j− lw,sw

• AndinConclusion,...

CS61c Lecture11:Datapath 2

Processor


Processor

Control

Datapath

PC

Registers

Arithmetic&LogicUnit(ALU)

Memory

Bytes

Enable?Read/Write

Address

WriteData

ReadData

Processor-Memory Interface

Program

Data

Datapath: addu - Specs

• GreenCard• MIPSISAdocumentation


DatapathDesign:addu• Instruction

• Effect- “Registertransferlevel,RTL”− PC ← PC + 4− R[$rd] ← R[$rs] + R[$rt]


Type 31… format(bits) …0

R OpCode(6) rs (5) rt (5) rd (5) shmt (5) funct (6)

0x0 rs rt rd 0 0x21

Circuit:addu

• Registertransferlevel,RTL− PC ← PC + 4− R[$rd] ← R[$rs] + R[$rt]




0x0 rs rt rd 0 0x21

Timing:addu


Controller


Controller

ControlSignals

• cALU− correctALUoperation:add,sub,or,…

• cRegW− Assert(1)towritetodest register− Registersunchangedif0

• Determinedby− OpCode− Func code(R-typeinstructions)


Control:addu


Control:addu

• Control− DeterminedfromOpCode andFunc

• Wewilldesignthecontrollerlater− Fornow,let’sjustremembertherequiredsignals


OpCode Func cALU cRegW

0x0 0x21 add 1

Datapathforaddu - Summary

• Registertransferlevel,RTL− PC ← PC + 4− R[$rd] ← R[$rs] + R[$rt]




0x0 rs rt rd 0 0x24


0x0 0x21 add 1

The61CMysteryChannelPresents…


The mystery ofadd and addu

Detective61Ccheckstheevidence

Whichofthefollowingstatementsiscorrect?


A B Cin S Cout

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Smoking Gunaka 1-bitaddertruthtable

Answer Statement

A TTisforsigned addition

B TT isforunsigned addition

C TTisincorrect,itssolepurpose istohidethecrime

D For32-bitthisisirrelevant,anyway

E TTisforsigned and unsignedaddition, since(Lecture1)withtwo’scomplement representationtheyaretheSAME

SinisterMotives• What’sthepurposeofhavingtwoinstructions,add addu?

− Midterm“trick”questions?• Overflowdiffersforsigned andunsigned!

− Lecture1• add

− Raisesexceptiononoverflow,assumingoperandsaretwo’scomplementsigned

• addu− Ignoresoverflow− Itcanthereforebeusedforsigned ANDunsignedtwo’scomplementnumbers

− Despiteitsname!• Whataboutexceptionsonunsignedoverflow?

− DesignyourownMIPS!− Nowyouknowwhyyouneedtotake61C!

CS61c 15

Whenuseadd, addu?

• Address(pointer)arithmetic:− signedoverflowmakesnosense− alwaysuseaddu

• Unsignedints− addu−won’treportoverflow!

• Signedints− add ifyoucareaboutoverflow

§ e.g.Fortran− addu ifyoudon’tcareaboutoverflow

§ e.g.C


So…

• Sincein61CweprograminC−wealwaysuseaddu− andneveradd?


You Got It!

Andafterthisinterlude…

•61Creturnsto−rigorous−alwayscrystalclear−andneverconfusing−engineeringfacts!

•Nomoremystery!


Agenda






Datapathforand

• Registertransferlevel,RTL− PC ← PC + 4− R[$rd] ← R[$rs] & R[$rt]

• Sameasadd – exceptcALU− Dittoforsub, or, xor, …



0x0 rs rt rd 0 0x24


0x0 0x24 and 1

Agenda






Datapathforaddiu

• Registertransferlevel,RTL− PC ← PC + 4− R[$rt] ← R[$rs] + sign_ext(imm)

• Updateddatapathtosupportimmediate:


I 0x9 rs (5) rt (5) immediate(16)

NewControlSignals

• cDstReg AddrDst =$rt (not$rd)• cImm ALUB=immediate(not$rt)• cSignExt Signextendimmediate


SignExtension




31… …0

31… …0

Signextension:

Nosignextension:

Controlforaddiu

Datapathforaddiu - Control



Instr OpCode Func cALU cRegW cRegDst cSignExt cImm

add 0x0 0x20 add 1 0 0 0

addi



Datapathforaddiu - Summary



Instr OpCode Func cALU cRegW cRegDst cSignExt cImm

add 0x0 0x20 add 1 0 0 0

addi 0x9 X add 1 1 1 1



YourTurn- ori

Answer OpCode Func cALU cRegW cRegDst cSignExt cImmA 0xd X or 0 1 0 1B 0xd X or 1 1 0 1C 0x0 0xd or 1 1 0 1D 0xd X ori 1 1 1 1E 0xd X or 1 1 1 1

I 0xd rs (5) rt (5) immediate(16)

YourTurn- ori

Answer OpCode Func cALU cRegW cRegDst cSignExt cImmA 0xd X or 0 1 0 1B 0xd X or 1 1 0 1C 0x0 0xd or 1 1 0 1D 0xd X ori 1 1 1 1E 0xd X or 1 1 1 1

I 0xd rs (5) rt (5) immediate(16)

GorillaTutoring


• GorillaSessions−Wednesdays7:30– 9:30pm− 405Sodaor293Cory− 10tutors− review&practicequestions

• PrivateTutoring− 2tutors− 10studentsmax− Sign-upinstructionsonPiazza

Agenda






Datapathforbeq



I 0x5 rs (5) rt (5) offset(16)

• Registertransferlevel,RTL− PC ← PC + 4

+ if (R[$rs]==R[$rt]) then signext(4*off)else 0

Controlforbeq




Instr OpCode Func Zero cALU cRegW cRegDst cSignExt cImm cBranch

addiu 0x9 X X add 1 1 1 1 0

addu 0x0 0x21 X add 1 0 0 0 0

beq

Controlforbeq





addi 0x8 X X add 1 1 1 1 0

add 0x0 0x20 X add 1 0 0 0 0

beq 0x4 X 1 sub 0 X X 0 1


Datapathforbneq







bneq 0x5

Agenda






Datapathforj



J 0x2 targetaddress(26)

• Registertransferlevel,RTL− PC[2 … 28] ← target address

jDestinationaddress



J 0x2(6) targetaddress(26)

old 31…28 27…2 1…0

PC

new 31…28 27…2 1…0

PC

Controlforj



J 0x2 targetaddress(26)

Instr OpCode Func Zero cALU cRegW cRegDst cSignExt cImm cBranch cJump

addiu 0x9 X X add 1 1 1 1 0 0

addu 0x0 0x21 X add 1 0 0 0 0 0

j 0x2 X X X 0 X X X X 1

Agenda






Datapathforlw



I 0x23 rs (5) rt (5) offset (16)

• Registertransferlevel,RTL− PC ← PC + 4− R[$rt] ← MEM[ R[$rs] + signext(offset) ]

Timingforlw


Controlforlw


Instr OpCode Func Zero cALU cRegW cRegDst cSignExt cImm cBr cJ cLW cMemW

addiu 0x9 X X add 1 1 1 1 0 0 0 0

addu 0x0 0x21 X add 1 0 0 0 0 0 0 0

j 0x2 X X X 0 X X X X 1 X 0

lw 0x23

Controlforlw



addiu 0x9 X X add 1 1 1 1 0 0 0 0

addu 0x0 0x21 X add 1 0 0 0 0 0 0 0

j 0x2 X X X 0 X X X X 1 X 0

lw 0x23 X X add 1 1 1 1 0 0 1 0

Datapathforsw



I 0x15 rs (5) rt (5) offset (16)

• Registertransferlevel,RTL− PC ← PC + 4− MEM[ R[$rs] + signext(offset) ] ← R[$rt]

Controlforsw



addiu 0x9 X X add 1 1 1 1 0 0 0 0

addu 0x0 0x21 X add 1 0 0 0 0 0 0 0

j 0x2 X X X 0 X X X X 1 X 0

lw 0x23 X X add 1 1 1 1 0 0 1 0

sw 0x2b X X add 0 X 1 1 0 0 X 1

MIPSDatapathSummary


Phase Action TimeSlot HardwareUsed1 Fetch instruction tIF InstrMemory2 Decodeinstr,readregisters tID Instr Dec, Register File3 Executeinstruction tEX ALU4 Accessdatamemory tMEM DataMemory5 Writeregister,PC tWB Register File,PC

Note:notallinstructionsareactiveinallphases

YourTurn

Answer Fewest MostA nor lwB bne swC j lwD jr lwE slt sw


Whichinstructionisactiveinthefewest/mostphases?

YourTurn

Answer Fewest MostA nor lwB bne swC j lwD jr lwE slt sw


Whichinstructionisactiveinthefewest/mostphases?

Agenda



− and,…− addi,...− beq,…− j− lw,sw− dowhile



MIPS2000,4000,MIPS61C!

int j = -1;do

// a[i] = b[i] * c[i]; …i = i+j;

while (i != 0);


Newinstructionthatupdatesi andbranches:dowhile $i, $j, label

dowhile $rt, $rs, label


• Registertransferlevel,RTL− R[$rt] = R[$rt] + R[$rs]− PC ← PC + 4

+ if (R[$rs]==R[$rt]) then signext(4*off)else 0


I 0x61c* rs (5) rt (5) offset(16)

*justreplaceoneofthelessusefulinstructions…

Controlfordowhile


Instr OpCode Zero cALU cRegW cRegDst cSignExt cImm cBr cJ cLW cMemW

dowhile 0x61c

Controlfordowhile


Instr OpCode Zero cALU cRegW cRegDst cSignExt cImm cBr cJ cLW cMemW

dowhile 0x61c 1 add 1 1 X 0 1 0 0 0

0 add 1 1 X 0 0 0 0 0

Agenda






AndinConclusion,…

• Universaldatapath− CapableofexecutingallMIPSinstructions− Notallunits(hardware)usedbyallinstructions

• 5Phasesofexecution− IF,ID,EX,MEM,WB− Notallinstructionsareactiveinallphases

• Controllerspecifieshowtoexecuteinstructions− Even“new”ones…(dowhile)


Documents

CS 61C: Great Ideas in Computer Architecture …cs61c/fa16/lec/11/L11.pdfMIPS Datapath Summary CS 61c Lecture 11: Datapath 47 Phase Action Time Slot Hardware Used 1 Fetch instruction