Cross-switched multilevel inverter using auxiliary reverse-connected voltage sources

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Published in IET Power ElectronicsReceived on 6th August 2013Revised on 31st October 2013Accepted on 7th December 2013doi: 10.1049/iet-pel.2013.0606

T Power Electron., 2014, Vol. 7, Iss. 6, pp. 1519–1526oi: 10.1049/iet-pel.2013.0606

ISSN 1755-4535

Cross-switched multilevel inverter using auxiliaryreverse-connected voltage sourcesSandirasegarane Thamizharasan1, Jeevarathinam Baskaran2, Subburam Ramkumar3,

Seenithangam Jeevananthan4

1Department of EEE, School of Engineering and Technology, Surya Group of Institutions, Vikiravandi, Villupuram, India2Department of EEE, Adhiparasakthi Engineering College, Melmaruvathur, Chennai, India3Department of EEE, RMD Engineering College, Chennai, India4Department of EEE, Pondicherry Engineering College, Puducherry, India

E-mail: [email protected]

Abstract: A new single-phase H-bridge multilevel inverter (MLI) topology constructed using auxiliary reverse-connected voltagesources along with a hybrid pulse width modulation (PWM) strategy is proposed, to extract a variable frequency variableamplitude output voltage. The principle eschews an astute philosophy to employ PWM approach only for a particular H-bridge that serves to produce the desired level while the remaining add-on modules function with the theory of fundamentalswitching. It involves the use of reduced number of switching devices for a specific number of output voltage levels incomparison with conventional MLIs. The design of the hybrid PWM suitable to power the appropriate switches add strengthto its formulation in the sense it requires only either addition or subtraction to generate the square wave modulated pulses forthe power devices in the other units other than that responsible for offering the preferred level of output voltage. TheMATLAB R2010b-based simulated performance adequately validated through experimental results foresee the emergence ofa new variety of MLIs and forge a different dimension for inverter interfaces in power control applications.

1 Introduction

Multilevel inverters (MLIs) endeavour to produce high-qualityoutput voltage with minimum filter requirements over theconventional two-level inverters, to make them suitable forhigh power and high voltage industrial applications.Pulse-width modulated (PWM) MLIs are considered to be animperative replacement for the conventional two-levelinverters as they are capable of operating with nearlysinusoidal current waveforms and higher stepped outputvoltages [1–3]. The MLIs claim an inimitable range of use inmedium voltage drive applications to ascertain its place overtraditional inverters [4–6].The cascaded H-bridge (CHB) MLI uses a string of

H-bridge inverters in each phase leg. Each inverter includesa three-phase uncontrolled six-pulse rectifier at the inputside with a capacitive filter. It induces current harmonics atthe input of each inverter cell. These harmonics are reducedby introducing phase-shifted secondary in the inputtransformer, resulting in a more complicated constructionand higher cost. Years later, hybrid topologies in whicheach inverter phase leg is structured by cascading diodeclamped or flying capacitor inverter and CHB MLI toproduce any number of voltage levels are evolved [7–9]. The disadvantage of hybrid structure is the presence ofnon-isolated dc sourced H-bridge topologies thatsynthesise unbalanced voltage levels in their respectiveoutput stages.

Although MLI offers several distinct advantages, itsapplication is limited due to power rating constraints. In thisview, an attempt is made by paralleling two diode-clampedinverters through an inter-phase reactor in order toovercome power rating constraints [10]. Several efforts arebeing carried out to increase the number of voltage levelswith reduced number of switching devices and one suchtopology is the new single-phase MLI topology [11] inwhich the number of voltage levels is increased by using asplit-wound coupled inductor within each inverter leg. Themain advantage of this topology is to provide low value ofhigh-frequency current ripple in the load circuit and reducedshoot-through fault against dc-rails. A new symmetricalcascaded MLI is devised [12] in which cascade connectionof sub-cells is achieved using two dc sources and fourswitches through an H-bridge inverter. Despite the fact thatthis topology enjoys high modularity and the skill to increasethe number of voltage levels with reduced total harmonicdistortion, it suffers from the drawback that the devices in theH-bridge need to withstand high blocking voltages.An isolated cascaded MLI, employing low-frequency

three-phase transformers and a single dc input power sourceand avails the use of lower number of power devices, hasbeen suggested in [13–15]. The higher implementation costhas been related to the fact that the number oflow-frequency transformers increases with simultaneousincrease in the number of voltage levels [13–15]. A dualstructure-based MLI that consists of an H-bridge inverter to

1519& The Institution of Engineering and Technology 2014

Fig. 1 Generalised topology

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switch the dc voltages sources in series and parallel andanother H-bridge inverter module for increasing the voltagelevel has been presented in [16, 17]. A symmetrical cascadeMLI composed of series connection of several sub-MLIunits has been shown to offer same number of outputvoltage levels with reduced power devices and power losseswhen compared to CHB MLI [18, 19].A new transformer-less MLI topology based on packed U

cell arrangement consisting of two power switches and onecapacitor has been proposed [20]. A new topology with areversing voltage component that requires fewercomponents compared to existing inverters has beenexplained [21]. Two new topologies based on multileveldc-link (MLDCL) concept that utilises fewer powercomponents and dc sources [22–24] and overcomes thedisadvantage of increased clamping diodes and highervoltage blocking capability for the switching devices whileincreasing number of levels have been explored.However, MLI technologies still require renewed

perspectives and invite continued attention to address thechallenges in the direction to extricate sinusoidal currentand voltage waveforms and reduce the number of switchingdevices in the conduction path.

Fig. 2 Basic auxiliary inverter cell

2 Proposed topology

The primary focus echoes the creation of a newMLI topologythat shares the voltage stress across the power devices whileincreasing number of levels derived using auxiliaryreverse-connected voltage sources and H-bridge inverter.The generalised structure of the new MLI topology seen inFig. 1 is derived using auxiliary reverse-connected voltagesources and H-bridge inverter. The structure consists of anisolated H-bridge inverter comprising a voltage source (Vo)whose magnitude is equal to the minimum step voltage andan auxiliary dual source inverter comprising complementarypaired voltage sources (V1 to Vn) connected through fewpower devices. Although the switches (S1–S4) in Fig. 1connect Vo with voltage sources (V1 to Vn) for leveladdition and subtraction, the switches (Sa1 to San) and (Sa1′to San′) are complementary switches and are used forcascading the voltage sources (V1–Vn). These switches


provide a bypass when the voltage sources (V1–Vn) are notrequired.If ‘n’ is the number of dc voltage sources used in the

proposed topology, then the number of output voltagelevels extracted for a given ‘n’ and number of switchesrequired is given by ((4 × n)−1) and ((2 × n) + 4),respectively. The structural formation in each conductionsequence allows the voltage to be shared and therebyreduce the blocking voltage.A basic auxiliary inverter cell shown in Fig. 2 consists of

two dc sources (V1 and V2) with six switches. The crux ofthe formulation needs only a fewer number of suchauxiliary inverter cells to be connected with the isolatedH-bridge module to produce any possible value of Vo. Thedc-link structure is represented by a fixed dc source and theoperating mode for level 1 ( ± Vo) and level 6 ( ± (V1 + V2))of a 15-level inverter with V0:V1:V2 = (1:2:4) V along withpositive and negative half cycles are explained pictoriallythrough Figs. 3 and 4.It is seen from Fig. 3 that the devices Sa3′, Sa2′, Sa1′ in the

auxiliary inverter and S4, S3 in the H-bridge inverter arerequired to conduct to extract the first level of the outputvoltage and goes through a similar sequence for otherlevels. The pattern of the output voltage depicted in Figs. 5and 6 clearly shows the devices that conduct for the variouslevels of the output voltage. The number of conductingswitches in the current path also plays an important role inthe overall efficiency of inverter. For example, a 15-levelCHB MLI has 12 switches, and half of them conduct theinverter current in each instance. However, the numbers ofswitching devices that conduct in the proposed topology areonly five for all the levels, while three of them are switchedat low-frequency in this approach.

IET Power Electron., 2014, Vol. 7, Iss. 6, pp. 1519–1526doi: 10.1049/iet-pel.2013.0606

Fig. 4 Operating mode-level 6 ( ± (V1 + V2))

Fig. 5 Modulation method

Fig. 3 Operating mode-level 1 ( ± Vo)

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Table 1 Detailed comparison of power components required between the proposed and other topologies

MLI structure components Cascaded H-bridge Diode clamped Flying capacitor Series parallel switched MLDCLI Proposed

main switches 2(m−1) 2(m−1) 2(m−1) (3m−1)/2 (m + 3)bypass diodes — — — 1 —clamping diodes — 2(m−3) — — —DC split capacitors — (m−1)/2 (m−1)/2 — —clamping capacitors — — (2m−6)/2 — —DC sources (m−1)/2 1 1 (m−1)/2 (m−1)/2

Fig. 6 Synthesis of output voltage waveform

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The proposed inverter produces m = [(2 × 2n)–1] levels andutilises ((6 × k) + 4) power switches, where ‘m’ is the numberof levels in the output voltage and ‘k’ is the number ofauxiliary inverter circuits connected in series. Although theentries in Table 1 comprehensively summarise the numberof components required for different types of MLIs toestablish the merits of the new topology, that in Table 2forays the relation between the number of dc sources (n) andnumber of auxiliary inverters (k) in the proposed topology.Table 3 includes the number of power devices required forsymmetrical and asymmetrical modes of this structure.

Table 2 Relation between ‘n’ and ‘k’ in the proposed inverter(n = (2 × k) + 1)

Parameters Symmetrical Asymmetrical

Binary Ternary

maximum outputvoltage

Vdc × ([(4 × k) +3]−1)/2

Vdc × ([(8 × k)+ 3]−1)/2

Vdc ×([(12 × k) +3]−1)/2

number of voltagelevels

[(4 × k) + 3] [(4 × k) + 3] [(4 × k) + 3]

number of isolated dcsources andcapacitors

[(2 × k) + 1] [(2 × k) + 1] [(2 × k) + 1]

number of switchesand gate drivers

(6 × k) + 4 (6 × k) + 4 (6 × k) + 4

standing voltages onall the switches in theproposed topology

Vdc Vdc Vdc

H-bridge inverterauxiliary inverter 2 ×Vdc 4 ×Vdc 6 ×Vdc


3 Modulation method

The theory attempts to modify the hybrid modulation methodcited in [25] to suit any number of levels and accordinglyFig. 5 displays the output for 15-level produced using thenew power module. Fig. 6 depicts the synthesis of outputvoltage waveform obtained from the output of bridge andauxiliary inverter, where Vc and Vr are the amplitudes ofcarrier and reference waveforms. Although the switches S1and S4 are driven by comparing Vc and Vr, the switches S3and S2 are made to conduct by comparing Vc and −Vr to

Table 3 Power components required between symmetricaland asymmetrical modes of proposed topology

Parameters Symmetrical Asymmetrical

Binary Ternary

maximum outputvoltage

Vdc ×[(m−1)/2]

Vdc ×[(m−1)/2]

Vdc ×[(m−1)/2]

number of isolated dcsources andcapacitors

(m−1)/2 (m + 1)/4 ln(m)/ln3

number of switchesand gate drivers

m + 3 (m + 9)/2 (m + 15)/3

standing voltages onall the switches in theproposed topology

Vdc Vdc Vdc

H- bridge inverter(S1′–S4′)(Sa1–San+1′) Vdc × [(m−3)/

2]Vdc × [(m−3)/2]

Vdc × [(m−3)/2]

control strategies applicable applicable applicablemulticarrier PWMhybrid PWM applicable applicable applicable


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produce the voltage V01. The switches (Sa1–Sa3) and (Sa1′–Sa3′) are switched on/off when the reference wave becomesdiscontinuous, as illustrated in Fig. 3.The turning on of switches (Sa1′, Sa2 and Sa3), (Sa1, Sa2 and
Sa3′) and (Sa1′, Sa2 and Sa3′) facilitate to acquire (2 × Vo), (4 ×Vo) and (6 × Vo), respectively, as depicted in Fig. 6.

4 Selection of devices

The methodology translates the fact that the blocking voltageof the power devices during off state vary in accordance withthe change with the magnitudes of voltage sources. Thestanding voltage of the switches (Sa1–San) and (Sa1′–San′)during off state are (VSa1–VSan) and (VSa1′–VSan′). Theforward blocking voltage of top switching devices VSa1 andVSa1′ in the auxiliary inverter during off state is obtained by (1)

VSa1 = V ′Sa1 = 2

2 2n( ) − 1

( )∑nk=0

Vk (1)

Similarly, the forward blocking voltage of bottom switchingdevices VSan+1 and VSan+1′ in the auxiliary inverter are

Fig. 7 Output voltage waveform

a H-bridge inverterb Auxiliary inverter


obtained by (2)

VSan+1 = V ′San+1 = 2n

2 2n( ) − 1

( )∑nk=0

Vk (2)

The forward standing voltage of the intermediate devices VSan

and VSan′ in the auxiliary inverter is calculated by adding themagnitudes of the voltage sources across the devices. Theswitching frequency of the power devices in the auxiliaryinverter is dependent on the selection of the voltagemagnitude of the voltage sources. If the voltage sources arearranged in the ratio of 2 or 3, the switching frequency ofthe devices is equal to two-fold of the reference frequency.If the voltage ratio is arranged in the ratio of power of 2, theswitching frequency of some devices may be twice, or theother devices may be equal to the reference frequency.The forward blocking voltages of the power devices S1–S4

during off state in the H-bridge inverter are VS1–VS4 and aregiven in (3)

VS1 = VS2 = VS3 = VS4 =1

2 2n( ) − 1

( )∑nk=0

Vk (3)

Since these switches are switched at carrier frequency, the


Fig. 8 Output voltage waveform of H-bridge inverter and its corresponding harmonic spectrum

a Load voltage waveformb Harmonic spectrum

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standing voltage of these switches is naturally smaller thanthe output voltage. It becomes much smaller withincreasing number of levels and a metal-oxidesemiconductor field-effect transistor (MOSFET) is preferredunder these circumstances. Therefore it is concluded thatthe proposed inverter requires power devices of differentvoltage rating which is mainly dependent on the selectionof magnitudes of voltage sources. However, the proposedinverter carries the advantage over the conventional MLI

Fig. 9 Experimental setup


that the standing voltage of the switches switched at highfrequency is low and that the switching frequency of theswitches with high-voltage stress is low.

5 Simulation results

The proposed inverter is simulated in MATLAB/SIMULINKR2010b with the following simulation parameters: V0 = 40 V,


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V1 = 80 V, V2 = 160 V, fs = 80 kHz, R = 110 Ω and L = 50 mH.The hybrid modulation method is used to control the proposedinverter. Figs. 7 and 8 show the output voltage waveform ofH-bridge inverter and auxiliary inverter along with the loadvoltage waveform and its corresponding harmonic spectrum.
6 Experimental results

Fig. 9 explains the prototype fabricated using MOSFETs (IRF840), insulated bipolar gate transistors (IRG4BC20UPBF)

Fig. 12 Practical viability of the proposed MLI topology

a Inductive load voltage and current waveformb Voltage spectrum

Fig. 11 Output voltage

a H-bridge inverterb Auxiliary inverter

Fig. 10 Gating signals


and a resistive inductive load of 110 Ω and 50 mH for15-level inverter. The experiment is conducted undersimilar specifications as those used in simulation. Thegating pulses using hybrid modulation are generated usingthe Xilinx-based system generator facility available as atoolbox in MATLAB R2010a and is downloaded in XilinxSpartan XC3SD1800A-FG676-4 Spartan 3A DSP FPGAboard.The gating signals and the output voltage across H-bridge

inverter and auxiliary inverter seen in Figs. 10 and 11 are


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captured using Tektronix TPS 2024 scope. The performanceof the proposed inverter with inductive load correspondingto a modulation index of 1 and an output of 220 Vpresented in Fig. 12 projects the practical viability of theproposed MLI topology.
7 Conclusion

A new MLI topology using auxiliary reverse-connectedvoltage sources with significant advantages over conventionaltopologies in terms of the required power switches andisolated dc sources has been proposed. The switchingoperation realised using two different high and low-frequencyswitching modes of the hybrid modulation procedure hasbeen found to endow it with reduction in power switches andthe magnitude of blocking voltages. The control method hasbeen carved to be free from complexities since it generatesonly minimum PWM pulses and remaining switchingachieved using fundamental switching control. The hardwareresults of the 15-level MLI obtained for an inductive loadhas been found to validate the simulation results and projectthe suitability of the new MLI configuration for use indifferent contexts in this energy crunchy era.

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Cross-switched multilevel inverter using auxiliary reverse-connected voltage sources