CPU Design Documentation Sample

8/12/2019 CPU Design Documentation Sample

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University Of Santo TomasEspaa, Manila

Faculty of EngineeringElectronics Engineering Department

CPU NAME (optional) Central Processing Unit (CPU) Design

Submitted by:

Surname, First Name MI.






(Centered and alphabetically arranged)

4 ECE _

*Insert name of your Professor here*Professor

February 22, 2014


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TABLE OF CONTENTS

I. Introduction A. Background of the Study 3B. Design Overview 4C. Scope and Delimitation 4

II. Architecture A. Block Diagram 5B. Bus Unit 7C. I/O Ports ..D. Program Counter ..E. General Purpose Registers

K. Accumulator and TMP Register 10L. Status/Flag Register 11M. Arithmetic and Logic UnitN. Instruction RegisterO. Controller/Sequencer

*The con tents of th is Chapter II (Archi tec ture) wi l l vary depending on your des ign .Jus t m ake sure you inc lud e the descr ip t ions of every regis ter /uni t /par t ofyour des ign .*

III. Controller/Sequencer A. State CounterB. State DecoderC. Control LogicD. Control Signals

IV. Instruction Set Architecture

A. Instruction Set Format / Opcode MappingB. Instruction SummaryC. Instruction Description

V. Simulation Results A. Sample CodeB. Execution Trace (Tabulated)

(Centered, font size: 14)

(font size: 11 for Arial, 12 for TNR)


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VI. Design Calculations A. Noise Margin 51B. Power Dissipation 52C. Fan Out 52D. Propagation Delay 53E. Clock Frequency

VII. Recommendations

References

L is t of Ins t ruc t ion s

App endix A: Hardware Summ ary

App endix B: Speci f ica t ion Sheets


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CHAPTER HEADER: Centered,Bold, font size: 14)

Sub-header: Left-justified, bold, one font size larger thanthe body

BODY: observe proper indention, justified, font size:11 if Arial, 12 ifTNR, 1.5 spacing, no space between paragraphs

I. INTRODUCTION

A. Background of the Study

CPU designing involves the first task of knowing its usage. An ideal CPU for a particular

task should be powerful enough to handle a job. For example a simple 4-bit processor is

sufficient enough to control room-air-conditioning unit and on and on a different side, a

complicated quad-core microprocessor is ideal for a personal computer. The interchange of

their usage has significan t disadvantages for both applications. And according to Carpinelli The

key is to match the capabilities of the CPU to the tasks it will perform.

According to Malvino, the CPU or central processing unit are circuits which are designed

to act as the brain of a computer. The CPU could perform basic arithmetic operations such as

addition and subtraction, logic operations such as AND and OR and control operations. Thus, it

could process data. By definition, a microprocessor is a CPU which is constructed on a single

silicon chip. A CPU is an electronic circuit which can interpret and execute instructions and

control input and output.

According to Carpinelli, to design a CPU, we first develop its instruction set architecture,

including its instruction set and its internal registers. We then create a finite state machine

model of the micro-operations needed to fetch, decode and execute every instruction in its

instruction set. Then we develop an RTL specification for this state machine.

This paper aims to present a CPU design in partial fulfillment of the requirements of the

course COMP421.


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II. ARCHITECTURE

A. Block Diagram

A generalized block diagram of KISAP microprocessor is shown in Figure 1.

Figure 1. SAP143 Microprocessor Block Diagram


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B. Bus Unit

SAP143 has a 16-bit address bus and an 8-bit data bus. Access to the bus is controlled

via three-state buffers; those not connected to the bus are two-state. Additional bus is

included whose function is to

C. I/O Unit

Ports 1 and 3 are implemented using 8-bit controlled buffer registers. Ports 2 and 4 use

controlled shift-right registers. A control logic controls loading/sending data through ports 2

and 4 via a high ACK signal.

D. Program Counter

The program counter is a 16-bit controlled ripple counter. At the start of a program run, a

CLR signal resets the count value to 0000h. A high CP signal increments the counter up to

FFFFh.

.

N. Instruction Register

The SAP143 uses an 8-bit operation code (op-code). After fetching the instruction from

the RAM, the op-code is loaded into the instruction register (IR). The IR is an 8-bit

controlled buffer register, the inputs of which are latched to the lower byte of the word bus.

The output of the IR drives the controller-sequencer until a new instruction is fetched and

loaded.

O. Controller / Sequencer

5SAP2s controller/sequencer (CON) is asynchronous (unclocked ). The CON is

combinational circuit, driven by a state controller, provided by a 18-state ring counter.

The CON provides a variable machine cycle, which resets the ring counter after every

instruction.

More detailed descriptions on the controller/sequencer can be read in the next chapter.


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III. CONTROLLER / SEQUENCER

The Control Unit of SAP143 is designed using hardwired control. Under this design, the

states (Give a short background about the control unit design)

A. State Counter

SAP143 includes 187 instructions, which consumes 241 T-states. Thus, the state

counter.

B. State Decoder

The output of the T-State counter is connected to the T-State decoder. Since

there are 241 states, the state decoder uses two 4x16 decoders which are

connected in a coincident decoding scheme to form outputs, which creates the

8x256 decoder leaving 15 decoder outputs unused. The states are activated

depending on the counters input.

C. Control Logic

The outputs of the decoder will serve as the inputs to a control logic which is

responsible in sending control signals to registers, ALU, .

D. Control Signals Summary

Control Signals are used to direct the registers, dictate the operations and

operands. Table 1 shows that summary of the control signals used in SAP143 design.

TABLE 1. Control Signal Definition

CONTROL

SIGNALDEFINITION

ACCBUS output accumulator to bus

ACCDEC decrement the accumulator

ACCINC increment the accumulator

ACCLD enable loading to accumulator


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ADD add the data in the designated register to theaccumulator

ALULD enable loading to ALU

AND AND the accumulator contents with the designatedregister

BBUS output register B to bus

BLD enable loading to register B

CBUS output register C to bus

CLD enable loading to register C

HBUS output H to bus

HLD enable loading to H

HXALD load H to ALU

IRLD enable loading to instruction register

IXDEC decrement index register

MARLD enable loading to memory address register

MEMBUS output MDR to bus

NOT invert the accumulator contents

OROR the accumulator contents with the designatedregister

PCBUS output program counter to bus

PCINC increment program counters

SPDEC decrement SP

SUB subtract the data in the designated register to the

accumulatorXOR XOR the accumulator contents with the designatedregister

(Arrange the Con trol Signals alphabetically)


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IV. INSTRUCTION SET ARCHITECTURE

A. Instruction Format / Op-code Mapping

Descr ibe here how y ou came up wi th yo ur ins t ruc t ion c odes /opcod es .

Also , present in tabular form a l l the ins t ruc t ions together wi th the i r

opco des in b inary and hex form. Ex:

SAP143 has 180 instructions which are represented by an 8-bit instruction code. The

instructions are divided according to their functions, namely, memory-referenced, arithmetic,

logical, .

The last 2 bits, B7 and B6, of the op-code determines which functional group the

instruction belongs to. Then, the next bits represent

B7 B6 B5 B4 B3 B2 B1 B0

Table _. Op- code Mapping for B7 and B6

B7 B6 Instruction Group

0 0 Arithmetic / Logical

0 1 Memory-Referenced

1 0 Branching

1 1 Machine Control

Instruction

Group/Function

Operand


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For Arithmetic and Logical Operations:

B5 Function B4 B3 Function B2 B1

0 Arithmetic

0 0 ADD

0 1 ADC

1 0 SUB

1 1 SBB

1 Logical

0 0 NOT

0 1 AND

1 0 OR

1 1 XOR

B. Instruction Summary

The SAP143 have 180 instructions which can be divided functionally into the following

groups:

Memory-reference

Arithmetic

Register

Jump / Branching

Logical

Machine Control

Other Instructions

The following summary shows the instructions belonging to each group and the number

of operands required for each. The source operand is src , the destination operand is dst .


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C. Instruction Description

This section describes each instruction by means of presenting its op code,

addressing mode, T states, flags needed & affected and its microinstructions per T state.

Table _. Description of .

MEMORY REFERENCE INSTRUCTIONS

LDA LOAD ACCUMULATOR

Op Code 70HAddressingMode

DIRECT

T States 6Flags Needed NONEFlags Affected NONE

Microinstructions per T State:FETCH1: MAR PC MARLD, PCBUSFETCH2: MDR M, PC PC + 1 MEMOT, PCINC

FETCH3: IR MDR IRLD, MEMBUSLDA1: MAR SP MARLD, SPBUSLDA2: MDR M, SP SP + 1 MEMOT, SPINCLDA3: ACC MDR ACCLD, MEMBUS, CLR

LDSP LOAD STACK POINTER

Op Code 68HAddressingMode

IMPLIED


Microinstructions per T State:FETCH1: MAR PC MARLD, PCBUS

FETCH2: MDR M, PC PC + 1 MEMOT, PCINCFETCH3: IR MDR IRLD, MEMBUS

LDSP1: MAR PC MARLD, PCBUS

LDSP2: MDR M, PC PC + 1 MEMOT, PCINCLDSP3: L MDR LLD, MEMBUSLDSP4: MAR PC MARLD, PCBUS

LDSP5: MDR M, PC PC + 1 MEMOT, PCINC


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LDSP6: H MDR HLD, MEMBUS

LDSP7: SP HL SPLD, HLBUS, CLR

STAX STORE ACCUMULATOR WITH INDEX ADDRESS TO MEMORYOp Code A0HAddressingMode

INDEX


Microinstructions per T State:FETCH1: MAR PC MARLD, PCBUSFETCH2: MDR M, PC PC + 1 MEMOT, PCINC

FETCH3: IR MDR IRLD, MEMBUSSTAX1: MAR PC MARLD, PCBUS

STAX1: MDR M, PC PC + 1 MEMOT, PCINCSTAX2: L MDR LLD, MEMBUSSTAX3: MAR PC MARLD, PCBUSSTAX4: MDR M, PC PC + 1 MEMOT, PCINCSTAX5: H MDR HLD, MEMBUSSTAX6: L L + IX(0-7) LBUS, LXALD, ADDSTAX7: H H + IX(8-15) HBUS, HXALD, ADDSTAX8: MAR HL MARLD, HLBUSSTAX9: MDR ACC MEMLD, ACCBUS

STAX10: M MDR MEMIN, CLR

JUMP AND CALL INSTRUCTIONS

JP JUMP

Op Code C0HAddressingMode

DIRECT


Microinstructions per T State:FETCH1: MAR PC MARLD, PCBUS

FETCH2: MDR M, PC PC + 1 MEMOT, PCINCFETCH3: IR MDR IRLD, MEMBUS


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JP1: MAR PC MARLD, PCBUS

JP2: MDR M, PC PC + 1 MEMOT, PCINCJP3: L MDR LLD, MEMBUSJP4: MAR PC MARLD, PCBUSJP5: MDR M, PC PC + 1 MEMOT, PCINC

JP6: H MDR HLD, MEMBUSJP7: PC HL PCLD, HLBUS, CLR

JZ JUMP IF ZEROOp Code C1HAddressingMode

DIRECT

T States 10

Flags Needed ZEROFlags Affected NONE

Microinstructions per T State:1 Branch FETCH1: MAR PC MARLD, PCBUS

FETCH2: MDR M, PC PC + 1 MEMOT, PCINCFETCH3: IR < MDR IRLD, MEMBUS

JZY1: MAR PC MARLD, PCBUS

JZY2: MDR M, PC PC + 1 MEMOT, PCINCJZY3: L MDR LLD, MEMBUSJZY4: MAR PC MARLD, PCBUSJZY5: MDR M, PC PC + 1 MEMOT, PCINCJZY6: H MDR HLD, MEMBUS

JZY7: PC HL PCLD, HLBUS

0 Branch JZN1: MAR


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FETCH3:

RET RETURNOp Code F0HAddressingMode

IMPLIED

T States 16Flags Needed NONE

Flags Affected NONEMicroinstructions per T State:

FETCH1: . FETCH2:FETCH3:


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V. SIMULATION RESULTS

A. Sample CodeTo verify that the CPU design is working, let us consider the segment of code

shown below. Table 9 shows the execution trace of these codes. Suppose 10 bytes ofdata are stored in memory from address 2000H to 2009H. Show a program that will copythese 10 bytes at address 5000H to 5009H.

LXI H, 1FFFh ;Initialize index registerMVI C, 0Ah ;load decimal 10 to C register

Loop: INX H ;increment index registerMOV B,M ;store byte to B registerMOV A,H ;load data of H to accumulator

ADI 30h ;add offset

MOV H,A ;load offset value to index registerMOV M,B ;write byte in new locationSUI 30h ;subtract offsetMOV H,A ;restore HDCR C ;decrement counterJNZ Loop ;check if zero, if not jump backHLT ;stop

Before computer run:PSW: 0082h HL: 0506hBC: 0102h SP: FFEEhDE: 0304h PC: 1000h3000: 11h 5000: 2Ah3001: 12h 5001: 2Fh3002: 13h 5002: 6Bh3003: 14h 5003: 7Ah3004: 15h 5004: CDh3005: 16h 5005: EFh3006: 17h 5006: 8Ah3007: 18h 5007: BBh3008: 19h 5008: DCh

3009: 1Ah 5009: 00h


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B. Execution Trace

Table 9. Execution Trace of the Sample Code (see previous page)

ADDRESS DATA C=0Ah C=09h C=08h C=07h C=06h

1000 F6h (LXI H)H=1FhL=FFh1001 FFh

1002 1Fh1003 EAh (MVI C)

C=0Ah1004 0Ah

1005 32h (INX H) H=20hL=00hH=20hL=01h

H=20hL=02h

H=20hL=03h

H=20hL=04h

1006 8Fh (MOV B,M) B=11h B=12h B=13h B=14h B=15h1007 85h (MOV A,H) A=20h A=20h A=20h A=20h A=20h1008 60h (ADI) A=50h

SR=06h

A=50h

SR=06h

A=50h

SR=06h

A=50h

SR=06h

A=50h

SR=06h1009 30h100A A8h (MOV H, A) H=50h H=50h H=50h H=50h H=50h100B B9h (MOV M, B) 5000:11h 5001:12h 5002:13h 5003:14h 5004:15h100C 62h (SUI) A=20h

SR=02h A=20hSR=02h

A=20hSR=02h

A=20hSR=02h

A=20hSR=02h100D 30h

100E A8h (MOV H, A) H=20h H=20h H=20h H=20h H=20h

100F 2Ah (DCR C) C=09hSR=06hC=08h

SR=02hC=07h

SR=02hC=06h

SR=06hC=05h

SR=06h1010 CFh (JNZ)

TRUE TRUE TRUE TRUE TRUE1011 05h

1012 10h1013 FFh (HLT)

ADDRESS DATA C=05h C=04h C=03h C=02h C=01h1000 F6h (LXI H)1001 FFh1002 1Fh1003 EAh (MVI C)1004 0Ah

1005 32h (INX H) H=20hL=05hH=20hL=06h

H=20hL=07h

H=20hL=08h

H=20hL=09h

1006 8Fh (MOV B,M) B=16h B=17h B=18h B=19h B=1Ah1007 85h (MOV A,H) A=20h A=20h A=20h A=20h A=20h1008 60h (ADI) A=50h

SR=06h A=50hSR=06h

A=50hSR=06h

A=50hSR=06h

A=50hSR=06h1009 30h

100A A8h (MOV H, A) H=50h H=50h H=50h H=50h H=50h100B B9h (MOV M, B) 5005:16h 5006:17h 5007:18h 5008:19h 500A:1Ah100C 62h (SUI) A=20h A=20h A=20h A=20h A=20h


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100D 30h SR=02h SR=02h SR=02h SR=02h SR=02h100E A8h (MOV H, A) H=20h H=20h H=20h H=20h H=20h

100F 2Ah (DCR C) C=04hSR=02hC=03h

SR=06hC=02h

SR=02hC=01h

SR=02hC=00h

SR=86h1010 CFh (JNZ)

TRUE TRUE TRUE TRUE FALSE1011 05h1012 10h1013 FFh (HLT)

INSTRUCTION STATES ACTIVE CONTROL SIGNALSLXI H, 1FFFh 5 T1 F P , C P , CE, L i

T2 E P , LM

T3 C P , CE, L HL

T4 E P , LM

T5 C P , CE, L HH MVI C, 0Ah 3 T1 F P , C P , CE, L i

T2 E P , LM

T3 C P , CE, L C INX H 2 T1 F P , CP , CE, L i

T2 M U MOV B,M 3 T1 FP , CP , CE, L i

T2 L M, EM

T3 L B, CE MOV A,H 2 T1 F P , CP , CE, L i

T2 L A, E MH ADI 30h 4 T1 F P , C P , CE, L i

T2 E P , LM

T3 CE, L T, Cp

T4 E U, L A, LF MOV H,A 2 T1 F P , CP , CE, L i

T2 L HH, E A MOV M,B 3 T1 F P , CP , CE, L i

T2 E M, LM

T3 WE, CE, E B SUI 30h 4 T1 F P , C P , CE, L i


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T2 E P , LM

T3 CE, L T, CP

T4 E U, L A, LF, SMOV H,A 2 T1 F P , CP , CE, L i

T2 L HH, E A DCR C 3 T1 F P , C P , CE, L i

T2 L T, EC

T3 L C, EU, LF, S, E ID JNZ Loop 6/3 If TRUE

T1 F P , C P , CE, L i

T2 E P , LM'

T3 CE', L XH', C P

T4 E P , LM'T5 CE', L PH

T6 E XL, LPL If FALSE

T1 F P , C P , CE, L i

T2 C P

T3 C P HLT 2 T1 F P , C P , CE, L i

T2

**For other reference on s im ulat ion resul ts d ocum entat ion, please see s l ides 24 to

28 of our lecture on Micro processo r Design (Lecture 6 PPT).


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VI. DESIGN CALCULATIONS

Data and pertinent computations with respect to the design are shown below such as

power dissipation, noise margin, fan out, propagation delay and clock frequency.

A. Noise Margin

(Write a short description here)

Noise margin, also called Noise Immunity, is the maximum noise voltage added or

subtracted to the input of a digital circuit that does not cause an undesirable change in the

circuit output. It is calculated from the level voltage level available in the output gate and

the voltage level required at the input gate. Table 15 shows the logic level specifications of

a TTL family to be used for the computations of noise margin. (table of logic level specification to be used)

Table 15. Logic Level Specifications: V OL, V IL, VOH , V IH

The general formula for Noise Margin is: (Then, general formula)

( )

or

( )

(Then show your computations here. You can opt to use tables to clearly present the

specific gates and their corresponding noise margins.)

.


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.

B. Power Dissipation

(short description)

(logic level specification)

(general formula)

(computations)

E. Clock Frequency Calculation

. .

1 x (J-K flip-flop) = 1 x 26 ns

3 x (4 input NOR) = 3 x 18.5 ns1 x (3 input NOR) = 1 x 6.25 ns2 x (4 input NAND) = 2 x 5.65 ns2 x (2 input NAND) = 2 x 15 ns1 x (3 input NAND) = 1 x 18.5 ns2 x (2 input OR) = 2 x 22 ns1 x (INVERTER) = 1 x 15 ns-------------------------------------------------------------------------------------------

Total delay = 206.55 ns

Clock Frequency = 1 / (206.55n x 2) = 2.421 MHz


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VII. RECOMMENDATIONS

Since the design is an 8 data bit microprocessor, the group recommends maximizing the

number of instructions possible. It is capable of supporting up to 256 instructions so

additional sets may be introduced such as interrupt request. Another point for improvement

is


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REFERENCES

[1] Malvino, . (Font size: 11 for Arial, 12 for TNR)

[2] .


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Font size: 22

Font size: 11

INDEX

A ADC B 37

ADD B 30

ADD C 31

BBCD 25

( 3 or 4-colum n list of all instructions; includethe page number where the description of theinstruction can be found in the documentation/Chapter IV Section C)


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APPENDIX AHardware Summary


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APPENDIX BSpecification Sheets

Documents

CPU Design Documentation Sample