CPRI v8.7 LogiCORE IP Product Guide (PG056) - Xilinx · 2019. 1. 13. · CPRI v8.7 8 PG056 October 5, 2016 Chapter 1: Overview License Type This Xilinx LogiCORE™ IP module is provided

CPRI v8.7

LogiCORE IP Product Guide

Vivado Design Suite

PG056 October 5, 2016

CPRI v8.7 2PG056 October 5, 2016 www.xilinx.com

Table of ContentsIP Facts

Chapter 1: OverviewFeature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 2: Product SpecificationChip Period (TC) in This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Related Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Speed Grade Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12CPRI Core Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Management Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 3: Designing with the CoreGeneral Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Clocking and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Interfacing to the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Chapter 4: Design ConsiderationsReference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Using the PLL to Generate the Core Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Resource Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Line Speed Configuration and Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121RS-FEC Enabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Using an External GMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Delay Measurement and Requirement 21 (R21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

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Chapter 5: Design Flow StepsCustomizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Chapter 6: Example Design

Chapter 7: Test Bench

Appendix A: Verification, Compliance, and InteroperabilitySimulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165Hardware Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Appendix B: Migrating and UpgradingMigrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Appendix C: DebuggingFinding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173Vivado Design Suite Debug Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175AXI4-Lite Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Appendix D: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

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CPRI v8.7 4PG056 October 5, 2016 www.xilinx.com Product Specification

IntroductionThe LogiCORE™ IP Common Public Radio Interface (CPRI™) core is a high-performance, low-cost flexible solution for implementation of the CPRI interface. It uses state-of-the-art transceivers to implement the Physical Layer. A compact and customizable Data Link Layer is implemented in the FPGA logic.

Features• UltraScale architecture-based device designs

operate at line rates of 614.4, 1,228.8, 2,457.6, 3,072, 4,915.2, 6,144, 8,110.08, 9,830.4, 10,137.6 and 12,165.12 Mb/s using GTHE3, GTYE3, GTHE4 or GTYE4 transceivers.

• Optional RS-FEC supported using GTYE3 and GTYE4 transceivers at 24,330.24, 12,165.12, 10,137.6 and 8,110.08 Mb/s line rates.

• Zynq-7000, Virtex®-7, and Kintex®-7 device designs operate at line rates of 614.4, 1,228.8, 2,457.6, 3,072, 4,915.2, 6,144, 9,830.4, and 10,137.6 Mb/s using GTXE2, GTHE2 transceivers.

• Artix®-7 devices designs operate at line rates of 614.4, 1,228.86 2,457.6, 3,072, 4,915.2, and 6,144 Mb/s using GTPE2 transceivers.

• UTRA-FDD in-phase and quadrature-phase data (I/Q) module supporting 1 to 48 Antenna-Carriers per core

• Automatic speed negotiation

• Supports both Fast (Ethernet) and Slow High-Level Data Link Control (HDLC) Control and Management (C&M) channels per CPRI Specification v7.0 [Ref 1].

IP Facts

LogiCORE IP Facts

Core Specifics

SupportedDevice Family(1)

Zynq® UltraScale+™ MPSoCUltraScale+UltraScale™

Zynq-7000 All Programmable SoC(2)7 Series(3)

See Speed Grade Support.

Supported UserInterfaces

Generic data, status, configuration andmanagement interfaces,

AXI4-Lite management interface

Resources Performance and Resource Utilization web page

Provided with CoreDesign Files Encrypted register transfer level (RTL)

Example Design VHDL

Test Bench VHDL

Constraints File Xilinx Design Constraints (XDC)

Simulation Models VHDL, Verilog

SupportedS/W Drivers N/A

Tested Design Flows(4)

Design Entry Vivado® Design Suite

Simulation For supported simulators, see theXilinx Design Tools: Release Notes Guide.

Synthesis Vivado Synthesis

SupportProvided by Xilinx at the Xilinx Support web page

Notes: 1. For a complete list of supported devices, see the Vivado IP

catalog.2. Excludes the Zynq-7000 010 and 020 devices.3. Excludes the Artix-7 100T device in CSG324 and FTG256

packages.4. For the supported version of the tool, see the

Xilinx Design Tools: Release Notes Guide.

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Chapter 1

OverviewCPRI™ is a standard for communication between a Radio Equipment Controller (REC) or Base Station and one or more Radio Equipment (RE) units in a cellular network. By defining a publicly available specification for the key internal interface between these units, an independent technology evolution is fostered for cellular equipment products. Figure 1-1 shows the position of the interface within a cellular system. The CPRI v8.7 core has been designed to the CPRI Specification v7.0 [Ref 1].

The CPRI core implements Layer 1 and Layer 2 of the CPRI specification in UltraScale™ devices, Zynq®-7000 All Programmable SoCs, and 7 series devices.

Feature Summary• Designed to CPRI Specification v7.0 [Ref 1]

• Can be configured as a master or slave at generation time. Master core can be switched to operate as a slave through a configuration port.

• Suitable for use in both Radio Equipment Controllers (RECs) and Radio Equipment (RE), including multi-hop systems. A multi-hop reference design is available at the CPRI product page (CPRI product page).

• Easy-to-use I/Q data interface together with optional modules for UMTS terrestrial radio access - frequency division duplexing (UTRA-FDD) and Evolved UMTS Terrestrial Radio Access (E-UTRA) data mappings

• Supports both Ethernet and HDLC Control and Management channels

X-Ref Target - Figure 1-1

Figure 1-1: Location of CPRI in a Cellular System

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Chapter 1: Overview

• Supports vendor-specific data transport including support for the passing of control AxC information in global system for mobile communications (GSM) systems

• Master core can be switched to operate as a slave through a configuration port

• Core includes the necessary clocking and transceiver logic to enable easy integration into your design

• Synthesizable example design and simple demonstration test bench provided

• Easy-to-use interface for in-phase (I) and quadrature-phase (Q) data and synchronization

• Supports vendor-specific data transport

• Delay measurement capability meets CPRI Requirement 21 per CPRI Specification v7.0 [Ref 1]

• Reed-Solomon Forward Error Correction (RS-FEC) supported at 8,110.08 Mb/s, 10,137.6 Mb/s, 12,165.12 Mb/s and 24,330.24 Mb/s line rates.

ApplicationsThe goal of the CPRI interface is to use one physical connection for the radio data (I/Q data), radio unit management (for example, Automatic Gain Control, alarms) and synchronization (clock frequency control, frame synchronization). Table 1-1 shows the data rates supported by each Xilinx device. Data is transferred over a single serial link. This link is defined to be electrically compliant with existing high-speed serial link standards such as the Gigabit Ethernet and 10 Gigabit eXtended Attachment Unit Interface (XAUI) standards.

Table 1-1: Supported Data Rates

FamilyFrequency in Mb/s

614.4 1,228.8 2,457.6 3,072.0 4,915.2 6,144.0 8,110.08 9,830.4 10,137.6 12,165.12 24,330.24

Virtex®-7

-1 speed grade Yes Yes Yes Yes Yes Yes No No No No No

-2 speed grade Yes Yes Yes Yes Yes Yes No Yes Yes No No

-3 speed grade Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No

Kintex®-7 and Zynq®-7000

-1 speed grade Yes Yes Yes Yes Yes Yes No No No No No

-2 speed grade Yes Yes Yes Yes Yes Yes No Yes(1) Yes(1) No No

-3 speed grade Yes Yes Yes Yes Yes Yes No Yes(1) Yes(1) Yes(1) No

Artix®-7

-1 speed grade Yes Yes Yes Yes No No No No No No No

-2/-3 speed grade Yes Yes Yes Yes Yes Yes

(2) No No No No No

UltraScale™ and UltraScale+™


-2/-3 speed grade Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

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Chapter 1: Overview

System RequirementsFor a list of System Requirements, see the Xilinx Design Tools: Release Notes Guide.

Recommended Design ExperienceAlthough the CPRI core is a fully-verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, previous experience building high performance, pipelined FPGA designs using Xilinx implementation software and the XDC file is recommended.

Contact your local Xilinx sales representative for a closer review and estimation for your specific requirements.

Licensing and Ordering Information

License CheckersIf the IP requires a license key, the key must be verified. The Vivado® design tools have several license check points for gating licensed IP through the flow. If the license check succeeds, the IP can continue generation. Otherwise, generation halts with error. License checkpoints are enforced by the following tools: Vivado design tools: Vivado synthesis, Vivado implementation, write_bitstream (Tcl Command).

IMPORTANT: The IP license level is ignored at checkpoints. The test confirms a valid license exists. It does not check IP license level.

Zynq UltraScale™+ MPSoC


-2/-3 speed grade Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Notes: 1. Not supported on non Pb-free flip-chip BGA (FFG) packages.2. Not supported on wire-bond packages.

Table 1-1: Supported Data Rates (Cont’d)

FamilyFrequency in Mb/s

614.4 1,228.8 2,457.6 3,072.0 4,915.2 6,144.0 8,110.08 9,830.4 10,137.6 12,165.12 24,330.24

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Chapter 1: Overview

License TypeThis Xilinx LogiCORE™ IP module is provided under the terms of the Xilinx Core License Agreement. For full access to all core functionalities in simulation and in hardware, you must purchase a license for the core. Contact your local Xilinx sales representative for information about pricing and availability of Xilinx LogiCORE IP.

For more information, visit the CPRI product page.

Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative.

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Chapter 2

Product SpecificationThe CPRI™ core implements Layer 1 and Layer 2 of the CPRI specification in UltraScale™ architecture-based, Zynq®-7000 and 7 series devices. The CPRI core provides the following client-side interfaces.

• I/Q Interface: Consists of a stream of radio data (I/Q samples) that is synchronized to the Universal Mobile Telecommunications System (UMTS) radio frame pulse.

• Synchronization Interface: Provides the means for the client logic to synchronize to the network time by transmitting the UMTS radio frame pulse and clock frequency.

• High-Level Data Link Control (HDLC) Interface: Transports management information between master and slave. The HDLC interface is serialized and synchronous.

• Ethernet Interface: When configured to support speeds of up to 3,072 Mb/s, the Ethernet interface is presented as a Media Independent Interface (MII); this allows a 100 Mb Ethernet Media Access Controller (MAC) to be attached to the core to provide a high-speed channel for management information. When speeds over 4,915.2 Mb/s are supported, a Gigabit Media Independent Interface (GMII) option is available. This allows a 1 Gb Ethernet MAC to be attached to the core. The core includes an Ethernet frame buffer in both transmit and receive directions. The frame buffers are derived from the FIFO Generator and Block Memory Generator IP cores.

• Vendor-Specific Data Interface: Provides client logic access to the vendor-specific sub-channels in the CPRI stream.

• Management Interface: Provides control and status registers that allow management of the entire design from a supervisory processor.

The architecture of the core is shown in Figure 2-1. In addition to the interfaces described previously, the core contains these blocks:

• Status/Alarm Block: Reflects the internal state of the core and the state of the link.

• Start-up Sequencer: Performs line-rate negotiation and Control and Management (C&M) parameter negotiation at link start-up. This block continuously monitors the state of the link and sends the status to the alarm block.

• UMTS Terrestrial Radio Access – Frequency Division Duplexing (UTRA FDD) I/Q Module: A pluggable I/Q module to support multiplexing and demultiplexing of I/Q samples in UTRA FDD systems (shown in Figure 2-1).

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Chapter 2: Product Specification

• Evolved UMTS Terrestrial Radio Access (E-UTRA) I/Q Module: A pluggable I/Q module to support multiplexing and demultiplexing of I/Q samples in E-UTRA systems (not shown in Figure 2-1).

• Legacy raw I/Q Module: A pluggable I/Q Module for backward compatibility with the raw interfacing timing for CPRI cores (not shown in Figure 2-1).

As well as the low-level I/Q Interface of the core, there are additional I/Q modules that ship with the core to implement mapping and unmapping of I/Q samples, in accordance with the Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access - Frequency Division Duplexing (UTRA-FDD) and the Evolved UMTS Terrestrial Radio Access (E-UTRA) mappings in the CPRI Specification v7.0 [Ref 1].


Figure 2-1: CPRI Top-Level Block Diagram

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Chip Period (TC) in This DocumentCPRI operation is largely defined in units of the “chip period,” defined in the 3GPP specifications as TC = 1/3.84 MHz; or 260.416667 ns. In particular, the CPRI basic frame length is defined as 1 TC, so all in-phase and quadrature-phase data (I/Q) data and frame synchronization depend directly on this time constant.

Related InformationXilinx products are not intended for use in life-support appliances, devices, or systems. Use of a Xilinx product in such application without the written consent of the appropriate Xilinx officer is prohibited.

PerformanceThe CPRI core is delivered with constraints files to ensure correct operation at line rates up to 24,330.24 Mb/s.

Maximum FrequenciesTable 2-1 shows the client clock rates at which the CPRI LogiCORE™ IP core operates at all supported line rates.

Table 2-1: Client Clock Rates

Line Rate(Mb/s)

Client Clock Rate (MHz)

16-bit Datapath 32-bit Datapath 64-bit Datapath

614.4 30.72 15.36 7.68

1,228.8 61.44 30.72 15.36

2,457.6 122.88 61.44 30.72

3,072.0 153.6 76.8 38.4

4,915.2 245.76 122.88 61.44

6,144.0 307.2 153.6 76.8

8,110.08 245.76 122.88

9,830.4 245.76 122.88

10,137.6 307.2 153.6

12,165.12 368.64 184.32

24,330.24 368.64

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Resource UtilizationFor full details about performance and resource utilization, visit the Performance and Resource Utilization web page.

Speed Grade Support• 9,830 and 10,137.6 Mb/s are only supported on -2 and -3 speed grades for Virtex-7

devices. These designs are implemented using a 32-bit datapath.

• 12,165.12 Mb/s line rates are only supported on -3 speed grades in FFG packages for Virtex-7, Kintex-7 and Zynq-7000 devices. These designs are implemented with a 32-bit datapath.

• 9,830 and 10,137.6 Mb/s are only supported on -2 and -3 speed grades in FFG packages for Kintex-7 and Zynq-7000 devices. These designs are implemented using a 32-bit datapath.

• CPRI designs supporting maximum line rates of 6,144 Mb/s require the use of a 32-bit datapath in Virtex-7, Kintex-7 and Zynq-7000 devices with a speed grade of -1 or -2L. See the Virtex-7 and Kintex-7 FPGA data sheets for more information

• 6,144 Mb/s is only supported on -2 and -3 speed grades in non-wire bond packages for Artix-7 devices. In wire-bond packages the maximum line rate is 4,915.2 Mb/s on -2 and -3 speed grade devices.

• Line rates up to 12,165.12 Mb/s are supported on UltraScale and UltraScale+ devices with the exception of GTH transceiver-based cores operating on 0.90V -1LI speed grade parts. In these parts the maximum line rate is 10,137.6 Mb/s.

• Line rates of up to 24,330.24 Mb/s are supported on -2 and -3 speed grade Virtex UltraScale devices using the GTYE3 or GTYE4 transceiver.

IMPORTANT: In this product guide where a feature is referred to with the phrase “cores supporting x Mb/s”, this also implies its sub-line rates. For example, “cores supporting 3,072 Mb/s” also implies 2,457.6, 1,228.8 and 614.4 Mb/s; “cores supporting 6,144 Mb/s” also implies 4,915.2 Mb/s; “cores supporting 12,165.12 Mb/s” also implies 8,110.08 Mb/s.

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CPRI Core StructureThe CPRI core is generated as encrypted RTL along with unencrypted block layer and core support layer wrapper files. The encrypted RTL contains the transmit and receive state machines, control and management multiplexing and de-multiplexing, L1 synchronization logic and management registers. The block layer connects the encrypted RTL to an instance of the transceiver channel. In addition optional interfaces for AXI4-Lite management and Open Radio Equipment Interface (ORI) support are provided. The core support layer contains logic to connect the block layer to the transceiver common block and the clocking and reset logic required to implement a single CPRI link. Figure 2-2 shows a diagram of the CPRI core.


Figure 2-2: Block Level of the CPRI Core with Core Support Layer

cpri_v8_7

OptionalORI I/F

OptionalAXI I/F

Vendor Specific I/F

Management I/F

Ethernet I/F

IQ I/F

Control & Status _gt_and_clocks

_v7_gtwizard_gt

GT_CHANNEL

RXOUTCLKTXOUTCLK

DRP

_v7_gtwizard

Speed ChangeState Machine

MMCM

clk

recovered_clk

DRP I/F

Transceiver I/F

DRP

txoutclk

rxoutclk

Speed Change

State Machine

recclk_in

clk_in

_gt_common_wrapper

GT_COMMON

_support

RX Sync

BUFG

BUFG/BUFH/BUFR

recclk_out_clocking

Serial I/O

_tx_alignment

TX Sync

_resets

Reset Generation

Alignment I/F

Quad PLL Ports

clk_out

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The following blocks are instantiated in the block layer:

• Encrypted RTL. The encrypted RTL of the CPRI IP core.

• Transceiver wrapper files. These files instantiate the transceiver channel primitive (GT_CHANNEL) along with the RX Sync block. The RX Sync block contains logic to carry out receive phase and delay alignment. In addition a state machine is included to program the transceiver channel clock divider settings using the Dynamic Reconfiguration Port (DRP) bus when the line rate of the link is changed.

• ORI. Optional block to support the ORI standard.

• AXI4-Lite. Optional block to control AXI4-Lite management interface.

The core support layer contains elements that can be shared between multiple CPRI cores. In this level the following blocks are instantiated:

• Transmit clock logic. In Zynq-7000-based and 7 series-based designs an mixed-mode clock manager (MMCM) is used to generate the system clock. This is routed to the core layer through a BUFG. A state machine to change the MMCM clock divider settings on a speed change is also included. In UltraScale architecture-based designs the clock divider settings are set by the transceiver rather than by an external MMCM. The transmitter output clock from the transceiver is routed to the core layer through a BUFG_GT.

• Receive clock logic. The recovered clock output from the transceiver is routed to the core layer through a clock buffer. In Zynq-7000-based and 7 series-based designs you can select a BUFH, BUFG or BUFR to implement the receiver clock buffering. In UltraScale architecture-based designs a BUFG_GT is used.

• Common Block Wrapper. The transceiver common block GT_COMMON, containing the quad phase-locked loop (QPLL). In Zynq-7000-based and 7 series-based designs one common block is required for a group of four cores sharing the same quad in the device. In UltraScale architecture-based designs the common block wrapper is only present in cores supporting line speeds over 9,830.4 Mb/s.

• Transmit Alignment. With the exception of 64B66B line rates on UltraScale devices, the CPRI core bypasses the transmit and receive buffers. This ensures predictable and measurable latency. In buffer bypass mode, phase and delay alignment must be carried out after a reset or a change in line rate. If the MMCM is shared between multiple cores, transmit phase alignment is implemented in multi-lane manual mode. See the “TX Buffer Bypass” section in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 2], the 7 Series FPGAs GTP Transceivers User Guide (UG482) [Ref 3], the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 4] and the UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 5] for more information. The transmit multi-lane manual mode phase alignment provided by the TX Sync block is carried out in the core support layer as it performs the alignment for multiple transceivers. The CPRI core support layer provides I/O for up to three other CPRI cores to share the transmitter alignment block. When running at 64B66B line rates on UltraScale devices, instead of bypassing the buffer, the asynchronous gearbox is used. The latency across the gearboxes is reported in Gearbox Latency Register (0x16).

• Reset Generation. A reset block is used to generate the reset to the transceiver common block.

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Optionally the CPRI core can be generated without the core support layer. In this case the core top level corresponds to the block layer in Figure 2-2. An example design provided with the core includes the logic provided by the core support layer in Figure 2-2. Figure 2-3 shows a block diagram of the core when it is generated without the core support layer.

For more information on sharing the resources between multiple cores see Resource Sharing. The core support layer is discussed in more detail in Output Generation.

Port DescriptionsThe interfaces for this core are described in detail in Interfacing to the Core in Chapter 3.


Figure 2-3: Block Level of the CPRI Core without the Core Support Layer

Transceiver I/F

Vendor Specific I/F

IQ I/F

Management I/F

Ethernet I/F

HDLC I/F

Control & Status

cpri_v8_7

OptionalORI I/F

OptionalAXI I/F

_gt_and_clocks

_v7_gtwizard

_v7_gtwizard_gt

GT_CHANNEL

RXOUTCLK

TXOUTCLKDRP

Speed Change

State Machine

clk

recovered_clk

DRP I/F

Serial I/O

txoutclk

rxoutclk

clk_in

Alignment I/F

RX Sync

recclk_in

Quad PLL Ports

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Management Register MapThe memory map for the management register block is shown in Table 2-2.

Table 2-2: Management Register Addresses

Address AXI Address Name Mode

0x0 0x0 Status Code and Alarm Register (0x0) Read Only

0x1 0x4 Miscellaneous Status Register (0x1) Read Only

0x2 0x8 Current HDLC Rate Register (0x2) Read Only

0x3 0xC Current Ethernet Pointer Register (0x3) Read Only

0x4 0x10 Received Subchannel 2, Word 0 Register (0x4) Read Only



0x7 0x1C Received Subchannel 2, Word 3 Register (0x7) Read Only

0x8 0x20 Transceiver Loopback and Ethernet Reset Request Register (0x8) Read/Write

0x9 0x24 Transceiver Barrel Shift Position Register(0x9) Read Only

0xA 0x28 Preferred HDLC Rate Register (0xA) Read/Write

0xB 0x2C Preferred Ethernet Pointer Register (0xB) Read/Write

0xC 0x30 Current Line Speed Register (0xC) Read Only

0xD 0x34 Line Speed Capability Register (0xD) Read/Write

0xE 0x38 General Configuration and Transmit CPRI Alarms Register (0xE) Read/Write

0xF 0x3C R21 Timers Register (0xF) Read Only

0x10(1) 0x40 Current Protocol Version Register (0x10) Read Only

0x11 0x44 Preferred Protocol Version Register (0x11) Read/Write

0x12 0x48 Scrambler Seed Register (0x12) Read/Write

0x13 0x4C Descrambler Seed Register (0x13) Read Only

0x14(2) 0x50 Transmit FIFO Transit Time Register (0x14) Read Only

0x15 0x54 Watchdog Timeout Value Register (0x15) Read/Write

0x16(3) 0x58 Gearbox Latency Register (0x16) Read Only

0x17 0x5C FIFO Fill Level Register (0x17) Read/Write

0x18 0x60 General Debug Register (0x18) Read Only

0x19 0x64 High Resolution FIFO Transit Time—Integer Part Register (0x19) Read Only

0x1A 0x68 High Resolution FIFO Transit Time—Fractional Part Register (0x1A) Read Only

0x1B(4) 0x6C FEC Status Register (0x1B) Read Only

0x1C(4) 0x70 FEC CW Count Register (0x1C) Read Only

0x1D(4) 0x74 FEC Corrected CW Count Register (0x1D) Read Only

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Status Code and Alarm Register (0x0)

Miscellaneous Status Register (0x1)Bits 31:16 of this register carry read-only information on the version of the core. Bits 15:8 are the latched error register bits and are set High when the relevant error condition is detected. They are reset when register 0x1 is read through the management interface.

0x1E(4) 0x78 FEC Uncorrected CW Count Register (0x1E) Read Only

Notes: 1. Addresses 0x10 and above (AXI addresses 0x40 and above) are only present in cores that support operation at

4,915.2 Mb/s or higher.2. Present only in Kintex-7, Virtex-7 and Zynq-7000 based cores supporting 10,137.6 or 12,165.12 Mb/s.3. Present only in UltraScale-based cores supporting line rates up to 10,137.6, 12,165.12, or 24,330.24 Mb/s.4. Present only in UltraScale-based cores supporting line rates up to 24,330.24Mb/s with FEC Enabled mode.

Table 2-3: Status Code and Alarm Register

Bits Description

31-5 Reserved

4

Summary AlarmThe summary alarm bit is identical to the stat_alarm bit on the Status and Alarm interface. It is set whenever any of the following conditions occur:

• If the SDI bit or the Reset bit is set in the Transmit CPRI Alarms register.

• Local Loss Of Frame (LOF), Loss of Signal (LOS) or Remote Alarm Indication (RAI) bits set. A local LOF or LOS results in the LOF or LOS bit being set in the transmitted Z.130.0 bits respectively. A local LOF or LOS also causes a local RAI which is returned in the transmitted Z.130.0 RAI bit.

• LOF, LOS or RAI bit set in received Z.130.0. When any of these alarms are seen for the first time the core returns to carrying out L1 Synchronization and rate negotiation. If the alarm persists, a slave CPRI core can still become operational albeit with the summary alarm bit set. A master CPRI core also completes L1 synchronization and rate negotiation regardless of received alarms.

3-0

Status CodeThe Status Code indicates the current state of the core. It is identical to the stat_code port on the Status and Alarm interface. The status code ports are as follows:

0000: Reset0001: Attempting L1 synchronization0010: Protocol version setup0011: C&M parameter setup1011: Passive Mode1110: Interface and vendor-specific negotiation1111: Operational state: link is up

Note that stat_code keeps its previous value until the deassertion of reset.

Table 2-2: Management Register Addresses (Cont’d)

Address AXI Address Name Mode

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Current HDLC Rate Register (0x2)

Table 2-4: Miscellaneous Status Register

Bits Description

31-24 Major version

23-20 Minor version

19-16 Revision

15 Latched version of local loss of frame synchronization (LOF)

14 Latched version of local loss of signal (LOS)

13 Latched version of local RAI

12 Latched version of remote loss of frame synchronization (LOF)

11 Latched version of remote loss of signal (LOS)

10 Latched version of remote Service Access Point (SAP) Defect Indication

9 Latched version of remote RAI

8 Latched version of remote Reset

7 When 1, core is a master port; when 0, core is a slave port.

6 When 1, core has been generated using a hardware evaluation license

5:2 Reserved

1 Local loss of frame synchronization(1)

0 Local loss of signal(1)

Notes: 1. Bits 0 and 1 are not latched and clear by themselves when LOS and LOF clear.

Table 2-5: Current HDLC Rate Register

Bits Description

31-3 Reserved

2-0

Current HDLC Rate Encoding000: No HDLC channel001: 240 kb/s010: 480 kb/s011: 960 kb/s100: 1,920 kb/s101: 2,400 kb/s110: Highest possible HDLC bit rate for line rates above 3,072.0 Mb/s.

3,840 kb/s when core is operating at 4,915.2 Mb/s4,800 kb/s when core is operating at 6,144.0 Mb/s7,680 kb/s when core is operating at 8,110.08, 9,830.4, 10,137.6, 12,165.12, and 24,330.24 Mb/s

111: User defined HDLC rate

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Current Ethernet Pointer Register (0x3)

Received Subchannel 2, Word 0 Register (0x4)Received value of control word Z.2.0. See CPRI Specification v7.0 [Ref 1], Section 4.2.7.6, “L1 Inband Protocol.”




Transceiver Loopback and Ethernet Reset Request Register (0x8)

Table 2-6: Current Ethernet Pointer Register

Bits Description

31-6 Reserved

5-0 Current Ethernet pointer. Value from 20 to 63, where 20 is the highest bandwidth, or 0 if a passive link is required, or is in operation.

Table 2-7: Transceiver Loopback and Ethernet Reset Request Register

Bits Description

31-4 Reserved

3:2

Loopback (defaults to 00)

00: Normal Operation10: Near-end physical medium attachment (PMA) Loopback01,11: Reserved

1 Reset the Ethernet receive block. Although this bit is writable, it is always read as 0 as the reset is immediate.

0 Reset the Ethernet transmit block. Although this bit is writable, it is always read as 0 as the reset is immediate.

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Transceiver Barrel Shift Position Register(0x9)

Preferred HDLC Rate Register (0xA)

Preferred Ethernet Pointer Register (0xB)

Current Line Speed Register (0xC)

Table 2-8: GTP/GTX Transceiver Barrel Shift Position Register

Bits Description

31-7 Reserved

6-0 Current position of the transceiver receive barrel shifter. See R21 Calculation for more details.

Table 2-9: Preferred HDLC Rate Register

Bits Description

31-13 Reserved

12:3 HDLC byte valid vector. These bits provide support for the user-defined HDLC rate, see Table 2-5. The vector value indicates which bytes in the HDLC codeword contain valid data.

2:0

The preferred HDLC rate for the link. This sets the initial value the core uses in negotiating a common rate with a peer. To ensure correct operation it should be set before link initialization. Typically, this is achieved by disabling the core through the line-speed capability register. For valid values, see Table 2-5. Defaults to 480 kb/s.

Table 2-10: Preferred Ethernet Pointer Register

Bits Description

31-6 Reserved

5:0

The preferred value of the Ethernet pointer.

The preferred value is used by the core in negotiating a common rate with its peer. The value must be between 20 and 63 decimal, where 20 is the highest bandwidth, or 0 to indicate no Ethernet channel. To ensure correct operation it should be set before link initialization. Typically this is achieved by disabling the core through the line speed capability register. Defaults to 20 in non-ORI cores and to 53 in cores supporting ORI.

Table 2-11: Current Line Speed Register

Bits Description

31-15 Reserved

14 24,330.24 Mb/s FEC Enabled Mode (GTYE3 or GTYE4 only)




10 24,330.24 Mb/s (GTYE3 or GTYE4 only)

9 12,165.12 Mb/s

8 8,110.08 Mb/s

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Line Speed Capability Register (0xD)The bits in this register define the line speeds that the core should use.

7 10,137.6 Mb/s

6 9,830.4 Mb/s

5 6,144.0 Mb/s

4 4,915.2 Mb/s

3 3,072.0 Mb/s

2 2,457.6 Mb/s

1 1,228.8 Mb/s

0 614.4 Mb/s

Table 2-12: Line Speed Capability Register

Bits Description

31-15 Reserved

14 Capable of 24,330.24 Mb/s FEC Enabled Mode




10 Capable of 24,330.24 Mb/s










Table 2-11: Current Line Speed Register (Cont’d)

Bits Description

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Table 2-13 shows the defaults for the Line Speed Capability Register, depending on the speed capability that is selected.

General Configuration and Transmit CPRI Alarms Register (0xE)

0 Capable of 614.4 Mb/s

Notes: 1. Setting 000 0000 0000 0000 disables the core.2. In cores that do not support 6,144.0 Mb/s operation, writes to bits 4 through 14 are ignored. In cores that do not

support 9,830.4 Mb/s operation, writes to bits 6 through 14 are ignored. In cores that do not support 10,137.6 Mb/s operation, writes to bits 7 through 14 are ignored. In cores that do not support 12,165.12 Mb/s operation, writes to bits 8 through 14 are ignored. In cores that do not support 24,330.24 Mb/s operation, writes to bits 10 through 14 are ignored.In cores that do not support FEC operation, writes to bits 11 through 14 are ignored.

Table 2-13: Line Speed Capability Register Defaults

Core Speed Capability Line Speed Capability Register (0xD) Default

24,330.24 Mb/s368.64 MHz reference clock: 000 0111 0000 0000

245.76 MHz reference clock: 000 0111 1111 1111

24,330.24 Mb/s with FEC368.64 MHz reference clock: 111 1111 0000 0000

245.76 MHz reference clock: 111 1111 1111 1111

12,165.12 Mb/s368.64 MHz reference clock: 000 0011 0000 0000

307.20 and 245.76 MHz reference clock: 000 0011 1111 1111

10,137.6 Mb/s 000 0000 1111 1111

9,830.4 Mb/s 000 0000 0111 1111

6,144.0 Mb/s 000 0000 0011 1111

4,915.2 Mb/s 000 0000 0001 1111

3,072.0 Mb/s 000 0000 0000 1111

Table 2-14: General Configuration and Transmit CPRI Alarms Register

Bits DefaultValue Description

31 0

Software resetWhen set to 1 the core performs a reset. The bit reads back a 1 while reset is in progress and 0 when complete. The reset is considered complete when clk_ok is asserted. The software reset does not affect the other management register settings.

clk_ok remains Low until a valid line rate is selected by the core. Setting the line speed capability register to 0 does not disable the management interface.

30:29 N/A Reserved

Table 2-12: Line Speed Capability Register (Cont’d)

Bits Description

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28 1GMII modeIf the GMII interface is selected and this field is set to 1 then 8-bit GMII data is transferred over the GMII interface. If this field is set to 0 4-bit MII data is transferred.

27:24 5Ethernet Jam Byte CountIf Ethernet Receiver Ignores TX_EN is FALSE, this field defines the number of bytes the core asserts the eth_rx_er signal on the Ethernet interface. Valid values: 1 to 15.

23:20 12

Ethernet Gap Byte CountIf the Ethernet Gap in C&M Channel bit (bit 17) is set to 1, this field defines the number of bytes of Interframe Gap. The valid range is 3 to 15. This functionality is not supported when the GMII interface is selected.

19 1Ethernet Transmitter Ignores RX_DVWhen set to 0, the core asserts eth_col if eth_tx_en is asserted at the same time as eth_rx_dv. When set to 1, eth_col does not depend on the state of eth_rx_dv.

18 1

Ethernet Receiver Ignores TX_ENWhen set to 0, the core does not attempt to source a frame on the Ethernet receive interface if a transmission is in progress (true half-duplex). When set to 1, the receiver ignores the transmitter and sources a frame on the receive interface if one is available.

17 1

Ethernet Gap in C&M ChannelWhen set to 1, the core inserts Ethernet interpacket gaps across the CPRI fast C&M channel. When set to 0, the core does not insert interpacket gaps on the CPRI Fast C&M channel but sends frames as fast as they are supplied on the Ethernet interface.

16 1

HDLC Rate AdaptationWhen set to 1, the enable for the transmit data and the valid signals for the receive data are pulsed High at regular intervals. This maintains the average HDLC data rate negotiated at start-up. When set to 0, the core outputs enable and valid signals that frame a burst of HDLC data. The length of the burst is dependent on the HDLC rate negotiated at start-up.

15 0Sync Header ReversalWhen set to 1 the txheader(1:0) and rxheader(1:0) bits are reversed if 64B66B encoding is enabled.

14:9 N/A Reserved

8 0

Slave Transmit EnableWhen the Slave Transmit Enable bit is set to 0, the slave does not turn on its transmitted output until HFNSYNC is achieved. When set to 1, the slave does turn on its transmitted output immediately on start-up. This bit is read when the design enters the L1 synchronization state.

7:3 N/A Reserved

2 0 SAP Defect Indicator (SDI)

Table 2-14: General Configuration and Transmit CPRI Alarms Register (Cont’d)


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R21 Timers Register (0xF)

See Delay Measurement and Requirement 21 (R21).

Current Protocol Version Register (0x10)

1 N/A Reserved

0

Reset (Downlink—Request, Uplink—Acknowledge)When this bit is set to 1 on a core configured as a Master, a 1 is transmitted in the reset bit of control word Z.130.0 of the outbound CPRI frame. When the Reset bit is then set to 0, the core continues to transmit a 1 for the Z.130.0 reset bit for 10 Hyperframes and then reverts to transmitting 0.

When the core is configured as a slave, setting this bit to 1 causes the Reset bit in Z.130.0 to be asserted as reset acknowledge. After a 0 is written the core transmits a 1 for the Z.130.0 Reset bit for 5 Hyperframes and then reverts to transmitting 0.

Other than obeying the requirements specified previously for performing two writes on the management interface (that is, wait for mgmnt_ack and then deassert mgmnt_req signal for at least one clock cycle before starting a subsequent write) there is no delay requirement between writing 1 and writing 0 to the Reset bit, bit 0.

See section 4.2.7.6.1 of CPRI specification 7.0 [Ref 1] for more information.

Table 2-15: R21 Timers Register

Bits Description

31-18 FIFO transit time value

17:0 Coarse timer value

Table 2-16: Current Protocol Version Register

Bits Description

31-8 Reserved

7:0 Current protocol version

Table 2-14: General Configuration and Transmit CPRI Alarms Register (Cont’d)


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Preferred Protocol Version Register (0x11)

RECOMMENDED: It is strongly recommended that scrambling is enabled at line rates of 4,915.2 Mb/s and over. At 8,110.08, 10,137.6, 12,165.12, and 24,330.24 Mb/s, scrambling is always enabled as part of the 64b/66b protocol.

Scrambler Seed Register (0x12)

Descrambler Seed Register (0x13)

Transmit FIFO Transit Time Register (0x14)

See Delay Measurement and Requirement 21 (R21).

Table 2-17: Preferred Protocol Version Register

Bits Description

31-8 Reserved

7:0

Preferred Protocol VersionAt speeds of 3,072.0 Mb/s and under and at 10,137.6 Mb/s, 12,165.12, and 24,330.24 Mb/s, protocol version 1 is supported. At other speeds protocol versions 1 and 2 are supported. Default is protocol version 2.

At line rates of 4,915.2, 6,144.0 and 9,830.4 Mb/s data scrambling is enabled when the protocol version on the link has been negotiated to version 2 and there is a non-zero value programmed into the Scrambler Seed register at address 0x12. To ensure correct operation it should be set before link initialization. Typically this is achieved by disabling the core through the line speed capability register.

Table 2-18: Scrambler Seed Register

Bits Description

31 Reserved

30:0 If the protocol on the CPRI link is set to 2, the data is scrambled by a side-stream scrambler prior to encoding. This field sets the seed value that the scrambler is initialized to.

Table 2-19: Descrambler Seed Register

Bits Description

31 Reserved

30:0 This field holds the received seed value when the protocol on the CPRI link is set to 2. If the protocol version is set to 1 on the link, this field is invalid.

Table 2-20: Transmit FIFO Transit Time Register

Bits Description

31:14 Reserved

13:0 Transmit FIFO transit time.

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Watchdog Timeout Value Register (0x15)

Gearbox Latency Register (0x16)

In UltraScale-based cores operating at line rates of 8,110.08, 10,137.6, 12,165.12, and 24,330.24 Mb/s, the asynchronous gearbox is used to implement 64b66b encoding. The latency through the transmit and receive gearboxes is reported using this register.

See the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 4] and UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 5] for more information on the asynchronous gearbox. The value is reported in units of 1/8 of a UI.

FIFO Fill Level Register (0x17)

Table 2-21: Watchdog Timeout Value Register

Bits Description

31:0

Watchdog Timeout ValueA timer in the core resets the transceiver after a certain amount of time has passed with no valid data received. This register holds the number of management clock cycles for the timer to wait before resetting the core. With a management clock speed of 125 MHz, the register times out after around 4 ms by default. Setting the register to all zeros disables the timer.

Table 2-22: Gearbox Latency Register

Bits Description

31:16 Receiver Gearbox Latency

15:0 Transmitter Gearbox Latency

Table 2-23: FIFO Fill Level Register

Bits Description

31:7 Reserved

6:0

FIFO Fill LevelIn master cores the starting level of the clock-domain crossing (CDC) FIFO can be set using this register. By default the CDC FIFO fills to half way (fill level = 64) before reading is enabled. To reduce latency, at the expense of reduced cable length support, the FIFO fill level can be reduced.

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General Debug Register (0x18)This register holds debug information on the state of the received L1 in-band protocol words. In addition an error in the CDC FIFO is flagged.

High Resolution FIFO Transit Time—Integer Part Register (0x19)The integer part of the receiver CDC FIFO transit time. See Delay Measurement and Requirement 21 (R21).

High Resolution FIFO Transit Time—Fractional Part Register (0x1A)The fractional part of the receiver CDC FIFO transit time. See Delay Measurement and Requirement 21 (R21).

FEC Status Register (0x1B)

Table 2-24: General Debug Register

Bits Description

31:4 Reserved

3 CDC FIFO Error

2 Invalid Ethernet Pointer Received

1 Invalid HDLC Rate Received

0 Invalid Protocol Received

Table 2-25: High Resolution FIFO Transit Time—Integer Part Register

Bits Description

31:7 Reserved

6:0 FIFO transit time (Integer part)

Table 2-26: High Resolution FIFO Transit Time—Fractional Part Register

Bits Description

31:16 Reserved

15:0 FIFO transit time (Fractional part)

Table 2-27: FEC Status Register

Bits Description

31:11 Reserved

10:8stat_symbol_errorsIndicates the number of symbol errors corrected in each codeword.

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FEC CW Count Register (0x1C)

FEC Corrected CW Count Register (0x1D)

FEC Uncorrected CW Count Register (0x1E)

7:1

stat_rx_delayIndicates the fraction of a clock cycle delay that is added to the RX datapath latency by the FEC input gearbox. A value of 0 means no additional delay, a value of 65 means 65/66 of a clock cycle is being added.

0stat_rx_align_statusWhen High this signal indicates that alignment to the incoming codeword boundary position has been achieved and the receiver is accepting and processing data.

Table 2-28: FEC CW Count Register

Bits Description

31:0CW Count Indicates the number of received RS-FEC codewords.

Table 2-29: FEC Corrected CW Count Register

Bits Description

31:0Corrected CW CountIndicates the number of corrected RS-FEC codewords.

Table 2-30: FEC Uncorrected CW Count Register

Bits Description

31:0Uncorrected CW CountIndicates the number of uncorrected RS-FEC codewords.

Table 2-27: FEC Status Register (Cont’d)

Bits Description

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Chapter 3

Designing with the CoreThis chapter provides a general description of how to use the CPRI™ core in your designs and also describes specific core interfaces.

General Design GuidelinesThis section describes the steps required to turn a CPRI core into a fully-functioning design with user-application logic. Not all implementations require all the design steps listed in this chapter. However, it is important to carefully follow the logic design guidelines in this guide.

Use the Example Design as a Starting PointEach instance of the CPRI core created by the IP Catalog is delivered with an example design that can be implemented in an FPGA and simulated. This design can be used as a starting point for your own design or can be used to debug your application in the event of difficulty.

See Chapter 6, Example Design for information about using and customizing the example designs for the CPRI core.

Know the Degree of DifficultyCPRI designs are challenging to implement in any technology and the degree of difficulty is further influenced by:

• maximum system clock frequency

• nature of your application

All CPRI implementations need careful attention to system performance requirements. Pipelining, logic mapping, placement constraints, and logic duplication are all methods that help boost system performance.

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Chapter 3: Designing with the Core

Keep It RegisteredTo simplify timing and increase system performance in an FPGA design, keep all inputs and outputs registered between your application and the core. This means that all inputs and outputs from your application should come from or connect to a flip-flop. While registering signals cannot be possible for all paths, it simplifies timing analysis and makes it easier for the Xilinx tools to place-and-route the design.

Recognize Timing Critical SignalsThe XDC provided with the example design identifies critical signals and timing constraints that should be used. Constraining the Core contains detailed information about the use of these signals.

Use Supported Design FlowsThe core is delivered to you as encrypted RTL in the Vivado® Design Suite. The Vivado synthesis tool is supported for the synthesis of the encrypted RTL and the associated wrapper files. Post-synthesis, only Vivado Design Suite is supported.

Make Only Allowed ModificationsThe CPRI core is not user-modifiable. Do not make modifications as they can have adverse effects on system timing and protocol compliance. Supported configurations of the CPRI core can only be made by selecting the options from within the IP catalog when the core is generated. See Chapter 5, Design Flow Steps.

Clocking and ResetsThis section lists the clock and reset ports of the CPRI core. Chapter 4, Design Considerations contains detailed descriptions of the clocking for each device family.

The datapath clocks are generated in the clocking block in the core support layer. This leads to some differences in the core level clocking ports between designs that are generated with the core support layer and those that are generated without. For more information on the core support layer see CPRI Core Structure.

Table 3-1 lists the clock and reset ports that are common to both support layer configurations of the core.

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Table 3-1: Clock and Reset Signals (All Cores)

Port Direction Description

reset In

Active-High asynchronous reset for the core and the management interface. This reset is synchronized to each clock domain in the core. Asserting this input resets both the core and the configuration registers. To reset the core without changing the configuration registers a soft reset can be used (see General Configuration and Transmit CPRI Alarms Register (0xE)).

refclk In Transceiver reference clock input. Generated from the transceiver differential reference clock input by an IBUFDS in the user design.

refclk_307 InTransceiver 307.2 MHz reference clock input. In 7 series and GTHE3-based cores that support 12,165.12 Mb/s a second reference clock is required in order to support all the line rates.

tx_refclk InArtix®-7 cores supporting a free running receive clock only. Transceiver reference clock input from a crystal oscillator by an IBUFDS. Used to drive PLL1 in the GTPE2_COMMON component.

aux_clk/s_axi_aclk In

Management clock in the range 10-125 MHz. When the AXI4-Lite Management Interface option is selected, the management interface is clocked by the s_axi_aclk input from the AXI4-Lite bus. When the generic management interface is used, the aux_clk input is used to clock the management interface. See Customizing and Generating the Core for more information. In addition to the management interface this clock also drives the blocks programming the Dynamic Reconfiguration Port (DRP) ports of the GT transceiver and the internal Phase-Locked Loops (PLLs) used for clock synthesis. This clock must run continuously without interruption as the GT transceiver and PLLs are reconfigured during speed switches. This clock can be shared between multiple instances of the CPRI core.

reset_aux_clk/s_axi_aresetn In

Management Interface reset. Asserting this signal resets the management sections of the design.reset_aux_clk is for generic management interface, s_axi_aresetn is generated when the AXI4-Lite Management interface option is selected.

gtwiz_reset_clk_freerun_in In

UltraScale™ architecture-based devices only. Clock for the transceiver reset state machine in the core. This free running clock must have a frequency lower than that of the system clock when running at the lowest supported line rate, for example 15.36 MHz for 32-bit cores supporting 614.4 Mb/s. This clock can be shared between multiple cores.

hires_clk In

High resolution sampling clock used to measure the transmit time of the clock-domain crossing FIFO(s). Must be at least

150 MHz when operating at speeds of 2,457.6 Mb/s and under 175 MHz for 3,072 Mb/s operation275 MHz for 4,915.2 Mb/s operation, 325 MHz for operation at 6,144 and 9,830.4 Mb/s380 MHz for operation at 8,110.08, 10,137.6, 12,165.12 and 24,330.24 Mb/s.

The clock should not be derived from the same source as refclk; it must be unrelated. This clock can be shared between multiple instances of the CPRI core.

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Table 3-2 lists the clock and reset ports that are exclusive to designs generated with the core support layer. These are generated by the clocking circuitry in the support layer and output for use in the user design. The clocks from the PLL in the common block are also routed out of the core. These can be shared by other transceivers in the quad. See Transceiver Interface for a description of these clocks.

Table 3-3 lists the clock and reset ports that are exclusive to designs generated with the core support layer in the example design rather than in the core. The clock inputs are

hires_clk_ok In High resolution clock OK. Signal indicating the status of the high resolution clock. Set High when the clock is stable.

eth_ref_clk InEthernet clock running at 25 MHz. When the MII interface is selected, this clock is used to clock the Ethernet interface. This should also be used to clock the client logic attached to this interface.

eth_tx_clk In

Ethernet transmit clock running at 125 MHz. When the GMII interface is selected, this clock is used to clock the transmit side of the Ethernet interface. This should also be used to clock the client logic attached to the transmit interface.

eth_rx_clk In

Ethernet receive clock running at 125 MHz. When the GMII interface is selected, this clock is used to clock the receive side of the Ethernet interface. This should also be used to clock the client logic attached to the receive interface.

rxrecclkout Out

In UltraScale and UltraScale+ based designs the RXRECCLKOUT port of the transceiver can be routed out of the device directly. This port can be connected to an OBUFDS_GTE3 or OBUFDS_GTE4 as shown in the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 4] and the UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 5]

Table 3-2: Clock and Reset Signals (Support Layer Generated in the Core)


clk_out Out

System clock. Used for all datapath logic in the core and to clock the I/Q, frame and synchronization, HDLC and vendor-specific interfaces. The same clock should be used to clock client logic attached to these interfaces. See Table 2-1 for the core clock rates.

clk_ok_out Out System clock OK. Signal indicating the status of the system clock. High when the clock is stable.

recclk OutRecovered clock from the GT transceiver. When the design is operating as a slave, a clean-up PLL should be used to generate the transceiver reference clock from the recclk output.

recclk_ok Out Recovered clock OK. Signal indicating the status of the recovered clock. High when the clock is stable.

gt_reset_req_out Out

Present on GTXE2, GTHE2 and GTPE2 implementations. Signal from the clocking logic in the core support layer that is asserted to reset the transceiver. This is asserted on startup and after a line rate change on the CPRI link. Used to reset transceivers that share the clocking logic in the core.

Table 3-1: Clock and Reset Signals (All Cores) (Cont’d)


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generated by the clocking circuitry in the support layer. The core also outputs some clocks and control signals to the clocking block. The clocks from the PLL in the common block are also routed in to the core. See Transceiver Interface for a description of these clocks.

Table 3-3: Clock and Reset Signals (Support Layer Generated in the Example Design)


txoutclk Out Transmit output clock from the GT transceiver. This is used to generate the system clock.

clk_in In

System clock. Used for all datapath logic in the core and to clock the I/Q, frame and synchronization, HDLC and vendor-specific interfaces. The same clock should be used to clock client logic attached to these interfaces. See Table 2-1 for the core clock rates.

clk_316_in In

Present on GTXE2 and GTHE2 implementations supporting 10,137.6 or 12,165.12 Mb/s only. This is the transceiver TX user clock. At line rates using 8B10B encoding it runs at the same frequency as clk_in. When 64B66B encoding is enabled it runs at 66/64th of the clk_in frequency.

At 12,165.12 Mb/s the frequency is 380.16 MHz; at 10,137.6 Mb/s it is 316.8 MHz and at 8,110.08 Mb/s it is 253.44 MHz.

See Clock Configuration.

txusrclk InArtix-7 and 24,330.24 Mb/s capable UltraScale and UltraScale+ based cores only. Transceiver TXUSRCLK input. Clock running at double the speed of clk_in. See Clock Configuration.

clk_ok_in In System clock OK. Signal indicating the status of the system clock. Drive High when the clock is stable.

rxoutclk Out Receive output clock from the GT transceiver. This is used to generate the recovered clock input.

recclk_in In Recovered clock input for the GT transceiver.

recclk_ok Out Recovered clock OK. Signal indicating the status of the recovered clock. High when the transceiver has completed receiver reset and alignment.

gt_reset_req In

Present on GTXE2, GTHE2 and GTPE2 implementations. Signal from the clocking logic in the core support layer that is asserted to reset the transceiver. This is asserted on startup and after a line rate change on the CPRI link.

mmcm_rst Out

MMCM Reset. A High on this signal holds the MMCM in the clocking block in reset until txoutclk is stable.mmcm_rst can be used to reset both the core and management interface. When mmcm_rst is asserted, the stat_code value is 0.

txresetdone_out Out Signal from the core indicating that the transceiver reset sequence is complete. The core is held in reset until this signal is asserted.

gtreset_sm_done Out

Present on GTHE2, GTPE2, UltraScale and UltraScale+ implementations. Signal from the core to indicate that the transceiver reset procedure has been completed. This is used by the clocking block to prevent a speed change during a reset cycle.

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Interfacing to the CoreThis section provides information about the data, status and transceiver interfaces and includes instructions for connecting them to the CPRI core. In the following timing diagrams clk refers to the system clock, as described in Clocking and Resets.

Data Interfaces

I/Q Interface

The I/Q interface of the CPRI core gives direct access to the multiplexed and mapped I/Q data stream as it appears on the CPRI link. As such, use of this interface requires detailed knowledge of the CPRI mapping protocol in use by the designer; however, it is an extremely flexible and powerful interface to use for transporting I/Q data.

Three I/Q data adapter modules are also delivered with the core example design: I/Q multiplexers that support the UTRA-FDD and E-UTRA sample mappings described in the CPRI specification and a legacy raw I/Q module to match the raw I/Q interface timing of v1.2 and earlier of the CPRI core.

The ports shown in Table 3-4 are used to pass I/Q data.

userclk_tx_reset Out Present in GTHE3/GTYE3/GTHE4/GTYE4 implementations only. Reset for the transmit clock BUFG_GT in the clocking logic.

userclk_rx_reset Out Present in GTHE3/GTYE3/GTHE4/GTYE4 implementations only. Reset for the receive clock BUFG_GT in the clocking logic.

Table 3-4: I/Q Interface Signals

Port Direction Clock Domain Description

iq_tx In System Clock

Transmit I/Q data. Synchronous to clk. 64 bits wide when the 64-bit datapath option is selected; 32-bits wide when the 32-bit datapath option is selected; 16-bits wide otherwise.

iq_tx_enable Out System Clock Transmit enable indicating the start of a new Tc.

iq_rx Out System Clock

Receive I/Q data. Synchronous to clk. 64 bits wide when the 64-bit datapath option is selected; 32-bits wide on when the 32-bit datapath option is selected; 16-bits wide otherwise.

basic_frame_first_word Out System Clock Indicates the start of a new basic frame, asserted once every Tc.

Table 3-3: Clock and Reset Signals (Support Layer Generated in the Example Design) (Cont’d)


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The signal basic_frame_first_word marks the start of a new basic frame. The signal iq_rx is sampled on the rising edge of clk. A basic frame at 614.4 Mb/s is 16 bytes in length, with the first byte being the control word. The control word, denoted as XX in Figure 3-1 is ignored and can be any value. Bytes are sent out in the basic frame in the following order:

XX, 00, 11, 22, 33 …

Similarly for the receive interface at 614.4 Mb/s:

The signal basic_frame_first_word marks the start of a new basic frame. The signal iq_rx is sampled on the rising edge of clk. The control word data, present in the first byte at 614.4 Mb/s should be ignored. Bytes are received in the basic frame in the following order:

cw, 00, 11, 22, 33 …

Other speeds follow a similar format. The length of the basic frame and the control word is expanded. For 1,228.8 Mb/s, the basic frame is 32 bytes in length, and the first two bytes are the control word. For 2,457.6 Mb/s, the basic frame is 64 bytes in length, and the first four bytes are the control word.

For 3,072 Mb/s, the basic frame is 80 bytes in length and the first five bytes are the control word. At 4,915.2 Mb/s the basic frame is 128 bytes in length and the first 8 bytes are the control word. At 6,144.0 Mb/s the basic frame is 160 bytes in length and the first 10 bytes are the control word. Figures 3-2 through 3-12 illustrate the 16-bit wide I/Q Transmit and Receive Interfaces at a range of speeds.


Figure 3-1: 16-Bit Wide I/Q Transmit Interface at 614.4 Mb/s


Figure 3-2: 16-Bit Wide IQ Receive Interface at 614.4 Mb/s

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Figure 3-3: I/Q Transmit Interface at 1,228.8 Mb/sX-Ref Target - Figure 3-4

Figure 3-4: I/Q Receive Interface at 1,228.8 Mb/sX-Ref Target - Figure 3-5





Figure 3-9: I/Q Transmit Interface at 4,915.2 Mb/s

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When the 32-bit datapath option is selected, the I/Q data bus is widened to 32 bits. The data transfers follow a similar format to the 16-bit I/Q interface; however, 4 bytes of data are input and output on each clock period. The basic frame is 4 clock periods long at 614.4 Mb/s, 8 clock periods at 1,228.8 Mb/s, 16 clock periods at 2,457.6 Mb/s, 20 clock periods at 3,072.0 Mb/s, 32 clock periods at 4,915.2 Mb/s, 40 clock periods at 6,144.0 Mb/s, and 64 clock periods at 8,110.08 Mb/s and 9,830.4 Mb/s. The control word is 16 bytes long at 8,110.08 Mb/s and 9,830.4 Mb/s. Figure 3-13 and Figure 3-14 illustrate the 32-bit wide I/Q Transmit and Receive Interfaces at 8,110.08 Mb/s and 9,830.4 Mb/s.

When the core is configured to run at 10,137.6 Mb/s, the 32 bit I/Q data bus is used. As with 8,110.08 Mb/s and 9,830.4 Mb/s, the control word is 16 bytes long. The basic frame is extended to be 80 clock periods long. Figure 3-15 and Figure 3-16 illustrate the I/Q transmit and receive interfaces at 10,137.6 Mb/s.




Figure 3-12: I/Q Receive Interface at 6,144.0 Mb/s


Figure 3-13: 32-Bit Wide Transmit Interface at 8,110.08 Mb/s and 9,830.4 Mb/sX-Ref Target - Figure 3-14

Figure 3-14: 32-Bit Wide Receive Interface at 8,110.08 Mb/s and 9,830.4 Mb/s

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When the core is configured to run at 12,165.12 Mb/s, the 32-bit I/Q data bus is used. As with 8,110.08, 9,830.4 and 10,137.6 Mb/s the control word is 16 bytes long. The basic frame is extended to be 96 clock periods long. Figure 3-17 and Figure 3-18 illustrate the I/Q transmit and receive interfaces at 12,165.12 Mb/s.

When the core is configured to run at 24,330.24 Mb/s a 64-bit I/Q data bus is used. The basic frame at the highest speed is 96 cycles long. The 24,330.24 Mb/s core can also operate at 12,165.12 Mb/s and 8,110.08 Mb/s. At these speeds the basic frame is 48 and 32 cycles long respectively. The control word is always 16 bytes long. Figure 3-19 and Figure 3-20 show the I/Q transmit and receive interfaces at 24,330.24 Mb/s.


Figure 3-15: 32-Bit Transmit Interface at 10,137.6 Mb/sX-Ref Target - Figure 3-16

Figure 3-16: 32-Bit Receive Interface at 10,137.6 Mb/s




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UTRA-FDD I/Q Module

This module (contained in iq_module.vhd) allows you to multiplex and interleave I/Q samples using the UTRA-FDD mapping defined in the CPRI specification. It multiplexes and de-multiplexes up to 48 channels of I and Q data, one sample per basic frame period. The existence and width of each channel is configurable at synthesis time.

The generics of the UTRA-FDD I/Q Module are described in Table 3-5.




Table 3-5: UTRA-FDD I/Q Module Generics

Name Type Description

C_TX_WIDTH_n NaturalTotal width of I/Q channel n (n = 1…48), transmit side. When set to 0, channel is disabled.

Legal values are 4–20 for active channels and 0 for inactive channels.

C_RX_WIDTH_n NaturalTotal width of I/Q channel n (n = 1…48), receive side. When set to 0, channel is disabled.

Legal values are 4–20 for active channels and 0 for inactive channels.

C_TX_START_n NaturalDetermines the bit position of the nth I/Q channel in each basic frame, transmit side. Bit 0 is the first bit after the control word. Maximum bit number depends on the I/Q channel widths and line rate.

C_RX_START_n NaturalDetermines the bit position of the nth I/Q channel in each basic frame, receive side. Bit 0 is the first bit after the control word. Maximum bit number depends on the I/Q channel widths and line rate.

Table 3-6: UTRA-FDD I/Q Module Signals - Core Interface


iq_tx_enable In System Clock Transmit enable indicating the start of a new Tciq_tx Out System Clock IQ Transmit Data

iq_rx In System Clock IQ Receive Data

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All ports of the transmit interface are synchronous to clk and connected user logic should also be clocked by clk. The enable signal iq_tx_enable is asserted by the core for exactly one cycle of clk for every Tc in time. The UTRA-FDD I/Q Module samples all iq_tx ports following assertion of the iq_tx_enable signal. Figure 3-21 illustrates this timing.

The de-multiplexer receive interface is similar to the transmit interface described previously. All ports of the receive interface are also synchronous to clk. The ports are described in Table 3-8.

The iq_rx_data_valid signal indicates when the I/Q data is valid and is asserted by the module once every Tc, as shown in Figure 3-22.

basic_frame_first_word In System Clock Start of new basic frame asserted once every Tc

speed_select In System Clock Current Line Rate. Connect to stat_speed output of CPRI core.

Table 3-7: UTRA-FDD I/Q Module Signals - Transmit Interface


iq_tx_i_n[C_TX_WIDTH_n-1:0] In System Clock I data for transmit direction (n = 1…48).iq_tx_q_n[C_TX_WIDTH_n-1:0] In System Clock Q data for transmit direction (n = 1…48).


Figure 3-21: UTRA-FDD I/Q Module Transmit Timing - Client Interface

Table 3-8: UTRA-FDD I/Q Module Signals - Receive Interface


iq_rx_data_valid Out System Clock Receive Data Valid asserted once every Tciq_rx_i_n[C_RX_WIDTH_n-1:0] Out System Clock I data for receive direction (n = 1…48)iq_rx_q_n[C_RX_WIDTH_n-1:0] Out System Clock Q data for receive direction (n = 1…48)

Table 3-6: UTRA-FDD I/Q Module Signals - Core Interface (Cont’d)


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In this multiplexer I/Q Channel Configuration example the core is configured as follows:

• Transmit:

° I/Q sample width: 16

° Over-sampling ratio: 1

° AxC containers: 3

• Receive:

° I/Q sample width: 5

° Over-sampling ratio: 2

° AxC containers: 3

To set up this configuration, the generics should be set as follows.

C_TX_WIDTH_1 = 16; -- AxC container 1C_TX_START_1 = 0;C_TX_WIDTH_2 = 16; -- AxC container 2C_TX_START_2 = 32; -- because channel 1 has 16 bits I data and 16

-- bits Q dataC_TX_WIDTH_3 = 16; -- AxC container 3C_TX_START_3 = 64;C_TX_WIDTH_n = 0; -- n = 4..48 all emptyC_RX_WIDTH_1 = 10; -- AxC container 1, 2 samplesC_RX_START_1 = 0;C_RX_WIDTH_2 = 10; -- AxC container 2, 2 samplesC_RX_START_2 = 20;C_RX_WIDTH_3 = 10; -- AxC Container 3, 2 samplesC_RX_START_3 = 40;C_RX_WIDTH_n = 0; -- n = 4..48 all empty

The transmit data sources should then be connected to the correct iq_tx_* ports and the receive data sinks should be connected to the iq_rx_* ports; in the receive case, the first sample should be connected to bits 4 down to 0 and the second sample connected to bits 9 down to 5, and so on.


Figure 3-22: UTRA-FDD I/Q Module Receive Timing - Client Interface

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Consider the number of data bytes in the basic frame when setting the size and start positions of the channels. The size of the data section of each basic frame varies from 15 bytes at 614.4 Mb/s to 240 bytes at 9,830.4 Mb/s, 308 bytes at 10,137.6 Mb/s, 368 bytes at 12,165.12 Mb/s and 752 bytes at 24,330.24 Mb/s. You should ensure that the channel start positions plus two times the channel width (I plus Q data) do not exceed the number of bits in the basic frame at the operating line speed. If this is not the case for a particular channel, the data for that channel will not be correctly transmitted or received.

E-UTRA I/Q Module

The E-UTRA IQ module (contained in iq_module_eutra.vhd) provides E-UTRA I/Q multiplexing and de-multiplexing as defined in the CPRI Specification v7.0 [Ref 1]. The module is implemented as a wrapper around the UTRA-FDD I/Q Module, enabling the transmission and reception of multiple samples per channel. It multiplexes and de-multiplexes up to eight channels each with up to eight samples per basic frame period. The existence, width, and number of samples in each channel are configurable at synthesis time. The generics of the E-UTRA I/Q Module are described in Table 3-9.

Table 3-9: E-UTRA I/Q Module Generics

Name Type Description

C_TX_S_n Natural Number of samples in IQ channel n (n=1…8) in the output CPRI stream. Legal values are 1-8 for active channels and 0 for inactive channels.

C_TX_WIDTH_n Natural Width of transmit IQ channel n (n=1…8) in the output CPRI stream. Legal values are 4-20 for active channels and 0 for inactive channels.

C_RX_S_n Natural Number of samples in IQ channel n (n=1…8) in the input CPRI stream. Legal values are 1-8 for active channels and 0 for in

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CPRI v8.7 LogiCORE IP Product Guide (PG056) - Xilinx · 2019. 1. 13. · CPRI v8.7 8 PG056 October 5, 2016 Chapter 1: Overview License Type This Xilinx LogiCORE™ IP module is provided