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COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE 421)

DIGITAL ELECTRONIC FUNDAMENTALS (ECE 422)

Finite State Machine

A Finite State Machine, or FSM, is a computation model that can be used to simulate sequential

logic, or, in other words, to represent and control execution flow. Finite State Machines can be

used to model problems in many fields, including mathematics, artificial intelligence, games or

linguistics.

Definition

A Finite State Machine is a model of computation based on a hypothetical machine made of one

or more states. Only one single state of this machine can be active at the same time. It means the

machine has to transition from one state to another in to perform different actions.

A Finite State Machine is any device storing the state of something at a given time. The state

will change based on inputs, providing the resulting output for the implemented changes.

Finite State Machines come from a branch of Computer Science called “automata theory”. The

family of data structure belonging to this domain also includes the Turing Machine.

The important points here are the following:

We have a fixed set of states that the machine can be in

The machine can only be in one state at a time

A sequence of inputs is sent to the machine

Every state has a set of transitions and every transition is associated with an input and

pointing to a state

Other names for FSM:

State Machine

Synchronous State Machine (SSM)

Synchronous Finite State Machine (SFSM)

The term ‘synchronous’ indicate that the flip-flops are connected to the same clock. There is also

another type of state machine, which is the Asynchronous Finite State Machine, and it is not

discussed here.

There are two different approaches of state machine design called Moore model and Mealy

model.

INPUT OUTPUT RELATION

In Moore model circuit outputs,

also called primary outputs are

generated solely from secondary

outputs or memory values.

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In Mealy model circuit inputs, also

known as primary inputs combine

with memory elements to generate

circuit output.

Differences between Moore and Mealy models

Moore model Mealy model

Primary outputs are generated solely from

secondary outputs or memory values.

Primary inputs combine with memory

elements to generate circuit output.

The output depends only on present state

and not on input.

The output is derived from present state as

well as input.

Requires less number of states and thereby

less hardware to solve any problem.

Requires more number of states and thereby

more hardware to solve any problem.

Output is generated one clock cycle earlier. Output is generated one clock cycle after.

The output remains stable over entire clock

period and changes only when there occurs a

state change at clock trigger based on input

available at that time.

Glitches occur.

DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUIT

A sequence detector is a sequential state machine which takes an input string of bits and

generates an output 1 whenever the target sequence has been detected. In a Mealy machine,

output depends on the present state and the external input (x). Hence in the diagram, the

output is written outside the states, along with inputs. Sequence detector is of two types:

1. Overlapping

2. Non-Overlapping

In an overlapping sequence detector the last bit of one sequence becomes the first bit of next

sequence. However, in non-overlapping sequence detector the last bit of one sequence does not

become the first bit of next sequence.

Example shows the output for non-overlapping Mealy machine in detecting the sequence 101.

For non overlapping case

Input: 0 1 1 0 1 0 1 0 1 1 0 0 1

Output: 0 0 0 0 1 0 0 0 1 0 0 0 0 --- once sequence is detected, it reset to detect next sequence

For overlapping case

Input: 0 1 1 0 1 0 1 0 1 1 0 0 1

Output: 0 0 0 0 1 0 1 0 1 0 0 0 0 --- quite complex

SEQUENCE DETECTOR PROBLEM

The Problem:- Design a sequence detector that receives binary data stream at its input X and

signals when a combination ‘011’ arrives at the input by making its output Y high which

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otherwise remains low. Consider, data is coming from right i.e. the first bit to be identified is 1,

second1and third 0 from the input sequence.

The first step in a sequential logic synthesis problem is to convert this word description to State

Transition Diagram (State Diagram).

MOORE MODEL STATE MACHINE DESIGN

1) Input output relation

In Moore model circuit outputs, also called primary outputs are generated solely from

secondary outputs or memory value.

2) State transition diagram

Since the output is generated only from the state variables, the detector circuit is at state a when

initialized where none of the bit in input sequence is properly detected or the starting point of

detection.

Then if 1st bit is detected properly the circuit should be at a different state say, b.

Similarly, we need two more states say, c and d to represent detection of 2nd and 3rd bit in

proper order. When the detector circuit is at state d, output Y is asserted and kept high as long

as circuit remains in state d signalling sequence detection. For other states detect or output, Y=0.

STATE TRANSITION DIAGRAM MOORE MODEL

Each state and output is defined within a circle in state

transition diagram in the format s/V where s represents

a symbol or memory values identified with a state and

V represents the output of the circuit. An arrow sign

marks state transition following an input value 0 or I

that is written along the path. X represents the binary

data input from which sequence ‘011’ is to be detected.

Figure above shows the state transition diagram

following Moore model.

Initialized with a (if input x=0 - remain in same state a, if input x=1 go to next state b first bit (1)

is detected and output y=0).

State b (if input x=0 - go to initial state a, if input x=1 go to next state c second bit (1) is detected

and output y=0).

State c (if input x=0 - go to final state d third bit (0) is detected, if input x=1 remain in same state

c and output y=0).

State d (if input x=0 - go to initial state a, if input x=1 go to state b and repeat the sequence ie,

‘011011’ and output y=1).

STATE ASSIGNMENT FOR SEQUENCE DETECTOR

Assign each state a binary combination of memory values. For this design, minimum two flip-

flops (say A and B) are required to define the 4 states a, b, c, d.

The state assignments are as follows.

a: B=0, A=0 b: B=0, A=1 c: B=1, A=0 d: B=1, A=1

STATE SYNTHESIS TABLE

The next step in design process is to develop state synthesis table, also called circuit excitation

table or simply state table from state transition diagram. For m number of memory elements, 2m

number of different states in a circuit.

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Bn An

X 00 01 11 10

0 0 0 b 1

1 0 a b 1

JB= An X

KB= An

For flip-flop FFX entry, we use the universal map method as follows:

DESIGN EQUATIONS AND CIRCUIT DIAGRAM

In design equation we express flip-flop inputs as a function of present state, i.e. memory values

(here, B and A) and present input (here, X). This ensures proper transfer of the circuit to next

state. The design equations also give output (here, Y) equation in terms of state variables or

memory elements in Moore model and state variables together with input in Mealy model. Use

Karnaugh map technique to get a simplified form of these relations.

Figure below presents Karnaugh map developed from the state synthesis table and also shows

corresponding design equations. Logic circuit in the Figure below shows the sequence detector

circuit diagram developed from these equations.

Present

state

Next

stateFF Entry

0 0 0

0 1 a

1 0 b

1 1 1

Output FFB FFA

Bn An X Bn+1 An+1 Y

0 0 0 0 0 0 0 0

0 0 1 0 1 0 0 a

0 1 0 0 0 0 0 b

0 1 1 1 0 0 a b

1 0 0 1 1 0 1 a

1 0 1 1 0 0 1 0

1 1 0 0 0 1 b b

1 1 1 0 1 1 b 1

Present

State

Present

inputNext State

State Synthesis Table for Moore Model

Flip-flop InputMust

read

Optional

read

Don’t

read

J a b,1,x 0

K b a,0,x 1

S a 1,x b,0

R b 0,x a,1

T T a,b x 1,0

D D a,1 x b,0

Flip-flop reading rules:

JK

SR

Bn An

X 00 01 11 10

0 0 b b a

1 a b 1 0

JA= ~X Bn + ~Bn X

KA= ~Bn + ~X

Bn

An 0 1

0 0 0

1 0 1

Y= An Bn

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If the logic circuit is to be designed using other type of flip-flop, read the Karnaugh maps using

the reading rules for the intended flip-flop. There is no need to do the design again.

Exercise:

Draw the logic circuit for the above example using D flip-flop.

MEALY MODEL STATE MACHINE DESIGN

Problem: ‘011’ Sequence detector (data is coming from the right)

1) Input output relation

Since, the output can be derived using state as well as input, three different states for 3-bit

sequence detector circuit following Mealy model. The three states say, a, b, c represents none, 1st

bit and 2nd bit detection. When the circuit is at state c if the input is as per the pattern the output

is generated in state c itself with proper logic combination of

input.

State Transition Diagram: Mealy Model

Figure shows state transition diagram of the given problem

following Mealy model.

Initialized with a (if input x=0 - remain in same state a, if input

x=1 go to next state b first bit (1) is detected and output y=0).

State b (if input x=0 - go to initial state a, if input x=1 go to next

state c second bit (1) is detected and output y=0).

State c (if input x=0 –go to state a third bit (0) is detected and output y=1, if input x=1 remain in

same state c and output y=0).

Note:- The difference with Moore model is where output is generated one clock cycle later in

state d and also requires one additional state.

STATE ASSIGNMENT FOR SEQUENCE DETECTOR

Assign each state a binary combination of memory values. For Mealy model require minimum

two flip-flops (say A and B) to define their states a, b, c.

The state assignment is as follows.

a: B=0, A=0 b: B=0, A=1 c: B=1, A=0

Since, Mealy Model requires three states for this problem we have six rows in state synthesis

table. In each state there can be two different types of input X=0 or X=1.

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Table below represents state synthesis table for Mealy model. The method remains the same as

Moore model.

Using state synthesis table corresponding to Mealy model, we can fill six positions in each

Karnaugh map. Locations B,A,X=110 and B,A,X=111 are filled with don’t care (x) conditions as

such a combination never occur in the detector circuit if properly initialized.

The design equations are obtained from these Karnaugh maps from which circuit diagram is

drawn as shown below. In this circuit, output directly uses input information.

Exercises:

Sequence detector: 110

1. Obtain the state diagram of the sequence detector using Moore

machine.

Then continue to design the logic circuit using D flip-flops.

Output FFB FFA

Bn An X Bn+1 An+1 Y

0 0 0 0 0 0 0 0

0 0 1 0 1 0 0 a

0 1 0 0 0 0 0 b

0 1 1 1 0 0 a b

1 0 0 0 0 1 b 0

1 0 1 1 0 0 1 0

Present

State

Present

inputNext State

State Synthesis Table for Mealy Model

Bn An

X 00 01 11 10

0 0 0 x b

1 0 a x 1

JB= X An

KB= ~X

Bn An

X 00 01 11 10

0 0 b x 0

1 a b x 0

JA= X ~Bn

KA= 1

Bn An

X 00 01 11 10

0 0 0 x 1

1 0 0 x 0

Y= ~X Bn

Bn An

X 00 01 11 10

0 0 0 x b

1 0 a x 1

JB= X An

KB= ~X

Bn An

X 00 01 11 10

0 0 b x 0

1 a b x 0

JA= X ~Bn

KA= 1

Bn An

X 00 01 11 10

0 0 0 x 1

1 0 0 x 0

Y= ~X Bn

Bn An

X 00 01 11 10

0 0 0 x b

1 0 a x 1

JB= X An

KB= ~X

Bn An

X 00 01 11 10

0 0 b x 0

1 a b x 0

JA= X ~Bn

KA= 1

Bn An

X 00 01 11 10

0 0 0 x 1

1 0 0 x 0

Y= ~X Bn

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2. Obtain the state diagram for the sequence detector using Mealy

machine.

Then continue to design the logic circuit using T flip-flops.

Example:

Sequence detector: 1101 – overlapping case

Mealy machine

Flip-flops: D

1. State Diagram

2. State Table

3. State Assignment

S0=00, S1=01, S2=11, S3=10

Using these assignments, the state table now becomes:

There are four states, and this requires two flip-flops.

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4. Excitation Table

5. Flip-flops excitation using K-Maps

6. Logic circuit using D flip-flops

Exercise 1:

Design the above logic circuit for the Mealy machine sequence detector using JK flip-flops.

Exercise 2:

Design the logic circuit for the Moore machine sequence detector using JK flip-flops.

Input Output

A B X An+1 Bn+1 Z

0 0 0 0 0 0 0 0

0 0 1 0 1 0 a 0

0 1 0 0 0 0 b 0

0 1 1 1 1 a 1 0

1 0 0 0 0 b 0 0

1 0 1 0 1 b a 1

1 1 0 1 0 1 b 0

1 1 1 1 1 1 1 0

FFB

Present

StateNext State

FFA

B X

A 00 01 11 10

0 0 0 a 0

1 b b 1 1

DA= B X + A B

B X

A 00 01 11 10

0 0 a 1 b

1 0 a 1 b

DB= X

B X

A 00 01 11 10

0 0 0 0 0

1 0 1 0 0

Z= A ~B X