Course Summarycourses.cecs.anu.edu.au › courses › ...Ideal_Effects.pdf · Intro to PICOBLAZE, C and Number systems and Boolean Algebra 3. Course overview with microprocessor MU0

1. Course overview 2. Intro to PICOBLAZE, C and Number systems and Boolean Algebra 3. Course overview with microprocessor MU0 (I) 4. Course overview with microprocessor MU0 (II) 5. Verilog HDL 6. Digital system components using schematics and Verilog 7. Combinational logic standard forms. Karnaugh maps 8. Combinational ccts and configurable logic devices 9. Simple Sequential circuits, flip flops10. Sequential circuits, counters, registers, memories11. Nonideal effects in digital circuits

12. Finite State Machines (EXAM THURSDAY APRIL 9, Forestry)13. Design of FSMs14. Register Transfer Level Systems (RTL) systems15. Design of RTLs16. Nonideal effects in complex digital systems (Karnaugh maps)17. Complex RTL design18. The PICOBLAZE Softcore19. Assembly language programming20. C and Assembly21. Other microprocessor architectures

3213: Digital Systems & Microprocessors: L#11

Course Summary

Non Ideal Effects in Digital Circuits


The combinational abstraction ignores propagation delays => combinational circuits are steadystate

The sequential abstraction ignores setup and hold times => sequential circuits are instantaneously synchronous with the clock


NonIdeal Effects in Digital Circuits: Timing Hazards


Analog Analysis

• Digital analysis works only if circuits are operated in spec:– Power supply voltage– Temperature– Inputsignal quality– Output loading

• Must do some “analog” analysis to prove that circuits are operated in spec.– Fanout specs– Timing analysis (setup and hold times)


CMOS Electrical Characteristics

•VIH(min) The minimum voltage level at the input recognised as H.

•VIL(max) The maximum voltage level at the input recognised as L.

•VOH(min) The minimum voltage at the output when in state H.

•VOL(max) The maximum voltage at the output when in state L.

Specified by the device manufacturer

VOH(min) > VIH(min) VOL(max) < VIL(max)


Device Specifications



• An output must sinkcurrent from a load when the output is in the LOW state.

• An output must source current to a load when the output is in the HIGH state.


DC Loading

1MΩ

Isink

5V

Gnd

100Ω

VoutVin = 5V

200ΩIsource

5V

Gnd

1MΩ

VoutVin = 0V

In practice, resistances are never zero or infinite Example: Inverter


CMOS Nonideal Characteristics

1MΩ

Isink

5V

Gnd

100Ω

VoutVin = 5V

E.g. if VOL(max) = 0.1V, then

IOL(max) = 0.1V / 100

= 1mA


CMOS Nonideal Characteristics

IOH The maximum current that can be sourced in the HIGH state while maintaining the output voltage within specified limits

• IOL The maximum current that can be sunk in the LOW state while maintaining the output voltage within specified limits

Noise MarginA measure of the extent to which a logic circuit can tolerate noise or unwanted spurious signals




Noise Margin

VIH(min)

VIL(max)

VOH(min)

The maximum number of gates that can be driven reliably.


Fanout

AC loading has become a critical design factor as the industry has moved to pure CMOS systems.

– CMOS inputs have very high impedance, DC loading is negligible.

– CMOS inputs and related packaging and wiring have significant capacitance.

– Time to charge and discharge capacitance is a major component of delay.


AC Loading


Transition times

tPHL tPLH


Propagation Delay


Setup and Hold Times Setup time is the time that a signal needs to be established before an active clock edge for its output to be valid

Hold time is the time that a signal needs to remain valid after an active clock edge for its output to remain valid

• Low static (Steady state) power consumption • Significant Dynamic power consumption due to

• Capacitive loads

• Both n and p channel transistors are partially on during transitions

Higher clock speeds => higher power consumption


Power Consumption in CMOS Devices

What are the manifestations of the above nonideal physical phenomena?

Static hazards

Even if a combinational circuit's output settles eventually, it may produce a short pulse or GLITCH during the switching of its inputs

Glitches are only harmful to any sequential circuits that follow

One can design combinational circuits using Karnaugh maps for glitch free operation


NonIdeal Effects in Combinational Circuits

A static1 hazard is a pair of input combinations that differ in only one input variable and both give a 1output.

But it is possible for a momentary 0 output to occur during a transition of that input variable

A static0 hazard is the converse.


Static Hazards


Example of a Static1 Hazard


Static1 Hazard Eliminated

A dynamic hazard occurs when more than one output transition results from a single input transition.

Multiple output transitions can occur if there are multiple paths with differing propagation delays from the input to the output

Handle by proper design and simulation


Dynamic Hazards


Dynamic Hazards: An example

What are the manifestations of the above nonideal physical phenomena in sequential circuits?

Clock synchronisation

Clock skew

Pulse catching

Switch debouncing

note that a switch could bounce through a combinational circuit but the problem is for the sequential circuits


NonIdeal Effects in Sequential Circuits

• Not all inputs to an RTL system are synchronised with the clock

• Examples:– Keystrokes– Sensor inputs– Data received from a network (transmitter has its own clock)

• Inputs must be synchronised with the system clock before being applied to a synchronous system.


Asynchronous inputs

Go – no go configuration


Asynchronous inputs


A simple synchroniser


Only one synchroniser per input

Combinational delays to the two synchronizers are likely to be different.


Even worse

• One synchroniser per input• Carefully locate the synchronisation points in a system.• But still a problem the synchroniser output may

become metastable when setup and hold time are not met.


Different approach...

• Hope that FF1 settles down before “META” is sampled.– In this case, “SYNCIN” is valid for almost a full

clock period

A bit like toll gates...3213: Digital Systems & Microprocessors: L#13

The correct approach...

Pulses must meet minimum pulse width requirement of SR latch!


Pulse Catching

– Clock signal may not reach all flipflops simultaneously.– Output changes of flipflops receiving “early” clock may reach D inputs of flip

flops with “late” clock too soon.

Reasons for slowness:(a) wiring delays(b) capacitance(c) incorrect design


Clock Skew

Switch Bounce



Measured bounce


Measured bounce

Schmitt TriggerVOUT

VIN

VT VT+5.0

0.0

VO

time

High

Low

VIN

time

5.0

0.0

VT+

VT

(a)

(b)


Debouncing Circuit

VO

time

High

Low

VIN

time

5.0

0.0

VT+

VT

(a)

(b)R1 >>R2



SR Debouncer

In practice, one writes software instead of using this circuit

Powerup


RC Debouncer

Documents

Course Summarycourses.cecs.anu.edu.au › courses › ...Ideal_Effects.pdf · Intro to PICOBLAZE, C and Number systems and Boolean Algebra 3. Course overview with microprocessor MU0