Convolutional Code Based Concurrent Error Detection

in Finite State Machines

Konstantinos N. RokasAdvisor: Prof. Yiorgos Makris

2

Finite State Machine Model

Automaton View:

State Register (D Flip-Flops)

Hardware View:

CombinationalNext State Logic

Input

State

Next StateS1

S2

S5 S4

S3

In=1

In=0

3

Concurrent Error Detection

FSM CircuitNormal

Functionality

Concurrent Error DetectionFunctionality

inputs outputs

Concurrent Error Detection Output

Objective:• Obtain an Indication of

the Operational Health of the Circuit during Normal Functionality

What Can go Wrong?

• Permanent Faults• Intermittent Faults

• Transient FaultsWhy do we care? Circuit Reliability & Dependability

4

Non-Intrusive CED – Minimize Delay

Basic Principle: Leave Original FSM Intact

(Controller Circuits Highly Optimized for Speed)

Combinational Next State

Logic

Input

StateRegister

Next State

State

Simplest Approach: Duplication

Duplicate Next State

Logic

Duplicate Register

Next State

State

Comparator

ConcurrentError

DetectionOutput

5

Unrestricted Error Model

S1

S2

S5 S4

S3

In=1

In=0

Assumption:• Malfunctions May Transform a Transition

into Any Other Transition

Implication (Meyer ’67):

• Any Concurrent Error Detection for the

Unrestricted Model will be as Complex as Duplication

S1

S2

S5 S4

S3

From S1 on In=1, GM=>S2, BM=> {S1, S3, S4, S5}

6

Restricted Error Model

Assumption:• Hardware Malfunction

Model Pinpoints Set of Erroneous Transitions

“Stuck-at” Fault Model:• Every Line in the Circuit

may be Stuck Permanently at Logic ‘1’

or Logic ‘0’• Standard Industry Model, Acceptable but

not Exact• Any Model May be Used

S1

S2

S5 S4

S3

In=1

In=0S1

S2

S3

From S1 on In=1, GM=>S2, BM=> {S1, S3}DC=> {S4, S5}

7

Convolutional Code-Based Solution

State Register (D Flip-Flops)

CombinationalNext State Logic

Next State

Input

State

Key output Logic

Error Detecting convolutional Decoder

Fault

8

Convolutional Code-How it works

Codeword 1->1->6 is a valid codeword(occurs when input to code is B->C->D->C)

S1Key=6

S2 S3 S2Key=1 Key=1

Codeword 1->1->1 is an invalid codewordFault will be detected with latency 1!

A B C D

€

0 3 5 6

4 7 1 2

7 4 2 1

3 0 6 5

⎡

⎣

⎢ ⎢ ⎢ ⎢

⎤

⎦

⎥ ⎥ ⎥ ⎥

A

B

C

D

U2

U1

Transition matrixS1 S2

Key=1

Key=1

Erroneous transition

PROBLEM: How do we assign keys?

9

Working through an example

An FSM with 8 states has the following next state logic:

Need to consider a restricted Error model.Consider the stuck-at fault model.

10

Graph of Faulty transitions

If S1

S2

S3

then S2 S3

GM

BM

000 001 011

110 010

111 101 100

Graph for the previous example:

Next step:Identify coloring so thatconnected states havedifferent colors.

000 001 011

110 010

111 101 100

11

From colors to keywords:

C

A

D

A B C D

A

B

C

D

U2

U1

Transition matrix Previous State

Key output

Previous Color

Next Color

Next State

Input

B

For example:

000 101

Is a transition from B to D and gives a key 2

€

0 3 5 6

4 7 1 2

7 4 2 1

3 0 6 5

⎡

⎣

⎢ ⎢ ⎢ ⎢

⎤

⎦

⎥ ⎥ ⎥ ⎥

12

Table of Keys for previous Example:

IN PS2 PS1 PS0 NS2 NS1 NS0 K2 K1 K00 0 0 0 1 0 1 0 1 00 0 0 1 1 1 0 1 1 10 0 1 0 1 0 0 1 1 00 0 1 1 1 1 0 0 0 00 1 0 0 0 0 1 0 1 00 1 0 1 0 1 0 1 0 10 1 1 0 0 0 0 0 1 10 1 1 1 0 1 0 0 1 01 0 0 0 0 0 1 0 0 11 0 0 1 0 0 0 1 0 01 0 1 0 0 0 0 0 0 01 0 1 1 0 0 0 0 0 01 1 0 0 1 0 1 0 0 11 1 0 1 1 0 0 1 1 01 1 1 0 1 0 0 1 0 11 1 1 1 1 0 0 0 0 1

13

Observations on the H-K method:

• Flexibility in selecting the partition and the code

Key=f(PS,IN)

NS=g(PS,IN)

• Keys and Next State are both functions of PS and IN

Key output Logic

Error Detecting convolutional Decoder Fault

IN

PS

IDEA: Share some of the next state logic when making the key

Perhaps we could have one key bit equal a next state bit

NS

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Example with limited key logic:

000 001 011

110 010

111 101 100

Clever selection of a coloring:

C

A

D

B

€

0 1 7 6

4 5 3 2

5 4 2 3

1 0 6 7

⎡

⎣

⎢ ⎢ ⎢ ⎢

⎤

⎦

⎥ ⎥ ⎥ ⎥

A B C D

A

B

C

D

Clever selection of code

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Example with limited key logic:

IN PS2 PS1 PS0 NS2 NS1 NS0 K2 K1 K00 0 0 0 1 0 1 0 0 00 0 0 1 1 1 0 0 1 10 0 1 0 1 0 0 0 0 00 0 1 1 1 1 0 0 1 00 1 0 0 0 0 1 1 0 10 1 0 1 0 1 0 1 1 00 1 1 0 0 0 0 1 0 10 1 1 1 0 1 0 1 1 11 0 0 0 0 0 1 0 0 11 0 0 1 0 0 0 1 0 01 0 1 0 0 0 0 0 0 11 0 1 1 0 0 0 1 0 11 1 0 0 1 0 1 1 0 01 1 0 1 1 0 0 0 0 11 1 1 0 1 0 0 1 0 01 1 1 1 1 0 0 0 0 0

Notice that K1=NS1!

16

Mathematical Formulation:

The problem of having a next state bit equal to a output key can be solved as a mixed linear integer program.It is not guaranteed that we can always find a solution.More details on the mathematical formulation are provided in the final report.

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Limitation: Faults on output logic

State Register (D Flip-Flops)

CombinationalNext State Logic

Next State

Input

Previous State

Key output Logic

Error Detecting convolutional Decoder

Fault

OUT

Faults on the output will not be detected!

18

Detecting output faults- Solution A

IDEA: Share some of the output logic when making key

Perhaps we could have one key bit equal the output bit(just like we did with the next state bit before!)

Let’s try an example:An FSM with an output

Is shown on the right:

Then an incorrectOutput will give us anIncorrect key and theError may be detected!(and we will save h/w)

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Detecting output faults- Solution A

000 001 011

110 010

111 101 100

Graph of faulty transitions:

C

A

D

B

€

0 2 5 6

4 7 1 3

7 4 3 1

2 0 6 5

⎡

⎣

⎢ ⎢ ⎢ ⎢

⎤

⎦

⎥ ⎥ ⎥ ⎥

A B C D

A

B

C

D

Clever selection of code:

000 001 011

110 010

111 101 100

Clever selection of a coloring:

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Table of Keys:IN PS2 PS1 PS0 NS2 NS1 NS0 OUT K2 K1 K00 0 0 0 1 0 1 1 0 1 10 0 0 1 1 1 0 1 0 1 10 0 1 0 1 0 0 0 0 1 00 0 1 1 1 1 0 1 1 0 10 1 0 0 0 0 1 1 1 0 10 1 0 1 0 1 0 1 1 0 10 1 1 0 0 0 0 0 1 0 00 1 1 1 0 1 0 1 0 1 11 0 0 0 0 0 1 1 0 0 11 0 0 1 0 0 0 0 1 0 01 0 1 0 0 0 0 0 0 0 01 0 1 1 0 0 0 0 0 1 01 1 0 0 1 0 1 0 1 1 01 1 0 1 1 0 0 0 0 1 01 1 1 0 1 0 0 1 1 1 11 1 1 1 1 0 0 0 1 0 0

Notice that OUT=K0! Detects 58% of output errors.

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Detecting output faults- Solution B

Previous method had less than 100% efficiency

IDEA: Treat the FSM’s output as a state bit.All output faults will be detected, since all state faults are detected

Let’s work through the previous example:

011 0

Consider the first three bits to designate the stateand the fourth bit to designate the output

For example, can be written as:State=011Output=0

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Detecting output faults- Solution B

0101 1001 1111 0010

1000

0110

0100

0011

0001 1010 1101 0111

1110

1100

1011

0000

Fault set

0101 1001 1111 0010

1000

0110

0100

0011

0001 1010 1101 0111

1110

1100

1011

0000

Fault coloring:

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Table:IN PS2 PS1 PS0 PREV.

OUTNS2 NS1 NS0 NEXT

OUTK2 K1 K0

0 0 0 0 0 1 0 1 1 0 0 00 0 0 0 1 1 0 1 1 0 1 00 0 0 1 0 1 1 0 1 0 1 10 0 0 1 1 1 1 0 1 0 0 10 0 1 0 0 1 0 0 0 0 1 10 0 1 0 1 1 0 0 0 0 0 10 0 1 1 0 1 1 0 1 1 1 00 0 1 1 1 1 1 0 1 1 1 00 1 0 0 0 0 0 1 1 0 1 10 1 0 0 1 0 0 1 1 0 0 10 1 0 1 0 0 1 0 1 0 0 00 1 0 1 1 0 1 0 1 0 1 00 1 1 0 0 0 0 0 0 0 0 00 1 1 0 1 0 0 0 0 0 1 00 1 1 1 0 0 1 0 1 0 1 00 1 1 1 1 0 1 0 1 1 1 11 0 0 0 0 0 0 1 1 1 0 11 0 0 0 1 0 0 1 1 1 1 01 0 0 1 0 0 0 0 0 1 0 01 0 0 1 1 0 0 0 0 1 1 11 0 1 0 0 0 0 0 0 1 1 11 0 1 0 1 0 0 0 0 1 0 01 0 1 1 0 0 0 0 0 0 0 01 0 1 1 1 0 0 0 0 0 0 01 1 0 0 0 1 0 1 0 0 0 11 1 0 0 1 1 0 1 0 0 1 11 1 0 1 0 1 0 0 0 1 1 01 1 0 1 1 1 0 0 0 1 0 11 1 1 0 0 1 0 0 1 0 1 01 1 1 0 1 1 0 0 1 0 0 01 1 1 1 0 1 0 0 0 1 0 1

100% of faultswill be detected!

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Conclusion:

Overview:1) We have limited the hardware overhead for the key

logic2) Using the same methodology we can detect output

faults3) Alternatively, output faults can be detected by

treating output bits like state bitsFuture work:Possible expansion for codes with latency greater than one(this could minimize further the number of key output bits)