Configuration of FPGAs Using (JTAG) Boundary ScanChen Shalom

www.cs.huji.ac.il/~chensha

Agenda

• FPGAs - overview

• Using FPGA – from HDL to chip

• FPGA configuration Using JTAG

• Summary

Field

Programmable

Gate

Array

What are FPGAs ?

Who makes FPGAs ?

FPGA vs. CPLD

Internal logic

- overview

What are FPGAs ?• FPGAs are programmable digital logic

chips• Can be programmed to almost any

digital function• FPGA can be configured many times

with different functions• If we have bug in our design- we fix it in

the RTL and configure the FPGA again• FPGAs are much faster than a design

board with discrete components• FPGAs are volatile devices

Who makes FPGAs ?

• Xilinx – Virtex, VirtexII, VirtexII-

pro

• Altera

• Lattice

• Actel

• Quicklogic

FPGAs vs. CPLDsFPGAs CPLDs

“fine-grain” “coarse-grain”

RAM based- need to be downloaded at each power up

EEPROM based- active at power up

Slower Faster

Can hold very large designs

Can contain small designs only

Internal Logic• Thousands of Basic logic cells• Each logic cell consist:

• Small lookup table• Some basic gates• D-flipflop

• Logic cells can be connected using interconnect resources (wires/muxes)

Using FPGAFrom HDL to chip

Using FPGA

netlistplace & route

config

• Write synthesizable RTL in HDL

• Create the netlist from a HDL code

• Place and route according to the

module

constrains – creating a binary file

• Configure into the FPGA

FPGA configuration Using JTAG

What does it means ?The JTAG interfaceVirtex Boundry Scan InstructionsVirtex Boundry Scan RegistersThe configuration sequence

What does it means ?

• Configuring an FPGA means downloading a stream of 0’s and 1’s into it through some special pins

• The FPGA has 2 states- “configuration mode” and “user mode”

• Once the FPGA is configured, it goes into “user mode” and becomes active

• A special PROM on board configures the FPGA automatically at power-up

The JTAG interface• Standard JTAG commands can be used

to take control of each pin in the chain• In addition to testing, BS offers a device

to have it’s own set of user defined instructions

• The added instructions, such as configure and verify, have increased the popularity of BS devices

• BS FPGAs has the ability to be configured through the BS chain

Virtex Boundry Scan Instructions

Virtex Boundry Scan Registers

• The Virtex family is fully compliant with BS.1• In addition it supports some optional registers:

The configuration sequence

• Power up – FPGA in configuration mode• Get INIT==1• Load CFG_IN instruction• Load bitstream from the BSR• Load JSTART instruction• Start up sequence

• The FPGA is operational !!

An example for binary code0011 0000 0000 0001 0010 0000 0000 0001-> Header: Write to COR0000 0000 1010 0000 0011 1111 1111 1111-> COR data sets SHUTDOWN = 00011 0000 0000 0000 1000 0000 0000 0001-> Header: Write to CMD0000 0000 0000 0000 0000 0000 0000 0101-> Header: Start command0011 0000 0000 0000 1000 0000 0000 0001-> Write to CMD0000 0000 0000 0000 0000 0000 0000 0111-> RCRC command0000 0000 0000 0000 0000 0000 0000 0000-> flush pipe

Xilinx Virtex FPGA

A JTAG cable• Connects between the PC to the FPGA board

The Ximpact tool

Summary

Az ma haya lanu sham ??

• FPGA is a programmable chip

• The best friend of the HW designer

• Built with many basic cells

• JTAG is a great interface for FPGAs

configuration- added instructions and

regs

• The configuration sequence

• Future – IEEE 1532

• Element

BGU Pictures

Board infrastructure

The BGU device

The warm-air machine