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Confidential
2012 EU ALSA Training P9X79 SERIES
GRMA Brain_HUNG
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Communication BUS Introducing
P9X79 – Agenda
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
• CPU 6C/12T, 4C/8T• Support PCIe 3.0• DRAM support up to 4ch,
8xDIMM, Max. 64GB• Supports NVIDIA® 3-Way
SLI™ TechnologySupports AMD Quad-GPU CrossFireX™ Technology
• SATA 6G *2, SATA 3G *4• USB 2.0 *14• Remove SAS port
Intel X79 Platform Structure
Intel X79 Platform Structure
• Support 8GB,MAX is for 64GB
• Support DDR3 2400(O.C.)/2133(O.C.) 1866/1600/1333/1066 • Support Intel® Extreme Memory
Profile(XMP) • Support DIGI+ Power Control
• 2 + 2 Phase Control
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
P9X79 Deluxe - Architecture
PCI-E X16 SLOT4 (X16/X8)
PCIE x1
6Gb
PCI-E
100MHz
ASMEDIA
100 MHz
100MHz
32Mb
SATA3
DMI
5Gb/s
SATA4
NCT6776FASM1061
PCIE x1
ASMEDIA
ASM1042
PCI-E X16 SLOT2 (X8)
25 MHz
100MHz
ICS
SATA5
5Gb/s USB3.0
PCI-E
P9X79 DELUXE
High-Speed USB
33MHz
Patsburg
PCIE x1
SPI
100 MHz
PCI-E
Back 2 ports
CLOCK GEN
Sandy Bridge-E
SATA BUS
PCI-E X16 SLOT1 (X16)
ESATA
SLOT2
100 MHz
100MHz
10/100/1000
100MHz
LAN 2
Audio Codec
CLOCK GEN
100 MHz
100MHz
LPC BUS
PESATA
SM BUS
5Gb/s
ASMEDIA
480Mb/s
100MHz
Channel B
BT3
PCI-E X1
SM BUSRealtek 8111E-VL
PCIE x1
100 MHz
SATA2
100MHz
100MHz
Intel Lewisville
SATA1 Gen3
14.318 MHz
ASMEDIA
ITP
Rev 1.03B
Channel D
ASM1042
10/100/1000
Front 2 ports
ICS
ASM1042
PCI-E X1
100 MHz
VRD 12 on Board
LAN 1
Q-S
wit
chSIO PCH
SLOT1
100MHz
100 MHz
2 ports
PCIE x1
PCIE x1
Channel A
96 MHz
ICS932SQ428AKLF
DDR3 1066/1333/1600/1866/2133/2400
2011.12.12
5Gb/s
LGA-2011 Pin Socket
128-bit Dual-Channel Memory x 4 Slots
48MHz
SPI FLASH
2 External Ports
DDR3 1066/1333/1600/1866/2133/2400
PCIE x1
DDR3 1066/1333/1600/1866/2133/2400
SATA0 Gen3
Realtek ALC898
Channel C
PCI-E
INTEL 6Gb
12 ports
100MHz
100MHz
33MHz
USB3.0
Intel Processor
PCI-E X16 SLOT3 (X8)
AZAWARE
ICS9FGL1218AKLFT
100MHz
DDR3 1066/1333/1600/1866/2133/2400
Back 4 ports
24MHz
Marvell9128
Q-S
wit
ch
VL810
PCIE x1
USB3.0
P9X79 PRO - Architecture
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
DIGI+ Power Control (2/6)
Most Precise Adjustment on CPU & DRAM Extreme Performance & O.C. Capability for CPU & DRAM High System Stability
Digital Power : CPU + DRAM
Intelligent Digital Power Controller
(CPU)
Intelligent Digital Power Controller (DRAM)
New Feature – DIGI+ Power Control
New Feature – USB BIOS Flashback
Smart chip controlwithout boot-up
No need to open chassis
Complete within only ONE click
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
P9X79 Deluxe – Compare with P8 Series
• DRAM power control: Analog DIGITAL• Clock Generator: PCH Internal External • E-SATA support 6G Asmedia1061
• X79 is native support PCIe 3.0• BIOS can park setting on gen2 or gen3 for compatibility.
P8 & P9 series DRAM power control
Analog
PWM CONTROLLER UP6203
1.5VDUAL_REFEC
phaseMOSdriver 1.5VDUAL
Digital
PWM CONTROLLER ASP1101
EC phase
MOSdriver 1.5VDUAL
CPU
SMBus
SVID
P9 series DRAM power control
P8 series DRAM power control
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
P8 Series - Clock Distribution
C_PCIEX1#_2 32
C_PCIEX16_1 29
C1_CLK_ITP#
C_PCIEX16#_3 31
ST529 /X/CPT1
GND
C_PCI_ASM108534
ST17/X/CPT 1
IPD
CPU
C_PCIEX16#_2 30
SR5011MOhm/CPT
12
C_PCI_SIO_R
C_CLK_PCI4
IPD
GND
C_PCIE_R2# 43
12GND
3
SX2 25Mhz/CPT
C_48M_SIO66
SR194 90.9Ohm
1%
1 2
IPD
PCIEX16_2
ST15/X/CPT 1
IPD
PCIEX16_1
SC1533PF/50V/CPT
12
C_PCIE_U3 48
C_PCI_ASM1085_R
GND
IPDC1_CLK_FLEX2
C1_CLK_ITP
SR19
510
KOhm
12
Clock Buff
GND
C_PCIEX16_3 31
C_PCIE_X1#_BUF 14
IPD
IPD
PCIEX16_3
C_PCI_PCH16
SR554 33Ohm1 2
IPD
PLX 8608
SR23
510
KOhm
12
SC1633PF/50V/CPT
12
C_PCI_EC_R
PCIEX1_2
SR551 33Ohm1 2
ST542/X/CPT 1
SR23
810
KOhm
12
CLOCK
SU1H
COUGER_POINT_PCH
AT11
AN14
AT12
AT17
AT14
AT9BA5
AW5BA2
AL2
AN8
AJ5
AJ3
R27P27
R52N52
AE2AF1
P31R31
N56M55
AE6AC6
AA5W5
AB12AB14
AB9AB8
Y9Y8
AF3AG2
AB3AA2
AG8AG9
AE12AE11
W53V52
BD38BF38
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
CLKOUTFLEX0/GPIO64CLKOUTFLEX1/GPIO65CLKOUTFLEX2/GPIO66CLKOUTFLEX3/GPIO67
XCLK_RCOMP
REFCLK14IN
XTAL25_OUT
XTAL25_IN
CLKIN_GND1_NCLKIN_GND1_P
CLKOUT_ITPXDP_NCLKOUT_ITPXDP_P
CLKOUT_PCIE7NCLKOUT_PCIE7P
CLKOUT_DMI_NCLKOUT_DMI_P
CLKOUT_DP_NCLKOUT_DP_P
CLKOUT_PCIE0NCLKOUT_PCIE0P
CLKOUT_PCIE1NCLKOUT_PCIE1P
CLKOUT_PCIE2NCLKOUT_PCIE2P
CLKOUT_PCIE3NCLKOUT_PCIE3P
CLKOUT_PCIE4NCLKOUT_PCIE4P
CLKOUT_PCIE5NCLKOUT_PCIE5P
CLKOUT_PCIE6NCLKOUT_PCIE6P
CLKOUT_PEG_A_NCLKOUT_PEG_A_P
CLKOUT_PEG_B_NCLKOUT_PEG_B_P
CLKIN_GND0_NCLKIN_GND0_P
CLKIN_DOT_96NCLKIN_DOT_96P
C_CPU 5
IPDC_CPU# 5
C1_CLK_FLEX1
PCIEX1_1
C_PCI_EC95
S_25M_IN
GND
C_PCIEX1_2 32
C_PCIE_R2 43
C_PCIE_U3Q 53
SR23
710
KOhm
12
GND
USB3-2
C1_CLK_FLEX0
C_PCIE_PEX# 58
C_PCIE_U3Q# 53
C_PCIEX1#_1 32
SR553 33Ohm1 2
USB3-1C_PCIE_U3# 48
C_PCIEX16#_1 29
S_25M_OUT
C_PCI_PCH_R
ST530 /X/CPT1
C_PCI_SIO66
S_XCLK_RCOMP
C_48M_SIO_R
C_PCIE_PEX 58
SR23
610
KOhm
12
9128
C_PCIE_X1_BUF 14
+1.05PCH
C_PCIEX1_1 32
C_PCIEX16_2 30
ST16/X/CPT 1
SR552 33Ohm1 2
SR555 33Ohm1 2
P9X79 Deluxe - Clock Distribution
SRC2
FIX_SRC7
CK525CPU
SRC1
FIX_SRC6
PCI0
PCI
CLOCK BUFFER
XMM1, XMM2
FSLB
PCH PatsburgSRC0
FIX_SRC5
ControlLogic
SAS
DOT96
C_PCIEX16_2 100MHZ
SRC0
ICS9FG1217/1218
FSLA
C_CPU 100MHZ
C_L2X1 100MHZ
CPU1
FIX_SRC4
QPI
14MHz
PCI4
CPU0
FIX_SRC3
2011 pin
C_2X1 100MHZ
C_U33 100MHZ
PCI3
Ratio
C_U32 100MHZFIX_SRC2
Processor
CRYSTAL
25MHz
ITPConnector
NS_SAS1
C_CPU_QPI 100MHZ
C_PCIEX16_1 100MHZ
FIX_SRC1NS_SAS0
SIO 48MHZ
M/NSRC2
UPLINK
FIX_SRC0
25MHz
100MHZDMI
SRC8
100MHZ
CRYSTAL
11 : 100MHz
C_U31 100MHZ
C_1X1 100MHZDOT96
SRC7
C_L1X11 100MHZ
Intel
10 : 125MHz
SATA
DMI
M_CHA_CLK[0..3]/#
01 : 167MHz
PCI1
48M
FSLB
CPHY
C_DMI_PCH 100MHZ
DIF_IN
SRC6
M_CHB_CLK[0..3]/#
00 : 250MHz
IntelSRC1
CLOCK CHIP
FSLA
SRC5
PCIE
PCI2
ICS932SQ428
C_RX1 100MHZ
FIX_SRC8
SRC4
XMM3, XMM4
C_CPHY_PCH 100MHZ
C_PCIEX16_4 100MHZ
14M
SRC3
Sandy Bridge-E
C_PCIE_PCH 100MHZ
C_PCIEX16_3 100MHZ
• ICS428: SIO, PCI, SATA…
• ICS1218: CPU, CPU_QPI, DMI, PCIE, PCIE onboard device…
ICS1218
Patsburg Chipset High-Level Clock Diagram
PCIE2.0
USB
P9X79 Deluxe – Clock Generator
1218
428
+VTT_CPU_PWRGD CK420_PWRGD#25 MHz
25 MHz
Power
Power
Power for Clock Generator
+3VDUAL +VDD_CLK
Power Distribution for CLK GEN
428 CLK GEN
1218 CLK GEN
Clock Generator of ICS394SQ428
Clock Generator of ICS9FG1218
Server MB(For C_CPU)
SAS
Marvall 9128
(SATA)
C_PCH_GND(ex: E-SATA)
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
P9X79 Deluxe – Power Flow
P9X79 Deluxe – CPU Voltage
P9X79 Deluxe – DRAM Voltage
P9X79 Deluxe – PCH Voltage
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
P9X79 Power Status - ACPI
Mode Description Battery Power
Standby_ATX
Power
Standby Power
Dual Power
Main Power
G3 Time V
S0 Working Status
V V V V V Working Status
S1 CPU Suspend
V V V V V Power on Suspend
S2 V … … … …
S3 Suspend to RAM
V V V V Suspend to RAM
S4 Suspend to Disk
V V V … Suspend to Disk
S5 Soft Off V V V … SoftOff
Deep S5 Deep Soft Off(EuP)
V V … … Deep Soft Off( EuP)
Power 3V_BAT 5VSB_ATX,3VSB_ATX
5VSB, 3VSB,
1.5V_DUAL, 3V_DUAL
12V,5V,3V, VCORE
G3: Battery S0: All Power S3: Standby and Dual Deep S5: Only ATX Power
P9X79 Power – Deep S5 State
(PWRBTN#IN, KB MS Wakeup)
P9X79 Deluxe - Power Sequence
P9X79 Deluxe - Power Sequence (1)
Battery
SIO
3V_ATX+BAT_3V SR88 S_SRTCRST
O2_ECRST#
Power Supply
O_RSMRST#
O2_ECRST#O_RSMRST# O2_RSMRST#
1 2
3
4
5
6
P9X79 Deluxe - Power Sequence (2)
O2_ECRST# O2_RSMRST#
P_+VCCPLL_REF +1.8V level (0.03V in S5)
P_+VTTCPU_REF +1.05V level (0.8V in S5)
P_+1.1V_SB_REF +1.1V level
P_+VTTDDR_AB_REF_10 +0.75V level
P_+1.5V_SB_REF_10 +1.5V level
P_+VTTDDR_CD_REF_10 +0.75V level
O_RSMRST#
O2_CUT_PSON#
O_PSON#
O2_PSON#
+3V level
+3V level
8
6
7
P9X79 Deluxe - Power Sequence (3)
SIOPower Button O_PWRBTN#IN O_PWRBTN#
SIOSLP_S3#SLP_S4#
O_PSON#
O2_CUT_PSON#
O2_PSON#
+3V level
+3V level
+3V level
+5V level
Power Supply
O2_PSON# 3V, 5V, 12V
Power Supply
B_ATX_PWROK SIO
+3V level
+5V level
109
11
12 13
13 14
15
P9X79 Deluxe - Power Sequence (4)
+VTT_CPU, +1.5VDUAL_AB, +1.5VDUAL_CD, +1.1V_SB, +1.5V_SB+1.05V level +1.5V level +1.5V level +1.1V level +1.5V level
16
+VDDQ_AB_PWRGDS_DRAMPWROK
+VDDQ_CD_PWRGDS_DRAMPWROK
H_DRAMPWROK_AB
H_DRAMPWROK_CD
17
IC
SR1478+1.5VDUAL_CD
+VTT_CPU18MB Logic
Circuit +VTT_CPU_PWRGD
+1.5V level
+3V level
P9X79 Deluxe - Power Sequence (5)
19 +VTT_CPU_PWRGDVCORE
IC
VCCSAIC
SR151
SR1003
P_VCORE_EN_10
P_VCCSA_EN_10
SR255 Clock GenMB Logic
Circuit20
21VCORE
IC
VCCSAIC
P_VCORE_EN_10
P_VCCSA_EN_10
+VCORE
+VCCSA
(Around +1V)
+3V level
P9X79 Deluxe - Power Sequence (6)
VCOREIC
P_VCORE_VRDY_622O2_GPI1MB Logic
Circuit
O2R64
S_VRMPWRGD
EC
O2_GPO1 SR535
O2_GPO1
+VSA_CPU_PWRGDVCORE
ICMB Logic
CircuitP_+VCCPLL_REF_R_10
23 P_+VCCPLL_REF_R_10VCCPLL
IC+VCCPLL
+1.8V level
P9X79 Deluxe - Power Sequence (7)
24SIO O_PWROK_SIO
EC
SR1478 O_PWROK
H_CPUPWRGDH_SID_CLK
H_SID_DATA
H_SID_ALERT#
VCOREIC
25
+3V level
+1.05V level
+1.05V level
P9X79 Deluxe - Power Sequence (8)
S_VRMPWRGD26
S_PLTRST#
SIO
LAN
Other Devices
27 SIO O_PCIRST#_PCIEX16_* [1:3] MB PCIES_PLTRST#
28 H_CPURST#
+3V level
+3V level
+1.05V level
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
EC is a 8051 micro-processor EC functions
DIGI+ Power Control--SMBUS interface Over-voltage control, 3.2V/512=6.25mV/step--PWM interface Voltage sense--ADC interface TPU, EPU & EUP Control --GPIO interface Memory OK--GPIO interface PWM Fan Control--PWM & Fan-in interface SIO & PCH -- LPC interface BIOS
P9X79 Deluxe – Embedded Controller (1)
P9X79 Deluxe – Embedded Controller (2)
SMBUS interface PIN69 O2_SMB_SWITCH(Power)PIN72 O2_SMB1_DATAPIN73 O2_SMB1_CLK(EEPROM)PIN76 O2_SMB2_DATAPIN77 O2_SMB2_CLK
PWM interface PIN33 O2_PWM0(VCCPLL)PIN34 O2_PWM1(VTTCPU)PIN35 O2_PWM2(1.1V_SB)PIN36 O2_PWM3(VTTDDR_AB)PIN37 O2_PWM4(VTTDDR_CD)PIN38 O2_PWM5(1.5V_SB)
Flashback interface PIN84 O2_USB_SELPIN85 O2_USB_IN_RPIN86 O2_SPI_SWITCHPIN99 O2_USB_LED(USB)PIN44 O2_USB+PIN45 O2_USB-(SPI)PIN101 O2_SPI_CLKPIN102 O2_SPI_DOPIN103 O2_SPI_DIPIN104 O2_SPI_CS#
LPC interface PIN115 F_LAD0PIN116 F_LAD1PIN117 F_LAD2PIN118 F_LAD3PIN108 F_SERIRQ#PIN111 S_SLPRST#PIN112 F_FRAME#PIN113 C_PCI_EC
GPIO interface (TPU)PIN11 O2_OC_OK_R(EPU)PIN9 O2_EPU_RPIN70O2_+5VDUAL_USBKB_EUP(MEM OK)PIN36 O2_MEM_OK_R
PWM & FAN in interface PIN6 O2_SEN_FAN1PIN7 O2_SEN_FAN2PIN8 O2_SEN_FAN3PIN52 O2_FANPWR_PWM1 PIN53 O2_FANPWR_PWM2PIN54 O2_FANPWR_PWM3
Control Signals(Power)PIN48,65,83,96 +3VSBPIN31 O2_VDDAPIN30,32 O2_VREF(CLK)PIN81 XCLKOPIN82 XCLKI(Reset)O2_RSMRST#(PWRGD)PIN108 O2_GPO1_RPIN128 O2_GPI1(Others)PIN39 O2_GPO2PIN40 O2_GPO3PIN78 S_SLPS3#PIN79 S_SLPS4#PIN67 O_PWROKPIN63 O2_CUT_PSONPIN98 J_SILENT#
USB Back up Condition
USB Type : FAT32、 FAT type BIOS Image : Follow X79 each Model Crash free
naming(EX: X79 DLX: P9X79D.ROM、 X79 PRO: P9X79PRO.ROM…)
EC USB Back up function - 1
EC USB Back up function - 2
SLP_S3 SLP_S4 PWROK
G3 0 0 0
S5 0 or 1 0 0
S0 1 1 1
S1 1 1 1
S3 0 1 0
S4 0 0 0
Press flash button for 3 sec to start update station, then the LED of switch will be flashing.
1. Read PEN DRIVER
2. Scan files [XXX.ROM]
If can scan files
Start to update and BIOS LED will be flashing.
After finishing, the LED of switch will be extinguished.
The LED of switch is always bright
YES
NO
According these signals connecting to EC, EC can realize present system status
EC USB Back up function - 3
USB Device
EC USB Back up function - 4
Default : SB to USB SPI to SB
1
USB Device
At S5 status, press Backup button more than 3 sec to start back function.
EC USB Back up function - 5
2
1
USB Device
EC USB Back up function - 6
2
1
3
3
2
USB Device
Confirm ROMID & MODELID and others information are normal
EC USB Back up function - 7
1
3
3
2
4
EC USB Back up Function - 8
1
3
3
2
4
5
5
How to Debug Flashback Function - 1
How to Debug Flashback Function - 2
How to Debug Flashback Function - 3
How to Debug Flashback Function - 4
When System BIOS update EC Firmware
EC Broken status: EC flash is corrupted The data in the EC or EC flash might be corrupted.
Please contact ASUS Technical Support for help
EC flash update fail The data in the EC or EC flash might be corrupted.
Please contact ASUS Technical Support for help
EC Broken Status
Power & Reset & XTAL:
EC - Can’t Boot Status - 1
24 MHz Crystal
O2_OP_mode:
This PIN is used for RD & factory to update EC firmware or flash programming.
Normal should always keep low.
EC - Can’t Boot Status - 2
O2_PWM0~5:
Input Voltage Reference Output Voltage
P_+VCCPLL_REF_10 +VCCPLL
P_+VTTCPU_REF_10 +VTTCPU
P_+1.1V_SB_REF_10 +1.1V_SB
P_+VTTDDR_AB_REF_10 +VTTDDR_AB
P_+VTTDDR_CD_REF_10 +VTTDDR_CD
P_+1.5V_SB_REF_10 +1.5V_SB
EC - Can’t Boot Status - 3
O2_GPO2~3:
Load default -> check status : (1, 1)
X79 series models use these two pins to control BLK frequency
BCLK
EC - Can’t Boot Status - 4
O2_GPI1 & O2_GPO1: Correct: O2_GPI1:H & O2_GPO1:H
J_SILENT#(PROCHOT#): If this pin of X79 series model is pulled low at S5, it can’t boot up.
EC - Can’t Boot Status - 5
O_PWRBTN#IN_R& O_RSTCON#: Can’t Keep Low
O2_CUT_PSON#: To keep PWRBTN motion AC Power On -> PWM signal ready -> O2_CUT_PSON#: H
When starting to USB BIOS flashback, this pin is also low.
EC - Can’t Boot Status - 6
SMBUS & O2_SMB_SWITCH:
Hang”0d0c” : EC check internal register setting of each DIGI+ Power Control.
EC - Hang 0d0c Status
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
P9X79 SIO(6776F) – FEATURES
33M
Hz
LPC Interface
PECIPlatform Environment
Control Interface
SMBus
H/W Monitor
PORT 80
Deep S5
KBMS
ACPIAdvanced Configuration
and Power Interface
GPIO
COM1
FAN OUT
PCH
RSTOUT New CPU
48MHzClock Gen
3.3V Power
P9X79 SIO(6776F) Pin Description
• ASP1000 and ASP1101 are all DIGI power controller, all BIOS setting function can transmit signals through SMBUS to change or adjust IC internal value and in
order to get all DIGI VRM function.
DIGI VRM IC Introduction
• Vcc=3.3V• Vinsen = 0.86V• VRHot = Vcc• EN=3.3V
DIGI VRM IC Introduction - VCORE
The Sequence:VCC->Vinsen->VRHot->EN
Others Signals:1. VSEN (FB+)2. RRES3. V18A4. VR_READY5. PIN17~196. SMBus7. PWM signal
7.5 K Ohm
ASP1000
• Vcc=3.3V• Vinsen = 0.86V• VRHot = Vcc• EN=3.3V
DIGI VRM IC Introduction - Vccsa
The Sequence:VCC->Vinsen->VRHot->EN
ASP1101
7.5 K Ohm
• Vcc=3.3V• Vinsen = 0.38V• VRHot = 3VSB• EN=1V
DIGI VRM IC Introduction – 1.5VDUAL
The Sequence:VCC->Vinsen->VRHot->EN
7.5 K Ohm
ASP1101
Repairing For NO VCORE
When the debug card shows 00, the CPU or sequence can’t run completely.
(1) Visually inspect: (wrong parts, components missing …)
(2) Measure the impedance (component solder on the board) A. The impedance of each power circuit is short with GND or not. B. Each MOS, the impedance of the H-S or L-S MOS GS side is K level, C. the impedance of DS side can’t be zero D. Compare the difference with a golden compare .
(3) Power on and check each voltage
Step 1:Multi-meter in Ω level : “+” side connects with Source, “-” side connects with Gate. Let MOSFET going into the cut-off state.
Step 2: Multi-meter in diode level : “+” side connects with Source, “-” side connects with drain, measure Vf: 0.3V ~ 0.6V
Step 3: Multi-meter in resistance level :
“+” side connects with drain, “-” side connects with source Value: xM Ω, ~ ∞ Ω,“+” side connects with drain, “-” side connects with gate Value: xM Ω, ~ ∞ Ω
“+” side connects with source, “-” side connects with gate Value: xM Ω, ~ ∞ Ω
Step 4:
Multi-meter in resistance level : “+” side connects with gate, “-” side connects with source ,to turn on MOSFET “+” side connects with drain, “-” side connects with source Value: 0Ω ~~ 10 Ω
How To Identify MOS Is Normal
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
Power of VCCPLL
Controlling from EC
1. VIN2. Control PIN3. REF4. VOUT
Power:1. 3V2. +VCCPLL_13. +VCCPLL
Power of 1.5V_SB
1. VIN2. Control PIN3. REF4. VOUT
UP0109
GNDGND
3V
0ohm5V
P_+1.5V_SB_REF_10
4
8
1.5V_SB
Power:3V => +1.5V_SB
+d
Power of VTTCPU eCircuit
Power of VTTCPU – Block Diagram
SIO
PR217
P_+VTTCPU_FB_R1_10
O_+VTTCPU_OV#
Power:12V=>+VTTCPU
Power of 1.1V_SB eCircuit
5V
0
Power of 1.1V_SB – Block Diagram
SIO
PR527
P_+1.1V_SB_FB_R1_10
O_+1.1V_SB_OV#
• Intel X79 Platform Structure• P9X79 Series Architecture • New Feature• Difference With P8 Series• Clock Distribution• Power Flow & Critical Power on X79 Platform• Power Sequence• Embedded Controller Introducing• SIO and Other Power Chipset Introducing• Power theory and working condition• Communication BUS Introducing
P9X79 – Agenda
DMI
PCHCPU
VCOREVTTCPUVSA_CPUVCCPLL1.5VDUAL_CD1.5VDUAL_AB
C_CPUC_CPU#C_CPU_QPIC_CPU_QPI#
H_CPUPWRGDH_CPURST#
3V3VSB1.1V_SB1.5V_SB1.1V_SB_VCCDMIPLL
C_PCH_DMIC_PCH_DMI#32.768 Hz
O_PWROKS_VRMPWRGDS_PLTRST#
DMI_ZCOMP
DMIRBIAS
DMI
H_DMI_TXP[3:0]
H_DMI_TXN[3:0]
H_DMI_RXP[3:0]
H_DMI_RXN[3:0]PCHCPU
SPI
PCH
3V3VSB1.1V_SB1.5V_SB
C_PCH_14M32.768 Hz
O_PWROKS_VRMPWRGDS_PLTRST#
F1U1
O2U6
3V_SPI (3VSB) F1_SPI_HOLD#O_BIOS_WP#
5VSBO2_SPI_SWITCH (From EC)
SPI
PCH
F1U1
O2U6
EC
F_SPI_MOSI
F_SPI_MISO
F_SPI_CS1#
O2_SPI_MOSI_OUT
O2_SPI_MISO_OUT
O2_SPI_CS1#_OUT
O2_SPI_CLK_OUT
F_SPI_CLK
O2_SPI_MOSI_R
O2_SPI_MISO_R
O2_SPI_CS1#_R
O2_SPI_CLK_R
O2_SPI_SWITCH (From EC)
MEMORY
CPU
MEMORY
VCOREVTTCPUVSA_CPUVCCPLL1.5VDUAL_CD1.5VDUAL_AB
H_DRAMVREFDQ_TX_CDH_DRAMVREFDQ_TX_ABH_DRAMVREFDQ_RX_CDH_DRAMVREFDQ_RX_AB
H_DDR_CD_1V05_SDAH_DDR_AB_1V05_SDAH_DDR_CD_1V05_SCLH_DDR_AB_1V05_SCL
H_DRAMPWROK_CDH_DRAMPWROK_ABD3_MEMHOT#_ABD3_MEMHOT#_CD
3V1.5VDUAL_CD1.5VDUAL_AB+VTTDDR_AB+VTTDDR_CDD3_VREFDQ_A~DD3_VREFCA_A~D
D3_M[A~D]_CLK[3:0]D3_M[A~D]_CLK#[3:0]
D3_RESET#ABD3_RESET#CD
H_DDR_CD_3V3_SDAH_DDR_AB_3V3_SCLH_DDR_CD_3V3_SDAH_DDR_AB_3V3_SCL
MEMORY
CPU
MEMORY
D3_DQ_A[64:0]
D3_DQS_A[7:0]
D3_DQS_A#[3:0]
D3_MAA[15:0]
A~D
A~D
LPC
PCH
3V3VSB1.1V_SB1.5V_SB
C_PCH_14MC_PCI_PCH32.768 Hz
O_PWROKS_VRMPWRGDS_PLTRST#
SIO
3V3VSB_ATXVTTCPU
C_48M_SIOC_PCI_SIO
O_PWROK_SIOS_PLTRST#
SIO
LPC
PCH
SIO
F_SERIRQ#
F_FRAME
F_LAD[3:0]
F_DRQ#0
P9X79 Series – Q&A
~THANK YOU~
~Q &A~