Computer Data Communications Chapter 5 1 Serial Communications Interfaces oThe EIA RS-232D Standard oRS-232 Signal Characteristics oRS-232 Pin Assignments

Computer Data Communications Chapter 5

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Serial Communications Interfaces

oThe EIA RS-232D Standard

oRS-232 Signal Characteristics

oRS-232 Pin Assignments and Cables

Null Modem

Error Control

oParity Check

oBlock Character Check

oBlock Checksum

oPolynomial Codes

oHamming Codes


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The EIA RS-232D Standard defines a range of bit rates, from 0 to 115,000 bps A range of cable lengths, and cables up to 50 feet The physical requirements for a serial interface. Provide the connectivity between the PC and the

modems Other devices, such as serial printers, can be

configured as DCE or DTE devices, To communicate directly between a PC and another

computer


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Figure 1 : EIA RS-232D Interface applications


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RS-232 Signal Characteristics It is necessary to agree on data

and control signals. Provides voltage ranges for data

and control signals Figure 2 shows these ranges.

Useful to hardware vendors and designer of serial ports and modems.

The operation of these signals is not visible to a user


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RS-232 Signal Characteristics

Figure 2 : EIA RS-232D Signal Levels


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RS-232 Pin Assignments and Cables Typical signals used, however are pins, 2, 3, 4, 5, 6,

7 ,8 20 and 22. A communication cable transmits the RS-232D

signals to and from a serial port. Modems have a DB-25 female connectors, which

requires a cable with a DB-25 male connector Most PCs standard serial ports uses DB-9 male

connectors


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Figure 3 : EIA RE-232D pin layout and assignments


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Diagram of DB-9 pin assignments and how they must be communicate with a DB-25 connector at a DCE (modem).


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Null Modem To connect two computers using a device called a null modem or

modem eliminator. A null modem, which is not a modem at all, is a cable or set of

connectors designed to eliminate the need for a modem. The null modem makes each computer operate as if it were

communicating with a modem. Without the addition of a null modem, the PCs cannot communicate

directly.


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A PC’s asynchronous port is communicating with an asynchronous modem.The two devices have compatible transmit and receive signals

The two PC asynchronous ports are both expecting to receive and send data on the same lines.

Figure 4: Computer and modem interfaces

Figure 5: Incompatible DTE to DTE connection


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Figure 6 : Null modem connection diagram.


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i) Single-Bit Errorii) Burst Error

Types of ErrorTypes of Error

Error Detection and CorrectionError Detection and Correction

Data can be corrupted during transmission. For reliable communication, errors must be detected and corrected.


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Single-Bit ErrorIn a single-bit error, only one bit in the data unit has changed


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Burst Error

A burst error means that 2 or more bits in the data unit have changed.


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Error Detection MechanismsError Detection Mechanisms

The two broad categories of error detection mechanisms are:

Forward error control Feedback error control


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Forward error control

Character frame contains a more comprehensive form of redundant information. So that the receiver is able to detect and correct the erroneous information.

It is used in simplex communication mode and in situation where retransmission is not possible. For example: Radio broadcast in which there are many receivers for one transmission.

Disadvantages: Expensive and number of additional bits (oh) increases rapidly as the number of information bits increases.


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Feedback error control

Character frame includes only sufficient additional information for the receiver to detect errors are present and employ retransmission to request the another correct copy of the errorneous information be sent.

Advantages: It is simple to use and extremely effective. Disadvantage: The multiple retransmission can reduce the

throughput to a small fraction of the link’s capacity.


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Type of Error DetectionType of Error Detection

i) Redundancy

ii) Parity Check

iii) Cyclic Redundancy Check (CRC)

iv) Checksum

Error detection uses the concept of redundancy, which means adding extra bits for detecting errors at the destination.


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RedundancyRedundancy


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Parity CheckParity Check

• Common in ‘small’ information

• Common when probability of error is low

• Can be odd or even

• Only one extra bit is added

In parity check, a parity bit is added to every data unit so that the total number of 1s is even or odd . With even parity, another bit is added to produce an even number of binary 1s. With odd parity, another bit is added to produce an odd number of binary 1s.


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Even-parity conceptEven-parity concept


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Example 1Example 1

Suppose the sender wants to send the word world. In ASCII the five characters are coded as

1110111 1101111 1110010 1101100 1100100

The following shows the actual bits sent if EVEN parity is used.

11101110 11011110 11100100 11011000 11001001


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Example 2Example 2

Now suppose the word world in Example 1 is received by the receiver without being corrupted in transmission.

11101110 11011110 11100100 11011000 11001001

The receiver counts the 1s in each character and comes up with even numbers (6, 6, 4, 4, 4). The data are accepted.


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Example 3Example 3

Now suppose the word world in Example 1 is corrupted during transmission.

11111110 11011110 11101100 11011000 11001001

The receiver counts the 1s in each character and comes up with even and odd numbers (7, 6, 5, 4, 4). The receiver knows that the data are corrupted, discards them, and asks for retransmission.

Simple parity check can detect all single-bit errors. It can detect burst errors only if the total number of errors in each data unit is odd.


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Two-dimensional parityTwo-dimensional paritya.k.a BCC or 2 coordinate parity check


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Example 4Example 4

Suppose the following block is sent:

10101001 00111001 11011101 11100111 10101010

However, it is hit by a burst noise of length 8, and some bits are corrupted.

10100011 10001001 11011101 11100111 10101010

When the receiver checks the parity bits, some of the bits do not follow the even-parity rule and the whole block is discarded.

10100011 10001001 11011101 11100111 10101010

In two-dimensional parity check, a block of bits is divided into rows and a redundant row of bits is added to the whole block.


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10101001 00111001 11011101 11100111 10101010

1 0 1 0 0 0 1 1

0 0 0 0 1 0 0 1

1 1 0 1 1 1 0 1

1 1 1 0 0 1 1 1

1 0 1 0 1 0 1 0

0 0 0 0 0 0

1 0 1 0 1 0 0 1

0 0 1 1 1 0 0 1

1 1 0 1 1 1 0 1

1 1 1 0 0 1 1 1

1 0 1 0 1 0 1 0

0 0 0 0 0 0 0

Two-dimensional parity – detect multiple errorsTwo-dimensional parity – detect multiple errors

Error detected

HorizontallyError notdetected


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10101001 00111001 11011101 11100111 10101010

1 0 1 0 0 0 0 0

0 0 1 1 1 0 0 1

1 1 0 1 1 1 0 1

1 1 1 0 0 1 1 1

1 0 1 0 1 0 1 0

0 0 0 0 1 0 0

1 0 1 0 1 0 0 1

0 0 1 1 1 0 0 1

1 1 0 1 1 1 0 1

1 1 1 0 0 1 1 1

1 0 1 0 1 0 1 0

0 0 0 0 0 0 0

Two-dimensional parity – correct single errorTwo-dimensional parity – correct single error

Error dictated

HorizontallyError detected

Error corrected to 1


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CRC (Cyclic Redundancy Check)CRC (Cyclic Redundancy Check)

CRC appends a few bits to the end of the bit string

The receiver performs a computation which should yield 0 forError free message.

Yield of Non 0 means there has been an error in one or more bits

CRC can detect an impressive range of error but not all.

32 bits of CRC is sufficient for 12KB of messages for the Ethernet.


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CRC generator and checkerCRC generator and checker


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Polynomial CodesPolynomial Codes

-Provide a reliable detection scheme against error bursts-Can also provide error correction but not normally used-Also called CRC

-Rules:

-1. Binary information is represented as a polynomial

E.g. 1 0 1 1 0 1 = x5 + x3 + x2 + 1

-2. These polynomials obeys the law of algebra but addition is base2 & NO carry is generated.

-i.e. -1+1=0, 1+0=1; 0+1=1; 0+0=0;

-Subtraction is equivalent to addition


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A polynomialA polynomial


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A polynomial representing a divisorA polynomial representing a divisor


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Method:

Message = G (x)CRC generating polynomial = P(x) of order n

Remainder R(x) = G(x) * Xn / P(x)

Frame Check Sequence (FRC) = G(x) * Xn + R(x)

Generating polynomialGenerating polynomial


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Message = 1 0 0 1 0 0

CRC generating polynomial = P(x) of order n

Remainder R(x) = G(x) * Xn / P(x) = 100100*1000 / 1101 = 001

Frame Check Sequence (FRC) = G(x) * Xn + R(x)= 100100001

P(x) 1 1 0 1

x3 + x2 + 1

Generating polynomialGenerating polynomial


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1 0 0 1 0 0 0 0 01 1 0 1

1

1 1 0 1

001 0

1

1 1 0 1

101 0

1

1 1 0 11 11 0

1 1 0 111

1

0

0

00 0 0 0

01 1 0

1

1 1 0 1100

When the leftmost bitof the remainder is zerowe must use 0000 insteadof the original divisor

Binary division in a CRC GeneratorBinary division in a CRC Generator


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Binary division in CRC checkerBinary division in CRC checker

Zero results means NO errorZero results means NO error


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Standard polynomialsStandard polynomials

Name Polynomial Application

CRC-8 x8 + x2 + x + 1 ATM header

CRC-10 x10 + x9 + x5 + x4 + x 2 + 1 ATM AAL

ITU-16 x16 + x12 + x5 + 1 HDLC

ITU-32x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8

+ x7 + x5 + x4 + x2 + x + 1LANs


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Example 5Example 5

It is obvious that we cannot choose x (binary 10) or x2 + x (binary 110) as the polynomial because both are divisible by x.

However, we can choose x + 1 (binary 11) because it is not divisible by x, but is divisible by x + 1. We can also choose x2 + 1 (binary 101) because it is divisible by x + 1 (binary division).


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Example 6Example 6

The CRC-12

x12 + x11 + x3 + x + 1

which has a degree of 12, will detect all burst errors affecting an odd number of bits, will detect all burst errors with a length less than or equal to 12, and will detect, 99.97 percent of the time, burst errors with a length of 12 or more.

1100000001011


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ChecksumChecksum


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Data unit and checksumData unit and checksum


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The sender follows these steps:

1. The unit is divided into k sections, each of n bits.

2. All sections are added using one’s complement to get the sum.

3. The sum is complemented and becomes the checksum.

4. The checksum is sent with the data.



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1. The receiver follows these steps:

2. The unit is divided into k sections, each of n bits.

3. All sections are added using one’s complement to get the sum.

4. The sum is complemented.

5. If the result is zero, the data are accepted: otherwise, rejected.



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Example 7Example 7

Suppose the following block of 16 bits is to be sent using a checksum of 8 bits.

10101001 00111001

The numbers are added using one’s complement

10101001

00111001 ------------Sum 11100010

Checksum 00011101

The pattern sent is 10101001 00111001 00011101


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Example 8Example 8

Now suppose the receiver receives the pattern sent in Example 7 and there is no error.

10101001 00111001 00011101

When the receiver adds the three sections, it will get all 1s, which, after complementing, is all 0s and shows that there is no error.

10101001

00111001

00011101

Sum 11111111

Complement 00000000 means that the pattern is OK.


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Example 9Example 9

Now suppose there is a burst error of length 5 that affects 4 bits.

10101111 11111001 00011101

When the receiver adds the three sections, it gets

10101111

11111001

00011101

Partial Sum 1 11000101

Carry 1

Sum 11000110

Complement 00111001 the pattern is corrupted.


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(m+r+1) ≤ 2r

Data and redundancy bits (Hamming Code)Data and redundancy bits (Hamming Code)

Number ofdata bits

m

Number of redundancy bits

r

Total bits

m + r

1 2 3

2 3 5

3 3 6

4 3 7

5 4 9

6 4 10

7 4 11


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r is also known as the check bit.

Positions of redundancy bits in Hamming codePositions of redundancy bits in Hamming code


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All bit positions that are powers of two are used as parity bits. (positions 1, 2, 4, 8, 16, 32, 64, etc.)

All other bit positions are for the data to be encoded. (positions 3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 17, etc.)

Each parity bit calculates the parity for some of the bits in the code word. The position of the parity bit determines the sequence of bits that it alternately checks and skips.

Position 1 (n=1): skip 0 bit (0=n−1), check 1 bit (n), skip 1 bit (n), check 1 bit (n), skip 1 bit (n), etc. (1,3,5,7,9,11,13,15,...)

Position 2 (n=2): skip 1 bit (1=n−1), check 2 bits (n), skip 2 bits (n), check 2 bits (n), skip 2 bits (n), etc. (2,3,6,7,10,11,14,15,...)

Position 4 (n=4): skip 3 bits (3=n−1), check 4 bits (n), skip 4 bits (n), check 4 bits (n), skip 4 bits (n), etc. (4,5,6,7,12,13,14,15,20,21,22,23,...)

Position 8 (n=8): skip 7 bits (7=n−1), check 8 bits (n), skip 8 bits (n), check 8 bits (n), skip 8 bits (n), etc. (8-15,24-31,40-47,...)



General rule for position n: skip n−1 bits, check n bits, skip n bits, check n bits... And so on.

General Algorithm Hamming codeGeneral Algorithm Hamming code


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Redundancy Hamming code Bit Redundancy Hamming code Bit CalculationsCalculations

This general rule can be shown visually:

Bit position1 2 3 4 5 6 7 8 9

10

11

12

13

14 1516

17 18 19 20

...

Encoded data bits

p1

p2

d1

p3

d2

d3

d4

p4

d5

d6

d7

d8

d9

d10

d11

p5

d12

d13

d14

d15

Paritybit

coverage

p1 X X X X X X X X X X

p2 X X X X X X X X X X

p3 X X X X X X X X X

p4 X X X X X X X X

p5 X X X X X


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Redundancy Hamming Code bits calculationRedundancy Hamming Code bits calculation


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Example of redundancy bit calculationExample of redundancy bit calculation


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Error detection using Hamming codeError detection using Hamming code

Documents

Computer Data Communications Chapter 5 1 Serial Communications Interfaces oThe EIA RS-232D Standard oRS-232 Signal Characteristics oRS-232 Pin Assignments