Comparator Generation and Selection for Highly LinearCMOS Flash Analog-to-Digital Converter�

Jincheol Yoo (jyoo@cse.psu.edu )Department of Computer Science & Engineering,The Pennsylvania State University, PA 16802

Kyusun Choi (kyusun@cse.psu.edu )Department of Computer Science & Engineering,The Pennsylvania State University, PA 16802

Daegyu Leei-Network Team, Samsung Advanced Institute of Technology, Suwon 440-600, Korea

Abstract. This paper presents a comparator generation and selection method to reduce thelinearity errors - DNL and INL - for a CMOS flash analog-to-digital converter (ADC) basedon threshold inverter quantization (TIQ) technique. The TIQ flash ADC requires2

n� 1 com-parators like conventional flash ADCs. However, each comparator in the TIQ flash ADC hasdifferent sizes to provide internal reference voltages, while the differential comparators haveidentical sizes. The design method has been incorporated into a software package and the2n� 1 optimized TIQ comparator layouts are generated as an output of the software package.

The linearity errors against the CMOS process, power supply voltage, and temperature varia-tions are significantly improved by the proposed comparator generation and selection methodfor the TIQ flash ADC. Especially, the DNL dependence on the CMOS process variation canbe almost eliminated. The simulation results show 82.6 % of DNL and 32.5 % of INL im-provements against CMOS process variation. For the other variations - power supply voltageand temperature - 43.5 % for DNL and 6.0 % for INL improvement has been achieved. Theprototype chips have been fabricated and the chip test results confirms the simulation results.

Keywords: Flash ADC, TIQ comparator, DNL, INL, Optimal design method, Automaticgeneration

Abbreviations: ADC – Analog-to-Digital Converter; TIQ – Threshold Inverter Quantization;SoC – System-on-Chip; CMOS – Complementary Metal Oxide Semiconductor

1. Introduction

The flash analog-to-digital converter (ADC) architecture[15, 3, 5] is mainlyknown for its fastest speed. Therefore, it is used for high speed and wide band-width applications. However, the flash ADC attributes are larger amount ofpower consumption and larger die size in comparison to the other ADCs suchas pipelined[2, 7] and successive approximation register (SAR) ADCs[6]. To-day’s system-on-chip (SoC) trend forces ADCs to be integrated with complex

� This work was supported in part by Pittsburgh Digital Greenhouse (EDTD00-2) througha grant from the Commonwealth of Pennsylvania, Department of Community and EconomicDevelopment.

c 2002Kluwer Academic Publishers. Printed in the Netherlands.

jaicsp3.tex; 16/11/2002; 0:45; p.1

2

digital processors and memory on a single chip. The major considerations indesigning ADCs for this SoC trend are high speed operation and low powerconsumption. A new flash ADC architecture - especially focused on the com-parator - has been devised by authors[11, 12] to further improve high speedconversion rate while maintaining comparable power consumption. The newflash ADC is called threshold inverter quantization (TIQ) flash ADC becauseit utilizes two cascading CMOS inverters as a voltage comparator. The TIQflash ADC can be applied to low power applications such as mobile systemsby changing the resolution of the ADC on demand to prolong the battery life.Such low power application ADC has been explored and it is called powerand resolution adaptive flash ADC[13].

The TIQ flash ADC can operate at the high speed with reasonable lowpower consumption and satisfy today’s SoC trend. But, a designer should becareful in designing the TIQ comparator. Unlike the differential comparators,a set of TIQ comparators has different size transistors, in order to internallygenerate2n � 1 different reference voltages for ann-bit resolution. Theseinternal reference voltages are sensitive to the CMOS process, power supplyvoltage, and temperature variations. The static errors - offset, gain, and lin-earity errors - are critical in designing the TIQ comparator. In this paper, theauthors present a comparator generation and selection method of the CMOSTIQ comparator to reduce the linearity errors.

2. TIQ Comparator

Threshold inverter quantization is a unique way to realize a comparator fora high speed CMOS flash ADC. A TIQ comparator essentially exploits theVoltage Transfer Characteristic (VTC) curve of an inverter as described inFigure 1(a). By varying its transistor sizes, the comparison voltage,Vm, canbe changed. Figure 1 shows the comparison of the TIQ comparator circuit anda differential comparator circuit in a traditional flash ADC. The circuits aredifferent but the VTC curves are similar. A key difference between the dif-ferential comparator and the TIQ comparator is how to supply their referencevoltages. The differential comparator utilizes the external reference voltage,Vr, using a resistor ladder circuit. TheVr directly depends on a resistor tapposition. However, the TIQ comparator sets its switching threshold voltage,Vm, internally as the built-in reference voltage, based on its transistor sizes.Unlike the conventional flash ADC whose comparators are all identical insize, the TIQ based ADC has individual comparators in all different sizes.To construct ann-bit flash TIQ based ADC, one must find2n � 1 differentinverters. Each has differentVm value, and one must arrange them in theorder of theirVm value. For a 6-bit ADC, 63 individual TIQ comparators areneeded as shown in Figure 2(a). Each of 63 TIQ comparators has different

jaicsp3.tex; 16/11/2002; 0:45; p.2

3

Vout

Vref

VoutVin

(a) TIQ comparator

Vout

VinVm VinVr

Vout

(b) Differential comparator

Vdd

Vin

Vr

Figure 1. The comparison of the TIQ comparator and a differential comparator

Vm63

Vm62

Vm61

Vm2

Vm1

Vin Vout63

Vout62

Vout61

Vout2

Vout1

(a) Schematic of the 6bit TIQ comparator

Vm1 Vm2

Vout

VinVm63Vm62Vm61

(b) VTC curves of 63 comparators

Figure 2. Schematic and VTC curves of the 6-bit TIQ comparator

sized transistors leading them to have differentVm from each other. EachVmis defined on its VTC curve in Figure 2(b)

The TIQ comparator is a pure inverter circuit, and is inherently faster andsimpler than the differential comparator. It has the following advantages:

� Clock signals, switches, or coupling capacitors are not necessary.

� Uses standard digital CMOS process, makes the TIQ comparator highlysuitable for SOC.

� Only two transistors are in between the power supply rails. The TIQcomparator realization is possible with the advanced CMOS technologybelow 0.1�m feature size and below 1.0V power supply voltage.

jaicsp3.tex; 16/11/2002; 0:45; p.3

4

3. Comparator Generation and Selection Method

The TIQ flash ADC requires2n�1 different size comparators and the authorsneed to effectively find them to correctly implement the TIQ comparators.However, choosing the neededVm from many candidates for comparators andgenerating the selected comparators with custom layout are difficult jobs. Forexample, a 10-bit flash ADC would need 1023 TIQ comparators, too manyfor manual layout designs, while other ADCs use a single comparator designand simply duplicate it for2n� 1 times. The authors developed a customizedprogram that automatically generates the TIQ comparators with an optimalselection approach.

A CMOS inverter consists of one PMOS and one NMOS transistors, withthe inverter switching threshold voltage depending upon the transistor sizes.If one fixes the length of both the PMOS and NMOS transistors at a constantsize, one can obtain different inverter switching threshold voltages (Vm inFigure 1) by simply varying the transistors’ widths. Figure 3 shows the 3-Dplot of Vm as the function of PMOS and NMOS transistor widths.

05

10 0 5 10 15 20

0.6

0.8

1

1.2

1.4

1.6

1.8

2

PMOS (um)

Vm

(V

)

NMOS (um)

Figure 3. The 3-D plot of the inverter switching threshold voltages,Vm, as the function ofPMOS and NMOS transistor widths

To design an n-bit ADC, one needs2n�1 equal quantization voltages, andone must decide on maximumVm and minimumVm. After deciding the max.Vm and min.Vm, one computes LSB voltage step (VLSB) by (max.Vm - min.Vm)/(2n�2). There are two different design methods for the TIQ comparatorwith Figure 3. One method - called Zero DNL design method - can obtain the2n�1 reference voltages by selecting the inverter width from the full range ofthe 3-D surface without considering the relation of adjacent comparators. Theother method -called Non-zero DNL design method - considers the relationof comparators in selection of the inverter size. Detailed descriptions andcomparisons are explained in the following sections.

jaicsp3.tex; 16/11/2002; 0:45; p.4

5

(a) Zero DNL 6-bit TIQcomparator design

(b) Non-zero DNL Optimized6-bit TIQ comparator design

Vm1Vm1

NMOS

PMOS

NMOS

PMOS

Vm63 Vm63

Figure 4. Two design methods of the 6-bit TIQ comparator design

3.1. ZERO DNL DESIGN METHOD

The zero DNL design method simply chooses theVm from the full-range ofthe 3-D plot (around 2 million points). This algorithm selects the actualVmthat is the closest the idealVm, theoretical points that are exactly spaced byVLSB, regardless of the transistor size relationship with other comparators.This method needs much time to find aVm, because it checks all points ofthe 3-D plot. As a result, all internal reference voltages of2n�1 comparatorsare almost equally divided byVLSB. Hence, the DNL - defined by((V 0

i+1 �

Vi)=VLSB) � 1 - of this approach is almost zero. A 6-bit TIQ comparatorlayout from the zero DNL design method is shown in Figure 4(a). The sizeincreasing/decreasing of transistors is not systematic.

3.2. NON-ZERO DNL DESIGN METHOD

In case of the Non-zero DNL design method, it selects theVm from thereduced-range of the 3-D plot. The diagonal line shown in Figure 3 is the idealline for this approach. This approach keeps the systematic increasing/decreasingorder of transistor sizes. But, the diagonal line is too small range to findproper2n�1 reference voltages. Therefore, the range is expanded around thediagonal line. The authors get systematic increasing/decreasing comparator intransistor size as shown in Figure 4(b) by considering the relation of adjacentcomparators.

jaicsp3.tex; 16/11/2002; 0:45; p.5

6

The algorithm developed by the authors determines the best fitVm valuesaround the diagonal line in Figure 3, keeping the increasing/decreasing or-der of transistor sizes. The algorithm also enforces the incremental transistorsize step to a certain minimum width (�W), which is initially given, for themaximum resolution of the given CMOS technology. This method uses thefollowing four steps to generate the2n � 1 TIQ comparators:

� Step 1: Generating a set of inverter sizes roughly following the diagonalline. The max.Vm, min.Vm, and�W are needed for this step.

� Step 2: FindingVm of each inverters produced in Step 1 through HSPICEsimulation. This step takes much more time. When the authors used5 Sun-Blade 2000 machines at the same time, this step took around 4hours for finding 28000 points.

� Step 3: Selecting a set of2n� 1 inverters among the inverters generatedin Step 1, whoseVm voltages are the nearest to the ideal one, satisfyingthe following conditions simultaneously;

� Does each comparator keep the order of increasing/decreasing tran-sistor sizes?

� Does the minimum�W placed between two adjacent comparatorsentirely?

� Step 4: Generating a cell design of the TIQ comparators based on theselected set of inverters in Step 3. With this automatic generation, theauthors can obtain the TIQ comparator layout in a few seconds A 6-bitTIQ comparator manual design takes around 4 hours.

Figure 5 shows an example of how the algorithm generates a set of tran-sistor sizes and chooses the best fit (optimal) ones among them. From everypossible combination of PMOS and NMOS transistor sizes, the program firstarranges them along the diagonal line. Next, the program selects the optimalcombinations by looking up theVm values of each combination resulted fromthe HSPICE simulation. The filled black dots are the selected combination ofPMOS and NMOS transistor sizes for the TIQ inverters.

3.3. COMPARISON OF TWO DESIGN METHODS

Two 6-bit TIQ comparators has been design with 0.25�mCMOS technology.One with the zero DNL design method and the other one with the non-zeroDNL design method. Initially the 6-bit comparator with the non-zero DNLdesign method has larger value of DNL and INL. However, choosing invertertransistor sizes from the diagonal line ensures the monotonic size increaseand decrease of PMOS and NMOS transistors, respectively. This makes the

jaicsp3.tex; 16/11/2002; 0:45; p.6

7

W

WNMOS

PMOS

: Selected combination: Arranged combination

Figure 5. An example of how the programs generate a set of transistor sizes and choose theoptimal ones

DNL and INL of the ADC to be less sensitive to the CMOS process variation.The 22 HSPICE parameters provided by MOSIS and 5 TSMC parameters areused to check process variation. The simulation results of the Figure 6 andTable I show that the DNL and INL of the zero DNL design method aremuch more sensitive to the process variation than those of the non-zero DNLdesign method.

For the process variation, the non-zero DNL design method can reduce DNLand INL to 82.6 % and 32.5 % on average compared to those of zero DNL de-sign method, respectively. Table II shows the effectiveness of non-zero DNLdesign method over power supply voltage and temperature variations. For thepower supply voltage and temperature variations, 43.5 % reduction for DNLand 6.0 % reduction for INL are achieved. Again, the key feature in non-zero DNL design method is to maintain the monotonicity of transistor sizechanges so that the resulting ADC will have consistent DNL limits againstthe process, power supply voltage, and temperature variations.

jaicsp3.tex; 16/11/2002; 0:45; p.7

8

Table I. Process variation simulation results

process Max. DNL of Max. DNL of Max. INL of Max. INL of

Figure 4(a) Figure 4(b) Figure 4(a) Figure 4(b)

tsmc-tt 0.0023 LSB 0.0114 LSB 0.0013 LSB 0.0083 LSB

tsmc-ff 0.1384 LSB 0.0414 LSB 0.5839 LSB 0.5265 LSB

tsmc-fs 0.0134 LSB 0.0142 LSB 0.1140 LSB 0.1155 LSB

tsmc-sf 0.0140 LSB 0.0158 LSB 0.1190 LSB 0.1164 LSB

tsmc-ss 0.1399 LSB 0.0424 LSB 0.4954 LSB 0.4293 LSB

t08p-epi 0.9277 LSB 0.1028 LSB 1.1109 LSB 0.6823 LSB

t08p-ne 0.7054 LSB 0.0825 LSB 1.0058 LSB 0.6420 LSB

t09a-epi 0.9695 LSB 0.0790 LSB 0.7746 LSB 0.4836 LSB

t09a-ne 0.8278 LSB 0.0958 LSB 1.2349 LSB 0.7610 LSB

t0bl-epi 1.0548 LSB 0.0872 LSB 1.0539 LSB 0.6096 LSB

t0bl-ne 0.8946 LSB 0.0885 LSB 1.0335 LSB 0.6172 LSB

t11y-epi 0.9425 LSB 0.0431 LSB 0.5388 LSB 0.2581 LSB

t11y-ne 1.0289 LSB 0.0598 LSB 0.8105 LSB 0.3986 LSB

t13m-epi 1.1652 LSB 0.0832 LSB 0.6712 LSB 0.4954 LSB

t13o-epi 0.6815 LSB 0.0482 LSB 0.4142 LSB 0.3088 LSB

t14y-epi 0.9827 LSB 0.1055 LSB 1.1881 LSB 0.7065 LSB

t15h-epi 1.1302 LSB 0.0694 LSB 0.6809 LSB 0.4310 LSB

t16r-epi 0.8226 LSB 0.0687 LSB 0.5629 LSB 0.4220 LSB

t17a-epi 0.9733 LSB 0.0732 LSB 0.6464 LSB 0.4558 LSB

t18i-epi 1.0313 LSB 0.0840 LSB 0.8050 LSB 0.5284 LSB

t19o-epi 0.9317 LSB 0.0864 LSB 0.8417 LSB 0.5522 LSB

t1ab-epi 0.9246 LSB 0.0458 LSB 0.5458 LSB 0.2530 LSB

t1cj-epi 0.9578 LSB 0.0553 LSB 0.5122 LSB 0.3327 LSB

t21q-epi 0.5672 LSB 0.0436 LSB 0.3692 LSB 0.2762 LSB

t23c-epi 0.9806 LSB 0.0655 LSB 0.5564 LSB 0.3992 LSB

t25t-epi 0.8805 LSB 0.0533 LSB 0.7442 LSB 0.3982 LSB

t27h-epi 0.6261 LSB 0.0397 LSB 0.6181 LSB 0.3441 LSB

Table II. power supply voltage and temperature variations

variation Max. DNL of Max. DNL of Max. INL of Max. INL of

Figure 4(a) Figure 4(b) Figure 4(a) Figure 4(b)

2.375V 0.0365 LSB 0.0169 LSB 0.1450 LSB 0.1306 LSB

2.625V 0.0309 LSB 0.0155 LSB 0.1483 LSB 0.1337 LSB

-40oC 0.0634 LSB 0.0459 LSB 0.4449 LSB 0.4330 LSB

85oC 0.0617 LSB 0.0353 LSB 0.4392 LSB 0.4324 LSB

jaicsp3.tex; 16/11/2002; 0:45; p.8

9

0 10 20 30 40 50 60−1

−0.5

0

0.5

1

OUTPUT CODE

DN

L (

LS

B)

tsmc−tttsmc−ffn94s

0 10 20 30 40 50 60−1.5

−1

−0.5

0

0.5

1

1.5

OUTPUT CODE

INL

(L

SB

)

tsmc−tttsmc−ffn94s

0 10 20 30 40 50 60−1

−0.5

0

0.5

1

OUTPUT CODE

DN

L (

LS

B)

tsmc−tttsmc−ffn94s

0 10 20 30 40 50 60−1.5

−1

−0.5

0

0.5

1

1.5

OUTPUT CODE

INL

(L

SB

)

tsmc−tttsmc−ffn94s

(a) DNLs of zero DNL design (b) DNLs of non-zero DNL design

(d) INLs of non-zero DNL design(c) INLs of zero DNL design

Figure 6. DNLs and INLs of the two 6-bit TIQ comparators

4. Simulation Results of the TIQ flash ADCs

To verify the functionality of the TIQ comparator as well as to confirm theDNL and the INL improvements over the CMOS process parameter varia-tion, the 6-bit[11], 8-bit[12], and 9-bit TIQ flash ADCs were designed andfabricated, targeted for 0.25�m digital CMOS process. Figure 7 shows thelayout of the 8-bit TIQ flash ADC with non-zero DNL comparator designmethod. The TIQ flash ADC consists of the TIQ comparator, gain booster, 01generator, and ROM type encoder for binary code output. Table III shows thesummary of the design simulation results of the 6-bit and 8-bit ADCs.

Table III. The 6-bit and 8-bit ADC simulation results

6bit 8bit

Speed 1.1 GSPS 1 GSPS

Area 0.043mm2 0.228mm2

Power 59.91mW 256.09mW

Vm range 0.7477V -1.6480V 0.7477V -1.6480V

VLSB 0.0145V 0.0035V

jaicsp3.tex; 16/11/2002; 0:45; p.9

10

EncoderGain booster

01 GeneratorTIQ comparators

Figure 7. The 8-bit TIQ flash ADC layout

Table IV shows the 6-bit and 8-bit ADCs’ key parameters in comparison toother ADC designs in recent literature. One can easily recognize that theTIQ based ADCs operate with higher speed and comparably lower powerconsumption.

Table IV. Comparisons to other high speed ADCs

ADCs Technology Speed Power

[11]6-bit TIQ CMOS 0.25�m 1.1 GSPS 59.91mW

[12]8-bit TIQ CMOS 0.25�m 1 GSPS 256.09mW

[1]6-bit Flash GaAs 0.5�m 2 GSPS 970mW

[4]6-bit Flash CMOS 0.6�m 0.2 GSPS 380mW

[8]4-bit Flash GaAs 0.8�m 1.18 GSPS 185.6mW

[9]6-bit Flash CMOS 0.4�m 0.5 GSPS 400mW

[10]8-bit Pipeline CMOS 0.6�m 0.15 GSPS 395mW

[14]6-bit Flash CMOS 0.6�m 0.5 GSPS 330mW

jaicsp3.tex; 16/11/2002; 0:45; p.10

11

5. Measurements

The prototype chips have been fabricated in 0.25�m digital CMOS process,each containing the 6-bit, 8-bit, and 9-bit TIQ based ADCs with the non-zero DNL design method. The initial chip testing results show that the 6-bitADC is working in full precision shown in Figure 8(a) but with lower speedand lower power consumption than the simulation results. The authors have

(a) Oscilloscope display of the 6-bit TIQ flash ADC

(b) Oscilloscope display of the 9-bit TIQ flash ADC

(c) Oscilloscope display with power supply noise

Figure 8. Display of 6-bit TIQ ADC operation

observed maximum 250 mega samples per second (MSPS) sampling rate with

jaicsp3.tex; 16/11/2002; 0:45; p.11

12

0 10 20 30 40 50 60−0.5

−0.4

−0.3

−0.2

−0.1

0

0.1

0.2

0.3

0.4

0.5

OUTPUT CODED

NL

(L

SB

)0 10 20 30 40 50 60

−1.5

−1

−0.5

0

0.5

1

1.5

OUTPUT CODE

INL

(L

SB

)

(a) DNL of prototype chip (b) INL of prototype chip

Figure 9. DNL and INL of prototype chip

(a) Prototype chip with PC board (b) Chip die photo

Figure 10. Prototype chip and die photo

35.25mW power consumption in the 6-bit TIQ flash ADC. The 8-bit and9-bit ADCs are working in reduced precision, 7-bit and 8-bit effective pre-cisions respectively. Also, they operate at the lower speeds and lower powerconsumption levels than the simulation results. The lower precision and lowersampling rate are possibly due to the noise problem. The lower power con-sumption is mainly due to under estimation of the parasitics in simulationparameters. Figure 8(b) shows the 9-bit ADC input and output. Figure 8(c)shows the power supply noise generated by the digital switching of the 6-bitADC with a sign wave input. The DNL and the INL measurements of the 6-bit ADC prototype are 0.27 LSB and 1.20 LSB, respectively. Figure 9 showsthe plot of the measured DNL and INL of the 6-bit ADC. The inverter’ssingle ended input in the TIQ comparator causes the ADC to be susceptible tonoise. The authors are working on reducing noise in the comparator with newcomparator design method. Figure 10 shows the prototype chip test board andthe chip die photo. With 5 layers of metals, top two layers are used to routethe Vdd and GND in a grid form, none of the active area below are visible.

jaicsp3.tex; 16/11/2002; 0:45; p.12

13

6. Conclusion

The TIQ based A/D converter circuits offer higher data conversion rates whilemaintaining a comparable power consumption level. It is also highly suit-able for the SoC integration using the standard digital CMOS process. How-ever, the comparator design is based on the internal voltage reference deter-mined by the transistor sizes. Such internal voltage reference varies due to theCMOS process parameter variation during the manufacturing. Such variationcreates a margin of the linearity variation of the A/D converter.

The optimal design method of the TIQ comparator presented in this papersignificantly improves the linearity of the A/D converter against the CMOSprocess variation. In particular, the DNL dependence on the CMOS processvariation can be almost eliminated. This design method has been incorporatedinto a software package that generates the2n � 1 optimized TIQ comparatorlayouts. The simulation results show the effectiveness of the linearity im-provement of the flash TIQ based A/D converter, and the prototype chip hasbeen fabricated, with initial testing result confirming the DNL reduction.

References

1. T. Broekaert, B. Brar, J. van der Wagt, A. Seabaugh, T. Moise, F. Morris, E. B. III, andG. Frazier, “A Monolithic 4 Bit 2 GSps Resonant Tunneling Analog-to- Digital Converter,”Gallium Arsenide Integrated Circuit Symposium, pp. 187–190, 1997.

2. H. Chen, B. Song, and K. Bacrania, “A 14-b 20-MSamples/s CMOS Pipelened ADC,”IEEE Journal of Solid-State Circuits, 36(6):997–1001, June 2001.

3. M. Choi, and A. A. Abidi, “A 6b 1.3GSample/s A/D Converter in 0.35�mCMOS,” IEEEInternational Solid-State Circuits Conference, pp. 126–127, 2001.

4. D. Dalton, G. J. Spalding, H. Reyhani, T. Murphy, K. Deevy, M. Walsh, and P. Griffin,“A 200-MSPS 6-Bit Flash ADC in 0.6-�m CMOS,” IEEE Transactions on Circuit andSystems, 45(11):1433–1444, November 1998.

5. G. Geelen, “A 6b 1.1GSample/s CMOS A/D converter,”IEEE International Solid-StateCircuits Conference, pp. 128–129, 2001.

6. S. Mortezapour, and E.K.F. Lee, “A 1-V, 8-Bit Successive Approximation ADC inStandard CMOS Process,”IEEE Journal of Solid-State Circuits, 35(4):642–646, April2002.

7. Y. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, “A 10b 100MSamples/s CMOSPipelined ADC with 1.8V Power Supply,” IEEE International Solid-State CircuitsConference, pp. 130–131, 2001.

8. J. Singh, “High Speed Multi-Channel Data Acquisition Chip,”IEEE InternationalConference on Electronics, Circuits and Systems, volume 1, pp. 401–404, 1998.

9. Y. Tamba and K. Yamakido, “A CMOS 6b 500MSample/s ADC for a Hard Disk DriveRead Channel,”IEEE International Solid-State Circuits Conference, pp. 324–325, 1999.

jaicsp3.tex; 16/11/2002; 0:45; p.13

14

10. Y.-T. Wang and B. Razavi, “An 8-Bit 150-MHz CMOS A/D Converter,”IEEE Journalof Solid-State Circuits, 35(3):308–317, March 2000.

11. J. Yoo, K. Choi, and A. Tangel, “A 1-GSPS CMOS Flash A/D Converter for System-on-Chip Applications,”IEEE Computer Society Workshop on VLSI, pp. 135–139, 2001.

12. J. Yoo, D. Lee, K. Choi, and A. Tangel, “Future-Ready Ultrafast 8Bit CMOS ADC forSystem-on-Chip Applications,”IEEE International ASIC/SOC Conference, pp. 455–459,2001.

13. J. Yoo, D. Lee, K. Choi, and J. Kim, “A Power and Resolution Adaptive Flash Analog-to-Digital Converter,”ACM/IEEE International Symposium on Low Power Electronics andDesign, pp. 233–236, 2002.

14. K. Yoon, S. Park, and W. Kim, “A 6b 500MSample/s CMOS Flash ADC with a Back-ground Interpolated Auto-Zeroing Technique,”IEEE International Solid-State CircuitsConference, pp. 326–327, 1999.

15. B. Yu, and W. Black. Jr, “A 900MS/s 6b Interleaved CMOS Flash ADC,”IEEE CustomIntegrated Circuits Conference, pp. 149–152, 2001.

jaicsp3.tex; 16/11/2002; 0:45; p.14

15

Authors’ Vitae

Jincheol Yoo

Jincheol Yoo received a BS degree in Computer Sciencefrom the Korea Military Academy (KMA), Seoul Korea in 1989 and a MSdegree in Statistics from the Iowa State University in 1993. He joined theDepartment of Mathematics at the KMA as an instructor. In 1995, he wastransferred to the Department of Computer Science at the KMA as a full-time instructor. He enrolled in the Ph.D. program in Computer Science andEngineering at the Pennsylvania State University in 1998. He is expecting hisPh.D. degree in May, 2003. His research interest include high speed and lowpower ADC design and design automation in the mixed-signal circuits. He isa student member of IEEE, IEEE CAS, and IEEE SSC.

Kyusun Choi

Kyusun Choi received his BS from Lehigh University in1985, MS and Ph.D. from the Pennsylvania State University in 1987 and in1993, respectively. He joined Penn State as an assistant professor of Com-puter Science and Engineering effective fall 1993. He received an Outstand-ing Teaching award from the Penn State Engineering Society. His currentresearch and teaching interests include mixed-signal VLSI circuit design, RFASICs, and DSP architecture for RF signal. He is the inventor of the fourPSU invention disclosures. He is a member of IEEE.

jaicsp3.tex; 16/11/2002; 0:45; p.15

16

Daegyu Lee

Daegyu Lee received the BS degree in electronics engi-neering from the Hanyang University, South Korea, and the MS degree inComputer Science and Engineering from the Pennsylvania State University,University Park, PA. He first joined Hyundai Korea Engine Fuel InjectionCompany in 1997 working on Engine Management System as a firmwareprogrammer. He joined Samsung Advanced Institute of Technology, SouthKorea in 2002, where he has been working on DVD analog front-end circuitdesign.

jaicsp3.tex; 16/11/2002; 0:45; p.16