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COMP541COMP541

Flip-Flop TimingFlip-Flop Timing

Montek SinghMontek Singh

Feb 23, 2010Feb 23, 2010

TopicsTopics Lab:Lab:

FeedbackFeedback VGA Display Timing GeneratorVGA Display Timing Generator

Timing of flip-flopsTiming of flip-flops Timing analysis of sequential systemsTiming analysis of sequential systems

Clock skewClock skew

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Input Timing ConstraintsInput Timing Constraints Setup time: Setup time: ttsetupsetup = time = time

before the clock edge before the clock edge that data must be stable that data must be stable (i.e. not changing)(i.e. not changing)

Hold time: Hold time: ttholdhold = time = time after the clock edge that after the clock edge that data must be stabledata must be stable

Aperture time: Aperture time: ttaa = time = time around clock edge that around clock edge that data must be stable (data must be stable (ttaa = = ttsetupsetup + t + tholdhold))

CLK

tsetup

D

thold

ta

Output Timing ConstraintsOutput Timing Constraints Propagation delay: Propagation delay: ttpcqpcq = time after clock edge = time after clock edge

that the output that the output QQ is guaranteed to be stable is guaranteed to be stable (i.e., to stop changing)(i.e., to stop changing)

Contamination delay: Contamination delay: ttccqccq = time after clock = time after clock edge that edge that QQ might be unstable (i.e., start might be unstable (i.e., start changing)changing)

CLK

tccq

tpcq

Q

Dynamic DisciplineDynamic Discipline The input to a synchronous sequential circuit The input to a synchronous sequential circuit

must be stable during the aperture (setup and must be stable during the aperture (setup and hold) time around the clock edge.hold) time around the clock edge.

Specifically, the input must be stableSpecifically, the input must be stable at least at least ttsetupsetup before the clock edge before the clock edge

at least until at least until ttholdhold after the clock edge after the clock edge

Implications on DesignImplications on Design The delay between The delay between

registers (clock period registers (clock period and rate) has a and rate) has a minimum and minimum and maximum delay, maximum delay, dependent on the dependent on the delays of the circuit delays of the circuit elementselements Both CL and FFsBoth CL and FFs

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

Setup Time ConstraintSetup Time Constraint Setup time constraint depends on max delay Setup time constraint depends on max delay

from R1 through the combinational logic.from R1 through the combinational logic. And input to R2 must be stable at least tsetup And input to R2 must be stable at least tsetup

before the clock edge.before the clock edge. What’s min clock period?What’s min clock period?

CLK

Q1

D2

Tc

tpcq tpd tsetup

CL

CLKCLK

Q1 D2

R1 R2

What’s Tc?

Tc ≥ tpcq + tpd + tsetup

tpd ≤ Tc – (tpcq + tsetup)

So, clock period constrained by:• Delay in CL• Delay in previous regs• Setup requirement of R2

Hold Time ConstraintHold Time Constraint Hold time constraint depends on the minimum Hold time constraint depends on the minimum

delay from register R1 through the delay from register R1 through the combinational logic.combinational logic.

The input to R2 must be stable for at least The input to R2 must be stable for at least thold after the clock edge.thold after the clock edge.

CLK

Q1

D2

tccq tcd

thold

CL

CLKCLK

Q1 D2

R1 R2thold < tccq + tcd

tcd > thold - tccq

Timing AnalysisTiming Analysis

CLK CLK

A

B

C

D

X'

Y'

X

Y

per

gate

Timing Characteristics

tccq = 30 ps (FF contamination)

tpcq = 50 ps (FF propagation)

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd =

tcd =

Setup time constraint:

Tc ≥

fc =

Hold time constraint:

tccq + tpd > thold ?

tpd = 3 x 35 ps = 105 ps

tcd = 25 ps

Setup time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

Hold time constraint:

tccq + tpd > thold ?

(30 + 25) ps > 70 ps ? No!

Fixing Hold Time ViolationFixing Hold Time Violation

per

gate

CLK CLK

A

B

C

D

X'

Y'

X

Y

Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd = 3 x 35 ps = 105 ps

tcd = 2 x 25 ps = 50 ps

Setup time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

Hold time constraint:

tccq + tpd > thold ?

(30 + 50) ps > 70 ps ? Yes!

Add buffers to the short paths:

Hold TimeHold Time Often FFs are designed for a hold time of zeroOften FFs are designed for a hold time of zero

To avoid these tricky problemsTo avoid these tricky problems

Clock SkewClock Skew Clock doesn’t arrive at all registers at the Clock doesn’t arrive at all registers at the

same timesame time Skew is the difference between two clock Skew is the difference between two clock

edgesedges Examine the worst case:Examine the worst case:

guarantee that discipline is not violated for guarantee that discipline is not violated for anyany registerregister

many registers in a system!many registers in a system!

t skew

CLK1

CLK2

CL

CLK2CLK1

R1 R2

Q1 D2

CLKdelay

CLK

Setup Time Constraint with Clock Setup Time Constraint with Clock SkewSkew

Worst case: CLK2 is earlier than CLK1Worst case: CLK2 is earlier than CLK1

CLK1

Q1

D2

Tc

tpcq tpd tsetuptskew

CL

CLK2CLK1

R1 R2

Q1 D2

CLK2

Tc ≥ tpcq + tpd + tsetup + tskew

tpd ≤ Tc – (tpcq + tsetup + tskew)

Similar Issue w/ Hold TimeSimilar Issue w/ Hold Time We won’t go over exampleWe won’t go over example

Have a look in bookHave a look in book

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Next TimeNext Time Read Section 3.5Read Section 3.5

MetastabilityMetastability Then we’ll move on to memoriesThen we’ll move on to memories

Section 5.5Section 5.5

Homework 3 dueHomework 3 due

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