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ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions. Commissioning the ATLAS Silicon Microstrip Tracker. Jose E. Garcia Universit é de Gen è ve for the Atlas SCT collaboration. IPRD08 - Siena. 2. ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions. - PowerPoint PPT Presentation
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1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Commissioning the ATLAS Silicon Microstrip Tracker
IPRD08 - Siena
Jose E. GarciaUniversité de Genèvefor the Atlas SCT collaboration
ATLAS Detector2
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Jose E. Garcia IPRD08 - Siena
ATLAS is being assembled toexploit the 14TeV pp collisions at the LHC
The Inner Detector forms the heart of the ATLAS experiment. The closest to the interaction point.
• Pixel Detector• Semiconductor Tracker (SCT)• Transition Radiation Detector (TRT)
Semi-Conductor Tracker3
Jose E. Garcia IPRD08 - Siena
• 61 m2 of silicon with 6.2 million readout channels• 4088 silicon modules arranged to form 4 Barrels and 9+9 Disks• Barrels : 2112 modules with acceptance || < 1.1 to 1.4• Endcaps : 1976 modules with acceptance 1.1 to 1.4 <|| < 2.5
• Space point resolution r ~17m / Z ~ 580 m (23 m strip resolution)
• Radiation hard: tested to 2x1014 1-MeV neutron equivalent /cm2 • Material: 3% X0 per layer ( = 0)
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Silicon Modules4
Jose E. Garcia IPRD08 - Siena
• Back-to-back sensors, glued to highly thermallyconductive substrates for mechanical stability and sensor cooling• 40mrad stereo angle between sensors• 1536 channels (768 on each side)• Optical communication• 5.6W/module (adding ~1W per sensor after 10 years LHC)• Cooled to -25oC to limit sensor radiation damage and -8oC ambient temperature.• up to 500V sensor bias
• 2112 Barrel modules• one module type
• 1976 EndCap modules• 4 module types
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Front End Electronics5
Jose E. Garcia IPRD08 - Siena
• 128 channel ASIC with binary architecture• Radiation-hard DMILL technology• 12 chips per module (6 each side)• glued to hybrid (Cu/polyimide flex circuit)• 40MHz (25ns) clock• 20ns front end shaping time• Redundancy scheme (chips, link, TTC)
DAC
Binary Pipeline (132 deep)
Comparator
PreAmp+Shaper
Threshold Voltage
Edge-Detect circuit
Readout Buffer
Test-Input
t
t
v
“Shaped” input pulse to Comparator
“Logic” output of comparator
• 3 pipeline bins read out, centeredon L1A trigger
Data Compression
Circuit
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Assembly Sites6
Jose E. Garcia IPRD08 - Siena
• 4 Assembly Sites• Oxford - Barrel• Nikhef - EndCap A• Liverpool - EndCap C• SR1 at CERN
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Installation Timeline7
Jose E. Garcia IPRD08 - Siena
2006
Quarter 1
Quarter 2
Quarter 3
Quarter 4
2007
Quarter 1
Quarter 2
Quarter 3
Quarter 4
2008
Quarter 1
Quarter 2
Quarter 3
Quarter 4
Barrel in Pit
EndCaps in Pit
ID sealed
ID operational in Atlas
Cooling Issues• 3 ID compressors failed• 100 kg of C3F8 lost and 900 contaminated• Cooling plant cleaned up and broken parts replaced• Fortunately detector not affected• Measures have been taken to prevent this to happen again
•Test Module connectivity and performance comparing with surface data
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Pixels in Pit
Commissioning Tests8
Jose E. Garcia IPRD08 - Siena
• Electrical Connections• Check LV arrives at modules: VDD, VCC, IPIN, IVCSEL • HV current voltage scan• Check temperature readings
• Optical Connections• P-i-n current checks• Light from fiber data measured at Redaout Driver (ROD) • Check fiber connection and correct module mapping
• Calibration Tests• Digital and Analogue functionality tested• Gain curve, Noisy/Dead channel map• Noise occupancy Tests
• Cosmic Tests• Milestone 6 (M6) :
• Global commissioning run with ATLAS
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Combined SCT and TRT track.
Atlas Integration9
Jose E. Garcia IPRD08 - Siena
• Calibration and configuration changes are being made to improve performance. Some modules were removed from due to readout issues. They will be back in once they are properly adjusted. Approximate numbers:
– Barrel: 99.6% modules
– EndCaps (*): 97.8% modules
(*2 out of 72 cooling loops off, partially recoverable during shutdown)
• Around 97% configuration for stable readout in ATLAS
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
• Standalone calibration was performed up to the first week of September. From then SCT has been included in the Atlas data taking
– Full Barrel and Endcap ROD readout
– Athena and ROS Level Monitoring
– Data Quality Monitoring
• Since middle of August cooling is back and running stably for the detectors.
• SCT running fully powered since end August
Noise Occupancy10
Jose E. Garcia IPRD08 - Siena
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Barrel Noise Occupancy at 150 V• measured ~4.4 x 10-5
• Outer/middle NO of ~ 5 x10-5
• Inner type modules much lower due to short strip length• Values in agreement to measurements from production, integration and installation.
Broken TX fibre or dead PINClock and control from neighbouringmodule Broken TX fibre or dead PINClock and control from neighbouring
module
Current issue: TTC link11
Jose E. Garcia IPRD08 - Siena
Some SCT channels generate no pin current (TX). Suspect ESD damage.
RX Ch
TX Ch
ROD BOC
DATA
TTC
Currently affected around 2.5 % of the modules
o Currently we are using redundancy whenever possible (this is not possible where two adjacent modules have zero pin current).
o If a few channels in a specific TX plugin are lost, it will be needed to change them.o Plugins can be replaced at the USA15. Newly manufactured plugins are being tested.
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Broken TX fibre or dead PINClock and control from neighboringmodule
Timing In with ATLAS12
Jose E. Garcia IPRD08 - Siena
• Apply global trigger delay offset on top of the 4088 individual delays,and scan offset to look for increase in number of coincidental hits, increasing the number of space-points and tracks.• Reading 3 bunch crossings (3 x 25 ns clock cycles).
• Scans were done and SCT was timed in using cosmics before first beam and continued after
• LATER (with beam!): When roughly timed in, start fine delay (steps of 280ps) to tune relative bin occupancies and optimise hit efficiency. Fine scan delay scan with different offsets for each module
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
0 1 X
First Beam (10th Sept)13
Jose E. Garcia IPRD08 - Siena
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
SCT EndCaps at 20 V during the first
beam
Many tracks and space-points seen during the circulating
beam
Combined Tracks: SCT + Pixels14
Jose E. Garcia IPRD08 - Siena
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
Data taking is ongoing 24/7 with the rest of the sub-systems.
First tracks seen with hits in pixels and SCT combined
The residuals for the SCT barrel show a behaviour similar to the M6 results.
Alignment with Last Cosmics Data15
Jose E. Garcia IPRD08 - Siena
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
SCT
Level 1Barrel
EndCap
Level 2Barrel layers
EndCap disks
Level 3Barrel modules
EndCap modules
Hits on tracks for barrel layers
The residuals for the SCT barrel show a behavior similar to the M6 results.
Conclusions16
Jose E. Garcia IPRD08 - Siena
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions
• SCT running fully powered since beginning of September with 97% configuration for stable readout in ATLAS after the first round of readout adjustments.
• Integrated the full SCT into ATLAS combined partition
• Observed first beam and used beam splashes to get first timing (on endcaps)
• Currently ongoing cosmics runs for:– Timing studies– Alignment– DAQ, DCS and Monitoring tuning up– Improvement on module calibration
Backup Slides17
Jose E. Garcia IPRD08 - Siena
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions7. Backup
Timing In18
Jose E. Garcia IPRD08 - Siena
BOC coarse delayUp to 32 clock cycles
BOC fine delay up to 35ns in 280ps
steps
… x48
ROD
Trig
ROD Crate
FINE
FINE
FINE
FINE
Fibres to modules
Compensate for differentpropagation delays ofC&C from BOC to module(which varies from 380nsto 446ns)
• 4088 individual delaysfrom 0 to 66ns
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions7. Backup
Optical Communication19
Jose E. Garcia IPRD08 - Siena
1. ATLAS and ID2. SCT3. Commissioning4. Integration5. Latest Runs6. Conclusions7. Backup