     # Combinational Circuit Design - ee.nthu.edu.t .Combinational Circuit Design CHAPTER 5. VLSI Design

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• VLSI Design

5-

Chih-Cheng Hsieh

Combinational Circuit Design

CHAPTER 5

• VLSI Design

5-

Chih-Cheng Hsieh

2

1. Static CMOS

2. Ratioed Circuits

3. Cascode Voltage Switch Logic

4. Dynamic Circuits

5. Pass-Transistor Circuits

6. Circuit Pitfalls

Outline

• VLSI Design

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Chih-Cheng Hsieh

Static CMOS

Bubble Pushing

Compound Gates

Logical Effort Example

Input Ordering

Asymmetric Gates

Skewed Gates

Best P/N ratio

3

• VLSI Design

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Chih-Cheng Hsieh

Example 1 module mux(input s, d0, d1,

output y);

assign y = s ? d1 : d0;

endmodule

1) Sketch a design using AND, OR, and NOT gates.

4

D0S

D1S

Y

• VLSI Design

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Chih-Cheng Hsieh

Example 2

2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available.

5

Y

D0S

D1S

• VLSI Design

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Chih-Cheng Hsieh

Bubble Pushing

Convert to NAND / NOR + inverters

Push bubbles around to simplify logic

Remember DeMorgans Law

6

A B A B A B A B

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Chih-Cheng Hsieh

Bubble Pushing

Y = AB + CD

7

Y Y

Y Y

(a) (b)

(c) (d)

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

• VLSI Design

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Chih-Cheng Hsieh

Example 3

3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available.

8

Y

D0SD1S

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Chih-Cheng Hsieh

Compound Gates

Logical Effort of compound gates

9

ABCD

Y

ABC

Y

A

BC

C

A B

A

B

C

D

A

C

B

D

2

21

4

44

2

2 2

2

4

4 4

4

gA = 6/3

gB = 6/3

gC = 5/3

p = 7/3

gA = 6/3

gB = 6/3

gC = 6/3

p = 12/3

gD = 6/3

YA

A Y

gA = 3/3

p = 3/3

2

1YY

unit inverter AOI21 AOI22

A

C

DE

Y

B

Y

B C

A

D

E

A

B

C

D E

gA = 5/3

gB = 8/3

gC = 8/3

gD = 8/3

2

2 2

22

6

6

6 6

3

p = 16/3

gE = 8/3

Complex AOI

Y A B C Y A B C D Y A B C D E Y A

• VLSI Design

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Chih-Cheng Hsieh

Example 4

The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs.

10

Y

D0S

D1S

Y

D0SD1S

H = 160 / 16 = 10

B = 1

N = 2

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Chih-Cheng Hsieh

NAND Solution 11

Y

D0S

D1S

2 2 4

(4 / 3) (4 / 3) 16 / 9

160 / 9

4.2

12.4

N

P

G

F GBH

f F

D Nf P

Y

D0S

D1S

DeMorgans Law

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Chih-Cheng Hsieh

Compound Solution 12

4 1 5

(6 / 3) (1) 2

20

4.5

14

N

P

G

F GBH

f F

D Nf P

Y

D0SD1S

AOI22 INV +

• VLSI Design

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Chih-Cheng Hsieh

Example 5

Annotate your designs with transistor sizes that achieve this delay.

13

6

6 6

6

10

10Y

24

12

10

10

8

8

88

8

8

88

25

25

2525Y

16 16160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 36

YY

NAND solution Compound solution

• VLSI Design

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Chih-Cheng Hsieh

Input Order

Our parasitic delay model was too simple

Calculate parasitic delay for Y falling

If A arrives latest? 2

If B arrives latest? 2.33

14

6C

2C2

2

22

B

A

x

Y

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Chih-Cheng Hsieh

Inner & Outer Inputs

Outer input is closest to rail (B)

Inner input is closest to output (A)

If input arrival time is known

Connect latest input to inner terminal

15

2

2

22

B

A

Y

• VLSI Design

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Chih-Cheng Hsieh

VTC is Data-Dependent The threshold voltage of M2 is higher than M1 due to body effect ()

since VSB of M2 is not zero (when VB = 0) due to the presence of Cint

VTn1 = VTn0

A

B

F= A B

A B

M1

M2

M3 M4

Cint

VGS1 = VB

VGS2 = VA VDS1

0.5/0.25 NMOS 0.75 /0.25 PMOS

D

D

S

S

weaker PUN

VTn2 = VTn0 + ((|2F| + Vint) - |2F|)

16

• VLSI Design

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Chih-Cheng Hsieh

Symmetric Gates

Inputs can be made perfectly symmetric

17

A

B

Y2

1

1

2

1

1

• VLSI Design

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Chih-Cheng Hsieh

Asymmetric Gates

Asymmetric gates favor one input over another

Ex: suppose input A of a NAND gate is most critical

Use smaller transistor on A (less capacitance)

Boost size of noncritical input

So total resistance is same

gA = 10/9

gB = 2

gtotal = gA + gB = 28/9

Asymmetric gate approaches g = 1 on critical input

But total logical effort goes up

18

A

resetY

4/3

2

reset

A

Y

A

resetY

4

4/3

22

reset

A

Y

• VLSI Design

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Chih-Cheng Hsieh

Skewed Gates

Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical

Downsize noncritical nMOS transistor

Calculate logical effort by comparing to unskewed inverter with same effective R on that edge. gu = 2.5 / 3 = 5/6 gd = 2.5 / 1.5 = 5/3

19

1/2

2A Y

1

2A Y

1/2

1A Y

HI-skew

inverter

unskewed inverter

(equal rise resistance)

unskewed inverter

(equal fall resistance)

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Chih-Cheng Hsieh

HI- and LO-Skew

Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.

Skewed gates reduce size of noncritical transistors

HI-skew gates favor rising output (small nMOS)

LO-skew gates favor falling output (small pMOS)

Logical effort is smaller for favored direction

But larger for the other direction

20

• VLSI Design

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Chih-Cheng Hsieh

Catalog of Skewed Gates 21

1/2

2A Y

Inverter

1

1

22

B

AY

B

A

NAND2 NOR2

1/21/2

4

4

HI-skew

LO-skew1

1A Y

2

2

11

B

AY

B

A

11

2

2

gu = 5/6

gd = 5/3

gavg = 5/4

gu = 4/3

gd = 2/3

gavg = 1

gu = 1

gd = 2

gavg = 3/2

gu = 2

gd = 1

gavg = 3/2

gu = 3/2

gd = 3

gavg = 9/4

gu = 2

gd = 1

gavg = 3/2

Y

Y

1

2A Y

2

2

22

B

AY

B

A

11

4

4

unskewedgu = 1

gd = 1

gavg = 1

gu = 4/3

gd = 4/3

gavg = 4/3

gu = 5/3

gd = 5/3

gavg = 5/3

Y

1/2

2A Y

Inverter

1

1

22

B

AY

B

A

NAND2 NOR2

1/21/2

4

4

HI-skew

LO-skew1

1A Y

2

2

11

B

AY

B

A

11

2

2

gu = 5/6

gd = 5/3

gavg = 5/4

gu = 4/3

gd = 2/3

gavg = 1

gu =

gd =

gavg =

gu =

gd =

gavg =

gu =

gd =

gavg =

gu =

gd =

gavg =

Y

Y

1

2A Y

2

2

22

B

AY

B

A

11

4

4

unskewedgu = 1

gd = 1

gavg = 1

gu = 4/3

gd = 4/3

gavg = 4/3

gu = 5/3

gd = 5/3

gavg = 5/3

Y

1/2

2A Y

Inverter

B

AY

B

A

NAND2 NOR2

HI-skew

LO-skew1

1A Y

B

AY

B

A

gu = 5/6

gd = 5/3

gavg = 5/4

gu = 4/3

gd = 2/3

gavg = 1

gu =

gd =

gavg =

gu =

gd =

gavg =

gu =

gd =

gavg =

gu =

gd =

gavg =

Y

Y

1

2A Y

2

2

22

B

AY

B

A

11

4

4

unskewedgu = 1

gd = 1

gavg = 1

gu = 4/3

gd = 4/3

gavg = 4/3

gu = 5/3

gd = 5/3

gavg = 5/3

Y

• VLSI Design

5-

Chih-Cheng Hsieh

Asymmetr

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