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COMBINATION LOGIC CIRCUIT LAB JOURNAL
Tittle : Combination Logic Circuit Lab Journal
Subject : Digital Electronics (EEE 1313)
Written by : Raefi Azrani Bin Ropee Adman
Student Id : 1006q78842
Advice by : Mr. Lee
Intake : Sem 1/SEP intake 2011
1
COMBINATION LOGIC CIRCUIT LAB JOURNAL
TABLE CONTENT
No. CONTENTS PAGE
1 Executive Summary 3
2 Introduction: 4
3 Methodology 5
4 Procedure 6-15
5 Learning Outcome 15
6 Conclusion 15
2
COMBINATION LOGIC CIRCUIT LAB JOURNAL
Executive Summary
This journal is mainly aiming to discuss about the designing a combinational logic circuit for the
Output Logic Block that get input of 3-Bit Asynchronous Up counter which counts in specific
order. The sequence is 3>0>1>6>7>4>5>2. It is a continues repeated sequence which mean it
will repeated again after the last number. Generally, the combination of logic circuit using a D
flip-flop and NAND gates
The method that is use are:
i. Expressing the sequence in binary form
ii. Expressing sequence in Boolean equation
iii. Use Karnaugh Map (K map) to simplified
iv. Use NAND gates as a universal gate
3
COMBINATION LOGIC CIRCUIT LAB JOURNAL
Introduction:
The objectives of the report are:
1. To design, build and test a 3-bit Asynchronous Counter that counts in a specific
order by using the D flip-flops and NAND gates.
2. To construct and troubleshoot a 3-bit Asynchronous Up Counter.
This journal is about designing the combination of digital circuit that count in specific
sequence. Each individual has been assigned with different order. For this report the order is
3>0>1>6>7>4>5>2.
List of tool and parts
Hardware Tools:
1. DC Power Supply
2. Wire Stripper/Cutter
3. Component bender (pliers)
No
.
Part Quantity
1 Light Emitting Diodes, LEDs 7
2 Resistors:10kΩ,1/4 W 2
3 Resistors:560Ω,1/4 W 7
4 IC:74HC00,4 units of 2-input NAND gate 1
5 IC:74HC10,3 units of 3-input NAND gate 1
6 IC:74HC74,2 units of D Flip-Flop gate 2
4
COMBINATION LOGIC CIRCUIT LAB JOURNAL
Methodology
The method of designing the circuit is as follow:
1. Generate the truth table for Out-2,Out-1 and Out-0 by building a clock generator
2. Derive the Boolean equation for Out-2,Out-1 and Out-0
3. Plot Karnough’s map to simplified the Boolean equation
4. Draw the schematic diagram of logic implementation of the Boolean equation for Out-
2,Out-1 and Out-0
5. Convert the logic implementation of Out-2,Out-1 and Out-0 into all NAND gate
Flow diagram of the entire circuit
Procedure
5
Bit-2
Bit-0
Bit-1Clock Generator
Output Logic Block
3-bit Asynchronous up Counter
OUT-0
OUT-2
OUT-1
CLOCK
DIAGRAM 1: Block Diagram of the `Out-of-Sequence’ Asynchronous Counter
COMBINATION LOGIC CIRCUIT LAB JOURNAL
U1A
74HC74N_6V
1D2 1Q 5
~1Q 6
~1CLR
1
1CLK3
~1PR
4U2B
74HC74N_6V
2D12 2Q 9
~2Q 8
~2CLR
13
2CLK11
~2PR
10 U1B
74HC74N_6V
2D12 2Q 9
~2Q 8
~2CLR
13
2CLK11
~2PR
10 U2A
74HC74N_6V
1D2 1Q 5
~1Q 6
~1CLR
1
1CLK3
~1PR
4
R110kΩ
V15 V
R210kΩ
J1Key = A
J2Key = A
V2
5 V
V3
5 V
V4
5 V
R3560 Ω
R4560 Ω
R5560 Ω
X1LED
X2LED
X3LED
Bit-0 BIt-1 Bit-2
X4LED
R6560 Ω
6
Diagram 2: Clock Generator and 3-Bit bit Asynchronous Up Counter
Procedure
COMBINATION LOGIC CIRCUIT LAB JOURNAL
1. Diagram 2 shows the design for the clock generator with 3-bit Asynchronous Up
Counter.
2. All the integrated circuits are connected to the 5V power supply.
3. Attach the LED with a 560Ω resistor to the Q and Q output of the D-flip flop once the
clock generator is wired up.
4. The LEDs should alternately light up every time the wire from the ground is touch one of
the 10kΩ resistor.
5. The LEDs determined whether the circuit is functional or not by lightning up accordingly
to the binary sequence from 000 to 111 and it will repeat itself after the last number of the
order
6. Wire up the clock generator output (CLK) to the D-flip flop of bit-0.
7. Next, the counter is connected as shown in the diagram using the LEDs to test the output.
8. The LEDs sequence will light in binary. In the decimal sequence is equal to
0>1>2>3>4>5>6>7
Circuit uses 3 D-flip flop from 2 74HC74
Note: In order the LED to light up and off respectively, you have to touch the wire
respectively between the two resistors.
7
COMBINATION LOGIC CIRCUIT LAB JOURNAL
9) Sequence assigned; (Group 9) is changed to binary and compared to the 3-bit Asynchronous
Up Counter. As shown in table below,
Output Logic Block,Group 9 sequence 3,0,1,6,7,4,5,2
Bit-2 Bit-1 Bit-0 Sequence
in decimal
Decimal number in Binary
OUTPUT-2 OUTPUT-1 OUTPUT-0
0 0 0 3 0 1 1
0 0 1 0 0 0 0
0 1 0 1 0 0 1
0 1 1 6 1 1 0
1 0 0 7 1 1 1
1 0 1 4 1 0 0
1 1 0 5 1 0 1
1 1 1 2 0 1 0
Logic Table
10) Use K arnaugh map for simplification the logic gates:
OUTPUT-2 (OUT-2)
00 01 11 10
0 0 0 1 1
1 0 1 0 1
Output Equation: (Bit-2)(Bit-1)(Bit-0) + (Bit-2)(Bit-0) + (Bit-2)(Bit-1)
8
Bit-0
Bit-2 ,Bit-1
COMBINATION LOGIC CIRCUIT LAB JOURNAL
OUTPUT -1 (OUT-1)
00 01 11 10
0 1 0 0 1
1 0 1 1 0
Output Equation: (Bit-1)(Bit-0) + (Bit-1)(Bit-0)
OUTPUT-0 (OUT-0)
00 01 11 10
0 1 1 1 1
1 0 0 0 0
Output Equation :( Bit-0)
Diagram representing the outputs from Karnaugh Map according to it gates
9
Bit-0
Bit-2 ,Bit-1
Bit-0
Bit-2 ,Bit-1
COMBINATION LOGIC CIRCUIT LAB JOURNAL
U1
AND2
U3
AND2
U4
OR3
U5
NOT
U6
NOT
U7
NOT
Bit-0
Bit-1
Bit-2
U2
AND3
OUTPUT
Output-1
Bit-1
Bit-0
U1
NOT
U2
NOT
U3
AND2
U4
AND2
U5
OR2
OUTPUT
10
Output -2
COMBINATION LOGIC CIRCUIT LAB JOURNAL
Output -0
U1
NOT
Bit-0Output
11
Legend
Symbol Explanation
U1
OR2
OR-Gate
U2
AND2
AND-Gate
U3
OR2
Inveter
COMBINATION LOGIC CIRCUIT LAB JOURNAL
To simplify all gates to NAND gates
Aim: To reduce the number of gates used
1. The universal NAND gate as an OR gate
U1
NAND2
U2
NAND2
U3
NAND2
2. The Universal NAND gate as AND gate
U4
NAND2
U5
NAND2
12
A + B
A
B
AB= A + B
A
B
A
B
ABAB
B
A
COMBINATION LOGIC CIRCUIT LAB JOURNAL
11) Knowing the universal properties of NAND gates. Circuit for output-2, output-1 and output-
0 can be simplified. The diagram is shown as follow:
U1
NAND3
U2
NAND2
U3
NAND2
U4
NAND3
U1
NAND2
U2
NAND2
U3
NAND2
Output-0
U1
NOT
Bit-0Output
13
Output-2
Output-1
Output
Output
COMBINATION LOGIC CIRCUIT LAB JOURNAL
Final Circuit
U1A
74HC74N_6V
1D2 1Q 5
~1Q 6
~1CLR
1
1CLK3
~1PR
4
U2B
74HC74N_6V
2D12 2Q 9
~2Q 8
~2CLR
13
2CLK11
~2PR
10 U2A
74HC74N_6V
1D2 1Q 5
~1Q 6
~1CLR
1
1CLK3
~1PR
4 U1B
74HC74N_6V
2D12 2Q 9
~2Q 8
~2CLR
13
2CLK11
~2PR
10
R110kΩ
V15 V
R210kΩ
J1Key = A
J2Key = A
V2
5 V
V3
5 V
V4
5 V
R3560 Ω
R4560 Ω
R5560 Ω
X1LED X2
LED
X3LED
Bit-0 BIt-1 Bit-2
X4LED
R6560 Ω
U3NAND3
U4NAND2U5
NAND2
U6NAND3
U7NAND2
U8NAND2
U9NAND2
X5LED
R7560 Ω
X6LED
R8560 Ω
In Diagram-3, this is the final circuit of the 3-Bit Asynchronous counter that counts according to
the sequence of 3>0>1>6>7>4>5>2 in binary form.
11) Finally, the counter is connected to output-2, output-1 and output-0 which are connected to
the LEDs light in order to determine it is a working circuit.
14
Diagram-3 - The complete circuit design
COMBINATION LOGIC CIRCUIT LAB JOURNAL
Actual Circuit
Learning Experience
1) Make sure that every component polarities are connected correctly.
2) The 5V power supply and the ground are connected accordingly in order to prevent
the circuit from short circuit
Conclusion
The final circuit design as shown in the diagram-3 is an Asynchronous Counter which
counts according to a specific sequence repeatedly, which is 3>0>1>6>7>4>5>2 in binary form.
15
COMBINATION LOGIC CIRCUIT LAB JOURNAL
Appendix
16
COMBINATION LOGIC CIRCUIT LAB JOURNAL
74HC/HCT10
17