Combinaonal Logic Chapter 4 Topics

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Combina-onalLogicChapter4

EECE256Dr.SidneyFels

StevenOldridge

Topics

•  Combina-onalcircuits•  Combina-onalanalysis

•  Designprocedure– simplecombinedtomakecomplex– adders,subtractors,converters– decoders,mul-plexers•  comb.designwithdecodersandmuxes

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Combina-onCircuit

•  Outputdependsonlyonpresentvalueofinput

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NOTE:NoMemoryorfeedbackpaths

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Combina-onCircuit

•  Whathappensifweaddmemory?

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Combina-onCircuit

•  Whathappensifweaddmemory?

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MemoryElements

Calleda:Sequen&alCircuit‐outputfunc-onofinputandmemory‐changesover-me

Combina-onCircuit

•  We’llfocusoncombina-onaldesignfirst– usefulfordesigninghowmemorywillchangewhenmakingsequen-alcircuits

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Combina-onalAnalysis

•  Some-mesneedto:–  confirmcircuitdoeswhatitissupposedto–  reverseengineercircuit

•  Steps(startatinputandworktooutputs):1.  labelalloutputsthatarefn’ofinputsandderiveBoolean

expression2.  labelalloutputsthatfn’ofinputsandlabelsdoneinstep

1andderiveBooleanexpressions3.  repeatun-lalloutputshaveBooleanfn’4.  usesubs-tu-ontogetBooleanfn’basedonlyoninputs

•  fillintruthtable

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F2=AB+AC+BCT2=ABCT1=A+B+C


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T3=T1F2’F1=T2+T3

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F1=ABC+T1F2’;con-nuesubs-tu-ngF1=A’BC’+A’B’C+AB’C’+ABC

Combina-onalDesign

1.  Determinethenumberofinputsandoutputs2.  Assignsymbols

3.  Derivethetruthtable4.  Obtainsimplifiedfunc-onsforeachoutput

5.  Drawthelogicdiagram

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Adders

•  mostfundamentalunitincomputer•  addtwonumbers

•  let’sstartwithbinary…

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½AdderDesign

•  Step1–#ofinputsandoutputs–  let’sstartwith½adderfirst•  i.e.let’snotworryaboutcarryinjustyet

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0 0 1 1

+ 0 1 0 1

sum 0 1 1 0

carryout 0 0 0 1

½AdderDesign

•  Step2–Assignsymbolnames

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0 0 1 1

+ 0 1 0 1

sum 0 1 1 0

carryout 0 0 0 1

ABSC

½AdderDesign

•  Step3–DeriveTruthTable

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0 0 1 1

+ 0 1 0 1

sum 0 1 1 0

carryout 0 0 0 1

ABSC

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

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½AdderDesign

•  Step4–Derivesimplifiedform– usek‐maps,BooleanAlgrebra,etc.

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0 0 1 1

+ 0 1 0 1

sum 0 1 1 0

carryout 0 0 0 1

ABSC

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

S=A+BC=AB

½AdderDesign

•  Step5–Drawcircuitdiagram

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0 0 1 1

+ 0 1 0 1

sum 0 1 1 0

carryout 0 0 0 1

ABSC

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

S=A+BC=AB

AB

FullAdder

•  Weneedtoworryaboutpossiblecarry‐inthough

•  Sameprocedure–  input:x,y,Cin– output:SandCout– findTT

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x y Cin S Cout

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

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FullAdder

•  Weneedtoworryaboutpossiblecarry‐inthough

•  Sameprocedure–  input:x,y,Cin– output:SandCout– findTT

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x y Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

FullAdder

•  DeriveBooleanexpressions

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x y Cin

S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

S=x’y’Cin+x’yCin’+xy’Cin’+xyCin

Cout=xy+xCin+yCin

yCin yCin

Cin CinS Cout

FullAdder

•  DeriveBooleanexpressions

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x y Cin

S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

S=x’y’Cin+x’yCin’+xy’Cin’+xyCin=(x+y)+Cin

Cout=xy+xCin+yCin=(x+y)Cin+xy

yCin yCin

Cin CinS Cout

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FullAdder

•  xxx

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½adder

½adder

xy

Cin

S

C

S

C

SCout

FA

Cascadethemfor4‐bitAdder

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Cascadethemforaparallel4‐bitAdder

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Howbigisthetruthtable?

What’stheproblemwiththiscircuit?

ripplecarryadder

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Canwefixthis?

•  weneedtocomputecarrybitsinparallelratherthancascade

•  Then,usesome½adderswithextracircuitstofixthesumdependinguponthecomputedcarries

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n‐bitCarrylook‐aheadAdder

•  Recallthatforthedesignoftheparalleladdertowork,thesignalmustpropagatethroughthegatesbeforethecorrectoutputsumisavailable.

•  Totalpropaga&on&me=propaga&ondelayofatypicalgatexthenumberofgates

•  Let’slookatS3.–  InputsA3andB3areavailableimmediately.

–  However,C3isavailableonlyagerC2isavailable.–  C2hastowaitforC1,etc.

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•  ThenumberofgatelevelsforthecarrytopropagateisfoundfromtheFAcircuit

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propaga-ondelay

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•  let’slookateachstagetoseehowweknowwhatthecarryis

•  Pi=Ai+Bi(carryprop)•  Gi=AiBi(carrygenerate)

•  Si=Pi+Ci•  Ci+1=Gi+PiCi

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•  let’slookateachstagetoseehowweknowwhatthecarryis

•  Pi=Ai+Bi(carryprop)•  Gi=AiBi(carrygenerate)

•  Si=Pi+Ci•  Ci+1=Gi+PiCi

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Now,calculateeachstage’sCarryintermsofCin(i.e.C0)andPsorGs.


•  C0=Cin•  C1=G0+P0C0•  C2=

•  C3=

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•  C0=Cin•  C1=G0+P0C0•  C2=G1+P1C1=G1+P1(G0+P0C0)

=G1+P1G0+P1P0C0•  C3=

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•  C0=Cin•  C1=G0+P0C0•  C2=G1+P1C1=G1+P1(G0+P0C0)

=G1+P1G0+P1P0C0•  C3=G2+P2C2=G2+P2(G1+P1G0+P1P0C0)

=G2+P2G1+P1P2G0+P2P1P0C0

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So,allcarriesarenowcomputedinP2,GsandC0

Carrylook‐aheadcircuit

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4bitCarrylook‐aheadAdder

•  Pi=Ai+Bi•  Gi=AiBi

•  Si=Pi+Ci

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Whatispropaga-ondelay?

BinarySubtractor

•  Howtomakeabinarysubtractor?

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BinarySubtractor

•  Howtomakeabinarysubtractor?–  remember:2’scomplementconvertssubtrac-onintoaddi-on

– so,whenwewanttosubtract,•  maketheinputa2’scomplementnumber•  andadd

– checkforoverflow– 2’scomplement?

–  invertthebits+1

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4‐bitBinarysubtractor

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FA FA FA FA

B3 A3 B2 A2 B1 A1 B0 A0

1

D3 D2 D1 D0

Cout

A‐B

Whataboutoverflow?• ifunsigned–ifB>A;lookatCout• ifsigned–ifA+veandB–veorA–veandB+ve

‐lookatCoutandsignbit(C3)–shouldbesame

Thisisreallyaborrownow

C3 C2 C1

overflow

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0 0 1 1

‐ 1 0 1 1

3

11

‐8

unsigned

case1:A,Bunsigned:B>Aandresult<‐7

0 0 1 1

+ 0 1 0 1

1 1 0 0 0

3

2’scompof11

‐8

unsigned

overflow

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1 0 1 0

‐ 0 1 1 0

‐6

‐(+6)

‐12–but4bitsonly‐7to+7

signed

1 0 1 0

+ 1 0 1 0

‐6

+(2’Scomplementof+6)

case2‐signed:ais–ve,bis+ve;result<‐7,i.e.‐6–(+6)

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overflow

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0 1 1 0

‐ 1 0 1 0

+6

‐(‐6)

+12–but4bitsonly‐7to+7

signed

0 1 1 0

+ 0 1 1 0

+6

+(2’Scomplementof‐6)

case3‐signed:ais+ve,bis‐ve;result>+7,i.e.6–(‐6)

4‐bitBinaryadder/subtractor

•  Wecanputthistogethertomakeamorefunc-onalelement– M=modeforadd(0)orsubtract(1)

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4‐bitBinaryadder/subtractor

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DesignofaBCDAdder

•  Addtwodecimalnumbers–  (0‐9)+(0‐9)+(1)=0‐19‐don’tforgetcarry

•  Howtobegin?–  truthtable– canweuseexis-ngcircuit•  binaryadder?

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DesignofaBCDAdder

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Ifwejustputdecimalnumbersin,italmostworks…

BCDadderTT

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BCDadderTT

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sameasbinaryrepn

’

needdecimalcarry

BCDadderTT

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sameasbinaryrepn

’

needdecimalcarry

Z8Z4

Z8Z2

K4

C=K+Z8Z4+Z8Z2

BCDadderTT

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ifC=1;needtoadd6totheBinarysum‐soweneedanotherbinaryadder

So,wecannowdrawcircuitaswehaveCandfinalSum

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BCDadderdesign

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BCDadderdesign

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Decoders

•  Abinarycodeofnbitscanrepresent2n

dis-nctcombina-ons(orunique“cases”).

•  Decoder:acombina-onalcircuitthatconvertsnbinarylinesinto2nuniqueoutputlines

•  Example:a3‐to‐8linedecoder–  3inputsaredecodedto8outputs–

represen-ngthe8minterms

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Minterms

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Decoders

•  Abinarycodeofnbitscanrepresent2n

dis-nctcombina-ons(orunique“cases”).

•  Decoder:acombina-onalcircuitthatconvertsnbinarylinesinto2nuniqueoutputlines

•  Example:a3‐to‐8linedecoder–  3inputsaredecodedto8outputs–

represen-ngthe8minterms

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Minterms

3x8Decoder

D0

D7

xyz

Decoderdesign

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Inputs Outputs

x y z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Decodertruthtable

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Inputs Outputs

x y z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

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DecoderwithNAND

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NANDDecoderwithenable

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Nowwecancombinethemtogetbiggerones.

CombiningDecoders

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BooleanFunc-onswithDecoders

•  sincewehaveallmintermsitiseasytocombinethemforourBooleanfunc-ons

•  Forexample:– S=Σ(1,2,4,7)– C=Σ(3,5,6,7)

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BooleanFunc-onwithDecoders

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Encoders

•  Inverseopera-onofadecoder–  Ithas2ninputsandgeneratesncodewords

•  Example:Designa8x3encoder

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8x3Encoders

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X=D4+D5+D6+D7Y=D2+D3+D6+D7Z=D1+D3+D5+D7

8x3Encoders

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X=D4+D5+D6+D7Y=D2+D3+D6+D7Z=D1+D3+D5+D7

What’stheproblemhere?

PriorityEncoder

•  Fortheotherinputsuseprioritytodetermineoutput–  i.e.D3takespriorityoverD2;D2overD1etc.

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PriorityEncoder

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PriorityEncoder

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No-ce,wecanusethedon’tcarestodesignthis.

1

PriorityEncoder

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Mul-plexers

•  Amul-plexerselectsoneofmanyinputsanddirectsittotheoutput.

•  Theselec-onmaybecontrolledby“selectlines”

•  Normally2ninputlines:nselectlines

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Transmissionline

ch1ch2

chn

Mul-plexers•  Example:2x1mul-plexer

•  Howtodesign?–  let’sdesign4x1MUX–  coderedirectsinput

•  useANDgatewithminterm•  likedecoderwithANDgate

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4x1MUX

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UsingMUXesforBooleanfunc-ons

•  Useamul-plexertoimplementthefollowingfunc-on:– F=x’y’z+x’yz’+xy’z+xyz

•  Idea:– no-cethatMUXisadecoder+ORgate

– usetheselectortodirectcorrectvaluetooutput

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•  Example– F(x,y,z)=Σ(1,2,6,7)

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•  Example– F(x,y,z)=Σ(1,2,6,7)

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UsingMUXforBooleanFn’

•  DesignaFull‐adder– S(x,y,z)=Σ(1,2,4,7);C(x,y,z)=Σ(1,2,4,7)

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x y z S C

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1



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x y z S C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

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x y z S C Sm Cm0 0 0 0 0 z 0

0 0 1 1 0 z 0

0 1 0 1 0 z’ z

0 1 1 0 1 z’ z

1 0 0 1 0 z’ z

1 0 1 0 1 z’ z

1 1 0 0 1 z 1

1 1 1 1 1 z 1

SCz

z’ z

z

0

z

z’

Summary

•  Combina-onalcircuits•  Combina-onalanalysis

•  Designprocedure– simplecombinedtomakecomplex– adders,subtractors,converters– decoders,mul-plexers•  comb.designwithdecodersandmuxes

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Documents

Combinaonal Logic Chapter 4 Topics