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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Topics
Combinational logic functions. Static complementary logic gate structures. Switch logic. Non-standard gate structures.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Combinational logic expressions
Combinational logic: function value is a combination of function arguments.
A logic gate implements a particular logic function.
Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Gate design
Why designing gates for logic functions is non-trivial:– may not have logic gates in the libray for all
logic expressions;– a logic expression may map into gates that
consume a lot of area, delay, or power.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Boolean algebra terminology
Function:f = a’b + ab’
a is a variable; a and a’ are literals. ab’ is a term. A function is irredundant if no literal can be
removed without changing its truth value.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Completeness
A set of functions f1, f2, ... is complete iff every Boolean function can be generated by a combination of the functions.
NAND is a complete set; NOR is a complete set; {AND, OR} is not complete.
Transmission gates are not complete. If your set of logic gates is not complete, you
can’t design arbitrary logic.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Static complementary gates
Complementary: have complementary pullup (p-type) and pulldown (n-type) networks.
Static: do not rely on stored charge. Simple, effective, reliable; hence
ubiquitous.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Static complementary gate structure
Pullup and pulldown networks:
pullupnetwork
pulldownnetwork
VDD
VSS
outinputs
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Inverter
a out
+
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
NAND gate
+
ba
out
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
NOR gate
+
b
a
out
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
AOI/OAI gates
AOI = and/or/invert; OAI = or/and/invert. Implement larger functions. Pullup and pulldown networks are compact:
smaller area, higher speed than NAND/NOR network equivalents.
AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
AOI/OAI gates
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Construction of an AOI Gate
out = [ab+c]’:
symbol circuit
and
or
invert
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Construction of another AOI Gate
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Pullup/pulldown network design
Pullup and pulldown networks are duals. To design one gate, first design one
network, then compute dual to get other network.
Example: design network which pulls down when output should be 0, then find dual to get pullup network.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Dual Network Construction
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Switch logic
Can implement Boolean formulas as networks of switches.
Can build switches from MOS transistors—transmission gates.
Transmission gates do not amplify but have smaller layouts.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Switch logic network
a
b
0
1
a b out
0 0 X
0 1 1
1 0 0
1 1 X
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Another switch logic network
a
b
r
s
a b out
0 0 X
0 1 r
1 0 s
1 1 X
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Switch-based mux
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Types of switches
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Behavior of n-type switch
n-type switch has source-drain voltage drop when conducting:– conducts logic 0 perfectly;– introduces threshold drop into logic 1.
VDD
VDD
VDD - Vt
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
n-type switch driving static logic
Switch underdrives static gate, but gate restores logic levels.
VDD
VDD
VDD - Vt
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
n-type switch driving switch logic
Voltage drop causes next stage to be turned on weakly.
VDD VDD - Vt
VDD
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Behavior of complementary switch
Complementary switch products full-supply voltages for both logic 0 and logic 1:– n-type transistor conducts logic 0;– p-type transistor conducts logic 1.
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Charge Sharing Problem
Values are stored at parasitic capacitances on wires:
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Charge Sharing Problem
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Charge Sharing Example
1
1
00 0
1 1
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Application of Transmission Gate
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR
Application of Transmission Gate
