COE 405 Synthesis of Combinational & Sequential Logic Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals

COE 405COE 405 Synthesis of Combinational & Synthesis of Combinational &

Sequential LogicSequential Logic

COE 405COE 405 Synthesis of Combinational & Synthesis of Combinational &

Sequential LogicSequential Logic

Dr. Aiman H. El-Maleh

Computer Engineering Department

King Fahd University of Petroleum & Minerals

Dr. Aiman H. El-Maleh

Computer Engineering Department

King Fahd University of Petroleum & Minerals

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OutlineOutlineOutlineOutline

Circuit Synthesis Multilevel Logic Synthesis Timing Issues in Multiple-Level Logic

Optimization Behavioral or High-Level Synthesis Synthesis of Combinational Logic Synthesis of Priority Structures Exploiting Logical Don’t Care Conditions Resource Sharing

Circuit Synthesis Multilevel Logic Synthesis Timing Issues in Multiple-Level Logic

Optimization Behavioral or High-Level Synthesis Synthesis of Combinational Logic Synthesis of Priority Structures Exploiting Logical Don’t Care Conditions Resource Sharing

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OutlineOutlineOutlineOutline

Synthesis of Sequential Logic with Latches Synthesis of Three-State Devices and Bus Interfaces Synthesis of Sequential Logic with Flip-Flops Synthesis of Explicit State Machine Synthesis of Gated Clocks and Clock Enable Synthesis of loops

Synthesis of Sequential Logic with Latches Synthesis of Three-State Devices and Bus Interfaces Synthesis of Sequential Logic with Flip-Flops Synthesis of Explicit State Machine Synthesis of Gated Clocks and Clock Enable Synthesis of loops

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Circuit SynthesisCircuit SynthesisCircuit SynthesisCircuit Synthesis

Architectural-level synthesis• Determine the macroscopic structure

• Interconnection of major building blocks.

Logic-level synthesis• Determine the microscopic structure

• Interconnection of logic gates.

Geometrical-level synthesis (Physical design)• Placement and routing.

• Determine positions and connections.

Architectural-level synthesis• Determine the macroscopic structure

• Interconnection of major building blocks.

Logic-level synthesis• Determine the microscopic structure

• Interconnection of logic gates.

Geometrical-level synthesis (Physical design)• Placement and routing.

• Determine positions and connections.

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Logic Synthesis FlowLogic Synthesis FlowLogic Synthesis FlowLogic Synthesis Flow

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Multilevel Logic SynthesisMultilevel Logic SynthesisMultilevel Logic SynthesisMultilevel Logic Synthesis

Combinational logic circuits very often implemented as multiple-level networks of logic gates.

Provides several degrees of freedom in logic design• Exploited in optimizing area and delay.• Different timing requirements on input/output paths.

Multiple-level networks viewed as interconnection of single-output gates• Single type of gate (e.g. NANDs or NORs).• Instances of a cell library.• Macro cells.

Multilevel optimization is divided into two tasks• Optimization neglecting implementation constraints assuming

loose models of area and delay.• Constraints on the usable gates are taken into account during

optimization.

Combinational logic circuits very often implemented as multiple-level networks of logic gates.

Provides several degrees of freedom in logic design• Exploited in optimizing area and delay.• Different timing requirements on input/output paths.

Multiple-level networks viewed as interconnection of single-output gates• Single type of gate (e.g. NANDs or NORs).• Instances of a cell library.• Macro cells.

Multilevel optimization is divided into two tasks• Optimization neglecting implementation constraints assuming

loose models of area and delay.• Constraints on the usable gates are taken into account during

optimization.

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Circuit ModelingCircuit ModelingCircuit ModelingCircuit Modeling

Logic network• Interconnection of logic functions.

• Hybrid structural/behavioral model.

Bound (mapped) networks• Interconnection of logic gates.

• Structural model.

Logic network• Interconnection of logic functions.

• Hybrid structural/behavioral model.

Bound (mapped) networks• Interconnection of logic gates.

• Structural model.

Example of Bound Network

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Example of a Logic NetworkExample of a Logic NetworkExample of a Logic NetworkExample of a Logic Network

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Network OptimizationNetwork OptimizationNetwork OptimizationNetwork Optimization

Two-level logic• Area and delay proportional to cover size. • Achieving minimum (or irredundant) covers corresponds to

optimizing area and speed.• Achieving irredundant cover corresponds to maximizing

testability. Multiple-level logic

• Minimal-area implementations do not correspond in general to minimum-delay implementations and vice versa.

• Minimize area (power) estimate• subject to delay constraints.

• Minimize maximum delay• subject to area (power) constraints.

• Minimize power consumption.• subject to delay constraints.

• Maximize testability.

Two-level logic• Area and delay proportional to cover size. • Achieving minimum (or irredundant) covers corresponds to

optimizing area and speed.• Achieving irredundant cover corresponds to maximizing

testability. Multiple-level logic

• Minimal-area implementations do not correspond in general to minimum-delay implementations and vice versa.

• Minimize area (power) estimate• subject to delay constraints.

• Minimize maximum delay• subject to area (power) constraints.

• Minimize power consumption.• subject to delay constraints.

• Maximize testability.

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EstimationEstimationEstimationEstimation

Area• Number of literals

• Corresponds to number of polysilicon strips (transistors)

• Number of functions/gates.

Delay• Number of stages (unit delay per stage).

• Refined gate delay models (relating delay to function complexity and fanout).

• Sensitizable paths (detection of false paths).

• Wiring delays estimated using statistical models.

Area• Number of literals

• Corresponds to number of polysilicon strips (transistors)

• Number of functions/gates.

Delay• Number of stages (unit delay per stage).

• Refined gate delay models (relating delay to function complexity and fanout).

• Sensitizable paths (detection of false paths).

• Wiring delays estimated using statistical models.

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Problem AnalysisProblem AnalysisProblem AnalysisProblem Analysis

Multiple-level optimization is hard. Exact methods

• Exponential complexity.

• Impractical.

Approximate methods• Heuristic algorithms.

• Rule-based methods.

Strategies for optimization• Improve circuit step by step based on circuit transformations.

• Preserve network behavior.

• Methods differ in• Types of transformations.• Selection and order of transformations.

Multiple-level optimization is hard. Exact methods

• Exponential complexity.

• Impractical.

Approximate methods• Heuristic algorithms.

• Rule-based methods.

Strategies for optimization• Improve circuit step by step based on circuit transformations.

• Preserve network behavior.

• Methods differ in• Types of transformations.• Selection and order of transformations.

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EliminationEliminationEliminationElimination

Eliminate one function from the network. Perform variable substitution. Example

• s = r +b’; r = p+a’ s = p+a’+b’.

Eliminate one function from the network. Perform variable substitution. Example

• s = r +b’; r = p+a’ s = p+a’+b’.

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DecompositionDecompositionDecompositionDecomposition

Break one function into smaller ones. Introduce new vertices in the network. Example

• v = a’d+bd+c’d+ae’. j = a’+b+c’; v = jd+ae’

Break one function into smaller ones. Introduce new vertices in the network. Example

• v = a’d+bd+c’d+ae’. j = a’+b+c’; v = jd+ae’

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FactoringFactoringFactoringFactoring

Factoring is the process of deriving a factored form from a sum-of-products form of a function.

Factoring is like decomposition except that no additional nodes are created.

Example• F = abc+abd+a’b’c+a’b’d+ab’e+ab’f+a’be+a’bf (24 literals)

• After factorization• F=(ab+a’b’)(c+d) + (ab’+a’b)(e+f) (12 literals)

Factoring is the process of deriving a factored form from a sum-of-products form of a function.

Factoring is like decomposition except that no additional nodes are created.

Example• F = abc+abd+a’b’c+a’b’d+ab’e+ab’f+a’be+a’bf (24 literals)

• After factorization• F=(ab+a’b’)(c+d) + (ab’+a’b)(e+f) (12 literals)

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Extraction …Extraction …Extraction …Extraction …

Find a common sub-expression of two (or more) expressions.

Extract sub-expression as new function. Introduce new vertex in the network. Example

• p = ce+de; t = ac+ad+bc+bd+e; (13 literals)

• p = (c+d)e; t = (c+d)(a+b)+e; (Factoring:8 literals) k = c+d; p = ke; t = ka+ kb +e; (Extraction:9 literals)

Find a common sub-expression of two (or more) expressions.

Extract sub-expression as new function. Introduce new vertex in the network. Example

• p = ce+de; t = ac+ad+bc+bd+e; (13 literals)

• p = (c+d)e; t = (c+d)(a+b)+e; (Factoring:8 literals) k = c+d; p = ke; t = ka+ kb +e; (Extraction:9 literals)

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… … ExtractionExtraction… … ExtractionExtraction

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SimplificationSimplificationSimplificationSimplification

Simplify a local function (using Espresso). Example

• u = q’c+qc’ +qc; u = q +c;

Simplify a local function (using Espresso). Example

• u = q’c+qc’ +qc; u = q +c;

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SubstitutionSubstitutionSubstitutionSubstitution

Simplify a local function by using an additional input that was not previously in its support set.

Example• t = ka+kb+e. t = kq +e; because q = a+b.

Simplify a local function by using an additional input that was not previously in its support set.

Example• t = ka+kb+e. t = kq +e; because q = a+b.

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Example: Sequence of TransformationsExample: Sequence of TransformationsExample: Sequence of TransformationsExample: Sequence of Transformations

Original Network (33 lit.) Transformed Network (20 lit.)

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Timing Issues in Multiple-Level LogicTiming Issues in Multiple-Level LogicOptimizationOptimizationTiming Issues in Multiple-Level LogicTiming Issues in Multiple-Level LogicOptimizationOptimization

Timing optimization is crucial for achieving competitive logic design.

Timing verification: Check that a circuit runs at speed• Satisfies I/O delay constraints.

• Satisfies cycle-time constraints.

• Delay modeling.

• Critical paths.

• The false path problem.

Algorithms for timing optimization.• Minimum area subject to delay constraints.

• Minimum delay (subject to area constraints).

Timing optimization is crucial for achieving competitive logic design.

Timing verification: Check that a circuit runs at speed• Satisfies I/O delay constraints.

• Satisfies cycle-time constraints.

• Delay modeling.

• Critical paths.

• The false path problem.

Algorithms for timing optimization.• Minimum area subject to delay constraints.

• Minimum delay (subject to area constraints).

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Delay ModelingDelay ModelingDelay ModelingDelay Modeling

Gate delay modeling• Straightforward for bound networks.

• Approximations for unbound networks.

Network delay modeling• Compute signal propagation

• Topological methods.• Logic/topological methods.

Gate delay modeling for unbound networks• Virtual gates: Logic expressions.

• Stage delay model: Unit delay per vertex.

• Refined models: Depending on size and fanout.

Gate delay modeling• Straightforward for bound networks.

• Approximations for unbound networks.

Network delay modeling• Compute signal propagation

• Topological methods.• Logic/topological methods.

Gate delay modeling for unbound networks• Virtual gates: Logic expressions.

• Stage delay model: Unit delay per vertex.

• Refined models: Depending on size and fanout.

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Network Delay Modeling …Network Delay Modeling …Network Delay Modeling …Network Delay Modeling …

For each vertex vi.

• Propagation delay di.

Data-ready time ti.• Denotes the time at which the data is ready at the output.

• Input data-ready times denote when inputs are available.

• Computed elsewhere by forward traversal

The maximum data-ready time occurring at an output vertex• Corresponds to the longest propagation delay path

• Called topological critical path

For each vertex vi.

• Propagation delay di.

Data-ready time ti.• Denotes the time at which the data is ready at the output.

• Input data-ready times denote when inputs are available.

• Computed elsewhere by forward traversal

The maximum data-ready time occurring at an output vertex• Corresponds to the longest propagation delay path

• Called topological critical path

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… … Network Delay Modeling …Network Delay Modeling …… … Network Delay Modeling …Network Delay Modeling …

Assume ta=0 and tb=10.

Propagation delays

• dg = 3; dh = 8; dm = 1; dk = 10; dl = 3;

• dn = 5; dp = 2; dq = 2; dx = 2; dy = 3;

• Maximum data-ready time is ty=25

• Topological critical path: (vb, vn, vp, vl, vq, vy).

Assume ta=0 and tb=10.

Propagation delays

• dg = 3; dh = 8; dm = 1; dk = 10; dl = 3;

• dn = 5; dp = 2; dq = 2; dx = 2; dy = 3;

• Maximum data-ready time is ty=25

• Topological critical path: (vb, vn, vp, vl, vq, vy).

tg= 3+0=3th= 8+3=11tk= 10+3=13tn= 5+10=15tp= 2+max{15,3}=17tl= 3+max{13,17}=20tm= 1+max{3,11,20}=21tx= 2+21=23tq= 2+20=22ty= 3+22=25

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… … Network Delay Modeling …Network Delay Modeling …… … Network Delay Modeling …Network Delay Modeling …

For each vertex vi.

• Required data-ready time ti.• Specified at the primary outputs.• Computed elsewhere by backward traversal

• Slack si.• Difference between required and actual data-ready times

For each vertex vi.

• Required data-ready time ti.• Specified at the primary outputs.• Computed elsewhere by backward traversal

• Slack si.• Difference between required and actual data-ready times

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… … Network Delay ModelingNetwork Delay Modeling… … Network Delay ModelingNetwork Delay Modeling

Required data-ready times

• tx = 25 and ty = 25.

Required data-ready times

• tx = 25 and ty = 25.

Required Times & Slack:sx= 2; sy=0tm= 25-2=23; sm=23-21=2tq= 25-3=22; sq=22-22=0tl= min{23-1,22-2}=20; sl=0th= 23-1=22; sh=22-11=11tk= 20-3=17; sk=17-13=4tp= 20-3=17; sp=17-17=0tn= 17-2=15; sn=15-15=0tb= 15-5=10; sb=10-10=0tg= min{22-8;17-10;17-2}=7; sg=4ta=7-3=4; sa=4-0=4

Data-Ready Times:tg= 3+0=3th= 8+3=11tk= 10+3=13tn= 5+10=15tp= 2+max{15,3}=17tl= 3+max{13,17}=20tm= 1+max{3,11,20}=21tx= 2+21=23tq= 2+20=22ty= 3+22=25

Propagation Delays :dg = 3; dh = 8; dm = 1; dk = 10; dl = 3; dn = 5; dp = 2; dq = 2;dx = 2; dy = 3

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Topological Critical Path …Topological Critical Path …Topological Critical Path …Topological Critical Path …

Assume topologic computation of• Data-ready by forward traversal.

• Required data-ready by backward traversal.

Topological critical path• Input/output path with zero slacks.

• Any increase in the vertex propagation delay affects the output data-ready time.

A topological critical path may be false.• No event can propagate along that path.

• False path does not affect performance

Assume topologic computation of• Data-ready by forward traversal.

• Required data-ready by backward traversal.

Topological critical path• Input/output path with zero slacks.

• Any increase in the vertex propagation delay affects the output data-ready time.

A topological critical path may be false.• No event can propagate along that path.

• False path does not affect performance

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… … Topological Critical PathTopological Critical Path… … Topological Critical PathTopological Critical Path

Topological critical path: (vb, vn, vp, vl, vq, vy).

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False Path ExampleFalse Path ExampleFalse Path ExampleFalse Path Example

All gates have unit delay. All inputs ready at time 0.

Longest topological path: (va, vc, vd, vy, vz).• Path delay: 4 units.

• False path: event cannot propagate through it

Critical true path: (va, vc, vd, vy).• Path delay: 3 units.

All gates have unit delay. All inputs ready at time 0.

Longest topological path: (va, vc, vd, vy, vz).• Path delay: 4 units.

• False path: event cannot propagate through it

Critical true path: (va, vc, vd, vy).• Path delay: 3 units.

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Algorithms for Delay Minimization …Algorithms for Delay Minimization …Algorithms for Delay Minimization …Algorithms for Delay Minimization …

Alternate• Critical path computation.

• Logic transformation on critical vertices.

Consider quasi critical paths• Paths with near-critical delay.

• Small slacks.

Small difference between critical paths and largest delay of a non-critical path leads to smaller gain in speeding up critical paths only.

Alternate• Critical path computation.

• Logic transformation on critical vertices.

Consider quasi critical paths• Paths with near-critical delay.

• Small slacks.

Small difference between critical paths and largest delay of a non-critical path leads to smaller gain in speeding up critical paths only.

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Behavioral or High-Level SynthesisBehavioral or High-Level SynthesisBehavioral or High-Level SynthesisBehavioral or High-Level Synthesis

The automatic generation of data path and control unit is known as high-level synthesis.

Tasks involved in HLS are scheduling and allocation.

Scheduling distributes the execution of operations throughout time steps.

Allocation assigns hardware to operations and values.

•Allocation of hardware cells includes functional unit allocation, register allocation and bus allocation.

•Allocation determines the interconnections required.

The automatic generation of data path and control unit is known as high-level synthesis.

Tasks involved in HLS are scheduling and allocation.

Scheduling distributes the execution of operations throughout time steps.

Allocation assigns hardware to operations and values.

•Allocation of hardware cells includes functional unit allocation, register allocation and bus allocation.

•Allocation determines the interconnections required.

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Behavioral Description and its Control Behavioral Description and its Control Data Flow Graph (CDFG)Data Flow Graph (CDFG)Behavioral Description and its Control Behavioral Description and its Control Data Flow Graph (CDFG)Data Flow Graph (CDFG)

X = W + ( S * T )Y = ( S * T ) + ( U * V )

*

+

*

+

W S T U V

X Y

(a)

CDFG

(b)

*

*+

+

W S T U V

X Y

1

2

3

(c)

Scheduled CDFG

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Resulting Architecture DesignResulting Architecture DesignResulting Architecture DesignResulting Architecture Design

MUX

X Y W

+

Z MUXMUX

*

S U T V

Bus 1 Data Path

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Architectural Design Space Example Architectural Design Space Example Architectural Design Space Example Architectural Design Space Example

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Architectural Design Space Example Architectural Design Space Example Architectural Design Space Example Architectural Design Space Example

1 Multiplier , 1 ALU 2 Multipliers, 2 ALUs

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Architectural Design Space ExampleArchitectural Design Space ExampleArchitectural Design Space ExampleArchitectural Design Space Example

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Synthesis of Combinational LogicSynthesis of Combinational LogicSynthesis of Combinational LogicSynthesis of Combinational Logic

Synthesizable combinational logic can be described with Verilog HDL using:• Netlist of structural primitives

• A set of continuous assignment statements

• A level-sensitive cyclic behavior if it assigns a value to each output for every possible value of its inputs

UDPs are not supported by most EDA vendors. Synthesis tools ensure that any redundant logic is

removed from combinational logic before it is mapped into a technology.

Synthesizable combinational logic can be described with Verilog HDL using:• Netlist of structural primitives

• A set of continuous assignment statements

• A level-sensitive cyclic behavior if it assigns a value to each output for every possible value of its inputs

UDPs are not supported by most EDA vendors. Synthesis tools ensure that any redundant logic is

removed from combinational logic before it is mapped into a technology.

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module boole_opt (output y_out1, y_out2, input a, b, c, d, e);

wire y1, y2, y3, y4, y5, y6, y7, y8;and (y1, a, c);and (y2, a, d);and (y3, a, e);or (y4, y1, y2);or (y_out1, y3, y4);and (y5, b, c);and (y6, b, d);and (y7, b, e);or (y8, y5, y6);or (y_out2, y7, y8);endmodule

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module or_and (output y, input enable, x1, x2, x3, x4);

assign y = ~(enable & (x1 | x2) & (x3 | x4));endmodule

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module comparator #(parameter size=2)(output reg a_gt_b, a_lt_b, a_eq_b,input [size-1:0] a, b );integer k;always @ (a, b) begin: compare_loop for (k=size-1; k>=0; k=k-1) begin if (a[k] != b[k]) begin a_gt_b = a[k]; a_lt_b = ~a[k]; a_eq_b = 0; disable compare_loop; end end a_gt_b = 0; a_lt_b = 0; a_eq_b = 1;endendmodule

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Synthesis of Priority StructuresSynthesis of Priority StructuresSynthesis of Priority StructuresSynthesis of Priority Structures

A case statement implicitly attaches higher priority to the first item than to the last one.

If the case items are mutually exclusive synthesis tool will synthesize a mux rather than a priority structure.

An if statement implies higher priority to the first branch than to the remaining branches.

An if statement will synthesize to a mux structure if the branching is specified by mutually exclusive conditions.

If not all conditions are specified in a case of if statement will cause latches to be implemented by synthesis tool.

A case statement implicitly attaches higher priority to the first item than to the last one.

If the case items are mutually exclusive synthesis tool will synthesize a mux rather than a priority structure.

An if statement implies higher priority to the first branch than to the remaining branches.

An if statement will synthesize to a mux structure if the branching is specified by mutually exclusive conditions.

If not all conditions are specified in a case of if statement will cause latches to be implemented by synthesis tool.

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Synthesis of Priority StructuresSynthesis of Priority StructuresSynthesis of Priority StructuresSynthesis of Priority Structures

module mux_4pri (output reg y, input a, b, c, d, sel_a, sel_b, selc);

always @ (*) // wildcard for complete sensitivity list

if (sel_a == 1) y=a;

else if (sel_b==1) y=b;

else if (sel_c==1) y=c;

else y=d;

endmodule;

module mux_4pri (output reg y, input a, b, c, d, sel_a, sel_b, selc);

always @ (*) // wildcard for complete sensitivity list

if (sel_a == 1) y=a;

else if (sel_b==1) y=b;

else if (sel_c==1) y=c;

else y=d;

endmodule;

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Exploiting Logical Don’t Care Exploiting Logical Don’t Care ConditionsConditionsExploiting Logical Don’t Care Exploiting Logical Don’t Care ConditionsConditions An assignment to x in a case or if statement will be

treated as a don’t care condition in synthesis.module alu_with_x (output alu_out, input [3:0] data_a, data_b,

input [2:0] opcode, input enable);

reg [3:0] alu_reg;

assign alu_out=(enable==1)?alu_reg:4’bz;

always @ (opcode, data_a, data_b)

case (opcode)

3’b001: alu_reg= data_a | data_b;

3’b010: alu_reg= data_a ^ data_b;

3’b110: alu_reg= ~data_b;

default: alu_reg= 4’b0;

endcase

endmodule

An assignment to x in a case or if statement will be treated as a don’t care condition in synthesis.

module alu_with_x (output alu_out, input [3:0] data_a, data_b,


reg [3:0] alu_reg;



case (opcode)




default: alu_reg= 4’b0;

endcase

endmodule

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Exploiting Logical Don’t Care Exploiting Logical Don’t Care ConditionsConditionsExploiting Logical Don’t Care Exploiting Logical Don’t Care ConditionsConditionsmodule alu_with_x (output alu_out, input [3:0] data_a, data_b,


reg [3:0] alu_reg;



case (opcode)




default: alu_reg= 4’bx;

endcase

endmodule

module alu_with_x (output alu_out, input [3:0] data_a, data_b,


reg [3:0] alu_reg;



case (opcode)




default: alu_reg= 4’bx;

endcase

endmodule

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Resource SharingResource SharingResource SharingResource Sharing

A synthesis tool must recognize whether physical resources required to implement behaviors can be shared.

Use parenthesis to control operator grouping and reduce the size of the circuit

Example:module res_share (output [4:0] y_out, input [3:0] data_a, data_b,

accum, input sel);

assign y_out = data_a + (sel ? accum : data_b);

endmodule

Failure to include the parenethesis for y_out may lead to synthesis of a circuit that uses two adders.

A synthesis tool must recognize whether physical resources required to implement behaviors can be shared.

Use parenthesis to control operator grouping and reduce the size of the circuit

Example:module res_share (output [4:0] y_out, input [3:0] data_a, data_b,

accum, input sel);

assign y_out = data_a + (sel ? accum : data_b);

endmodule

Failure to include the parenethesis for y_out may lead to synthesis of a circuit that uses two adders.

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Resource SharingResource SharingResource SharingResource Sharing

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Synthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesSynthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesmodule latchif2 (output reg [3:0] data_out, input [3:0] data_in, input

latch_enable);

always @ (latch_enable, data_in)

if (latch_enable) data_out = data_in;

endmodule

module latchif2 (output reg [3:0] data_out, input [3:0] data_in, input latch_enable);


if (latch_enable) data_out = data_in;

endmodule

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Synthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesSynthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatches When a variable is assigned to itself, synthesis tools

will synthesize a mux with feedback. A continuous assignment statement using a

conditional operator with feedback will synthesize into a latch.

Example:assign data_out = data_enable?data_in:data_out;

module latchif1 (output reg [3:0] data_out,

input [3:0] data_in, input latch_enable);


if (latch_enable) data_out <= data_in;

else data_out <= data_out;

endmodule

When a variable is assigned to itself, synthesis tools will synthesize a mux with feedback.

A continuous assignment statement using a conditional operator with feedback will synthesize into a latch.

Example:assign data_out = data_enable?data_in:data_out;

module latchif1 (output reg [3:0] data_out,

input [3:0] data_in, input latch_enable);


if (latch_enable) data_out <= data_in;

else data_out <= data_out;

endmodule

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Synthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesSynthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesmodule latch_case2(output reg latch_out, input latch_in, set, clear, enable);

always @(enable or set or clear or latch_in) // latch_in in activity list.

case ({enable, set, clear})

3’b000: latch_out = latch_in;

3’b110: latch_out = 1’b1;




endcase

endmodule

module latch_case2(output reg latch_out, input latch_in, set, clear, enable);








endcase

endmodule

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Synthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesSynthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesmodule latch_case2(output reg latch_out, input latch_in, set, clear, enable);








default: latch_out = latch_out;

endcase

endmodule

module latch_case2(output reg latch_out, input latch_in, set, clear, enable);








default: latch_out = latch_out;

endcase

endmodule

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Synthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesSynthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesmodule Latched_Seven_Seg_Display(output reg [6:0] Display_L, Display_R,

input Blcnking, Enable, clock, reset);

reg [3:0] count;

// abc_defg

parameter BLANK = 7’b111_1111;

parameter Zero= 7’b000_0001; // h01

parameter ONE= 7’b100_1111; // h4f

parameter TWO= 7’b001_0010; // h12

parameter THREE= 7’b000_0110; // h06

parameter FOUR= 7’b100_1100; // h4c

parameter FIVE= 7’b010_0100; // h24

parameter SIX= 7’b010_0000; // h20

parameter SEVEN= 7’b000_1111; // h0f

parameter EIGHT= 7’b000_0000; // h00

parameter NINE= 7’b000_0100; // h04

module Latched_Seven_Seg_Display(output reg [6:0] Display_L, Display_R, input Blcnking, Enable, clock, reset);

reg [3:0] count;

// abc_defg

parameter BLANK = 7’b111_1111;

parameter Zero= 7’b000_0001; // h01

parameter ONE= 7’b100_1111; // h4f

parameter TWO= 7’b001_0010; // h12

parameter THREE= 7’b000_0110; // h06

parameter FOUR= 7’b100_1100; // h4c

parameter FIVE= 7’b010_0100; // h24

parameter SIX= 7’b010_0000; // h20

parameter SEVEN= 7’b000_1111; // h0f

parameter EIGHT= 7’b000_0000; // h00

parameter NINE= 7’b000_0100; // h04

1-51

Synthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesSynthesis of Sequential Logic with Synthesis of Sequential Logic with LatchesLatchesalways @ (posedge clock)

if (reset) count <= 0; else if (Enable) count <= count +1;

always @ (count, Blanking)

if (Blanking) begin Display_L=BLANK; DISPLAY_R=BLANK; end else

case (count)

0: begin; Display_L=ZERO; DISPLAY_R=ZERO; end

2: begin; Display_L=ZERO; DISPLAY_R=TWO; end

4: begin; Display_L=ZERO; DISPLAY_R=FOUR; end

6: begin; Display_L=ZERO; DISPLAY_R=SIX; end

8: begin; Display_L=ZERO; DISPLAY_R=EIGHT; end

10: begin; Display_L=ONE; DISPLAY_R=ZERO; end

12: begin; Display_L=ONE; DISPLAY_R=TWO; end

14: begin; Display_L=ONE; DISPLAY_R=FOUR; end

endcase

endmodule

always @ (posedge clock)

if (reset) count <= 0; else if (Enable) count <= count +1;

always @ (count, Blanking)

if (Blanking) begin Display_L=BLANK; DISPLAY_R=BLANK; end else

case (count)

0: begin; Display_L=ZERO; DISPLAY_R=ZERO; end

2: begin; Display_L=ZERO; DISPLAY_R=TWO; end

4: begin; Display_L=ZERO; DISPLAY_R=FOUR; end

6: begin; Display_L=ZERO; DISPLAY_R=SIX; end

8: begin; Display_L=ZERO; DISPLAY_R=EIGHT; end

10: begin; Display_L=ONE; DISPLAY_R=ZERO; end

12: begin; Display_L=ONE; DISPLAY_R=TWO; end

14: begin; Display_L=ONE; DISPLAY_R=FOUR; end

endcase

endmodule

1-52

Accidental Synthesis of LatchesAccidental Synthesis of LatchesAccidental Synthesis of LatchesAccidental Synthesis of Latches

Verilog Case and if statements that do not include all possible cases or conditions will lead to synthesis of latches.

module mux_latch (output reg y_out, input data_a, data_b, sel_a, sel_b);

always @ (sel_a, sel_b, data_a, data_b)

case ({sel_a, sel_b})

2’b10: y_out = data_a;

2’b01: y_out = data_b;

endcase

endmodule

Verilog Case and if statements that do not include all possible cases or conditions will lead to synthesis of latches.

module mux_latch (output reg y_out, input data_a, data_b, sel_a, sel_b);

always @ (sel_a, sel_b, data_a, data_b)

case ({sel_a, sel_b})

2’b10: y_out = data_a;

2’b01: y_out = data_b;

endcase

endmodule

1-53

Accidental Synthesis of LatchesAccidental Synthesis of LatchesAccidental Synthesis of LatchesAccidental Synthesis of Latches

In an always block, all inputs must be included in sensitivity list.

Use always @ (*) or always @ *module or_latch #parameter(word_length=4)(

output reg y; input [word_length-1:0] x_in);

Integer k;

always @(x_in[3:1]) begin: check_for_1

y=0;

for (k=0; k<=word_length-1;k=k+1)

if (x_in[k]==1) begin

y=1; disable check_for_1;

end

end

endmodule

In an always block, all inputs must be included in sensitivity list.

Use always @ (*) or always @ *module or_latch #parameter(word_length=4)(

output reg y; input [word_length-1:0] x_in);

Integer k;

always @(x_in[3:1]) begin: check_for_1

y=0;

for (k=0; k<=word_length-1;k=k+1)

if (x_in[k]==1) begin

y=1; disable check_for_1;

end

end

endmodule

1-54

Synthesis of Three-State Devices and Synthesis of Three-State Devices and Bus InterfacesBus InterfacesSynthesis of Three-State Devices and Synthesis of Three-State Devices and Bus InterfacesBus Interfaces Three-state devices allow buses to be shared among

multiple devices. Preferred style for inferring a three-state bus driver

uses a continuous assignment that has one branch set to z.

module Uni_dir_bus (output [31:0] data_to_bus, input bus_enabled);

reg [31:0] ckt_to_bus;

assign data_to_bus = (bus_enabled) ? ckt_to_bus ? 32’bz;

// description of core circuit goes here to drive ckt_to_bus

endmodule

Three-state devices allow buses to be shared among multiple devices.

Preferred style for inferring a three-state bus driver uses a continuous assignment that has one branch set to z.

module Uni_dir_bus (output [31:0] data_to_bus, input bus_enabled);

reg [31:0] ckt_to_bus;

assign data_to_bus = (bus_enabled) ? ckt_to_bus ? 32’bz;

// description of core circuit goes here to drive ckt_to_bus

endmodule

1-55

Synthesis of Three-State Devices and Synthesis of Three-State Devices and Bus InterfacesBus InterfacesSynthesis of Three-State Devices and Synthesis of Three-State Devices and Bus InterfacesBus Interfacesmodule Bi_dir_bus (inout [31:0] data_to_from_bus, input send_data,

rcv_data);

wire [31:0] ckt_to_bus;

wire [31:0] data_from_bus;

assign data_from_bus = (rcv_data)?data_to_from_bus:32’bz;

assign data_to_from_bus = (send_data)?ckt_to_bus:data_to_from_bus;

// Behavior using data_from_bus and generating ckt_to_bus goes here

endmodule

module Bi_dir_bus (inout [31:0] data_to_from_bus, input send_data, rcv_data);

wire [31:0] ckt_to_bus;

wire [31:0] data_from_bus;

assign data_from_bus = (rcv_data)?data_to_from_bus:32’bz;

assign data_to_from_bus = (send_data)?ckt_to_bus:data_to_from_bus;

// Behavior using data_from_bus and generating ckt_to_bus goes here

endmodule

1-56

Synthesis of Sequential Logic with Synthesis of Sequential Logic with Flip-FlopsFlip-FlopsSynthesis of Sequential Logic with Synthesis of Sequential Logic with Flip-FlopsFlip-Flops A register variable in an edge-sensitive behavior will be

synthesized as a flip-flop if:• It is referenced outside the scope of the behavior

• It is referenced within the behavior before it is assigned value

• It is assigned value in only some of the branches of the activity within the behavior

By decoding signals immediately after the event control expression allows the synthesis tool to determine:• Which of the edge-sensitive signals are control signals

• Which is the synchronizing signal.

If the event control expression is sensitive to the edge of more than one signal, an if stmt must be the first stmt in the behavior.

A register variable in an edge-sensitive behavior will be synthesized as a flip-flop if:• It is referenced outside the scope of the behavior

• It is referenced within the behavior before it is assigned value

• It is assigned value in only some of the branches of the activity within the behavior

By decoding signals immediately after the event control expression allows the synthesis tool to determine:• Which of the edge-sensitive signals are control signals

• Which is the synchronizing signal.

If the event control expression is sensitive to the edge of more than one signal, an if stmt must be the first stmt in the behavior.

1-57

Synthesis of Sequential Logic with Synthesis of Sequential Logic with Flip-FlopsFlip-FlopsSynthesis of Sequential Logic with Synthesis of Sequential Logic with Flip-FlopsFlip-Flops The control signals must be decoded explicitly in the

branches of the if stmt. Decode the reset condition first.module swap_synth (output reg data_a, data_b, input set1, set2, clk);

always @ (posedge clk) begin

if (set1) begin data_a<=1; data_b<=0; end else

if (set2) begin data_a<=0; data_b<=1; end

else begin

data_b <= data_a; data_a <= data_b;

end

end

endmodule

The control signals must be decoded explicitly in the branches of the if stmt.

Decode the reset condition first.module swap_synth (output reg data_a, data_b, input set1, set2, clk);


if (set1) begin data_a<=1; data_b<=0; end else

if (set2) begin data_a<=0; data_b<=1; end

else begin

data_b <= data_a; data_a <= data_b;

end

end

endmodule

1-58

Synthesis of Sequential Logic with Synthesis of Sequential Logic with Flip-FlopsFlip-FlopsSynthesis of Sequential Logic with Synthesis of Sequential Logic with Flip-FlopsFlip-Flopsmodule D_reg4 (output reg [3:0] Data_out, input [3:0] Data_in, input clock,

reset)

always @ (posedge clock, posedge reset) begin

if (reset == 1’b1) Data_out <= 4’b0;

else Data_out <= Data_in;

endmodule

module D_reg4 (output reg [3:0] Data_out, input [3:0] Data_in, input clock, reset)

always @ (posedge clock, posedge reset) begin

if (reset == 1’b1) Data_out <= 4’b0;

else Data_out <= Data_in;

endmodule

1-59

Synthesis of Sequential Logic with Synthesis of Sequential Logic with Flip-FlopsFlip-FlopsSynthesis of Sequential Logic with Synthesis of Sequential Logic with Flip-FlopsFlip-Flops The behavior in empty_circuit assigns value to register

variable D_out, but D_out is not referenced outside the scope of behavior.

Synthesis tool will eliminate D_out.

module empty_circuit (input D_in, clk)

reg D_out;


D_out<= D_in;

end

endmodule

The behavior in empty_circuit assigns value to register variable D_out, but D_out is not referenced outside the scope of behavior.

Synthesis tool will eliminate D_out.

module empty_circuit (input D_in, clk)

reg D_out;


D_out<= D_in;

end

endmodule

1-60

Synthesis of Explicit State MachineSynthesis of Explicit State MachineSynthesis of Explicit State MachineSynthesis of Explicit State Machine

Use two cyclic behaviors to describe an explicit state machine:• A level-sensitive behavior to describe the combinational logic

for the next state and outputs

• An edge-sensitive behavior to synchronize the state transitions

Use the blocking procedural assignment operator (=) in the level-sensitive cyclic behaviors describing the combinational logic of a FSM.

Use the nonblocking assignment operator (<=) in the edge-sensitive cyclic behavior describing the state transitions of a FSM and the register transfers of the datapath of the sequential machine.

Use two cyclic behaviors to describe an explicit state machine:• A level-sensitive behavior to describe the combinational logic

for the next state and outputs

• An edge-sensitive behavior to synchronize the state transitions

Use the blocking procedural assignment operator (=) in the level-sensitive cyclic behaviors describing the combinational logic of a FSM.

Use the nonblocking assignment operator (<=) in the edge-sensitive cyclic behavior describing the state transitions of a FSM and the register transfers of the datapath of the sequential machine.

1-61

BCD-to-Excess-3 Code ConverterBCD-to-Excess-3 Code ConverterBCD-to-Excess-3 Code ConverterBCD-to-Excess-3 Code Converter

module BCD_to_Excess_3b (output reg B_out, input B_in, clk, reset_b);

// state assignment

parameter s_0=3’b000;

s_1=3’b001;

s_2=3’b101;

s_3=3’b111;

s_4=3’b011;

s_5=3’b100;

s_6=3’b010;

dont_care_state=3’bx;

dont_care_out=1’bx;

reg [2:0] state, next_state;

module BCD_to_Excess_3b (output reg B_out, input B_in, clk, reset_b);

// state assignment

parameter s_0=3’b000;

s_1=3’b001;

s_2=3’b101;

s_3=3’b111;

s_4=3’b011;

s_5=3’b100;

s_6=3’b010;




1-62


always @ (posedge clk, negedge reset_b)

if (reset_b==0) state<= S_0; else state <= next _state;

always @ (state, B_in) begin

B_out = 0; //default assignment

case (state)

S_0: if (B_in==0) begin

next_state=S_1; B_out=1;

end

else next_state=S_2;



end






case (state)



end




end


1-63


S_2: begin next_state=S_4; B_out=B_in; end




end



S_6: begin next_state=S_0; B_out=1; end

/* default: begin

next_state=don’t_care_state;

B_out=don’t_care_out;

end */

endcase

end

endmodule





end



S_6: begin next_state=S_0; B_out=1; end

/* default: begin



end */

endcase

end

endmodule

1-64


1-65

Mealy-Type NRZ Manchester Code Mealy-Type NRZ Manchester Code ConverterConverterMealy-Type NRZ Manchester Code Mealy-Type NRZ Manchester Code ConverterConvertermodule NRZ_2_Manchester_Mealy (output reg B_out, input B_in, clock,

reset_b);


parameter s_0=2’d0;

s_1=2’d1;

s_2=2’d2;







module NRZ_2_Manchester_Mealy (output reg B_out, input B_in, clock, reset_b);


parameter s_0=2’d0;

s_1=2’d1;

s_2=2’d2;







1-66

Mealy-Type NRZ Manchester Code Mealy-Type NRZ Manchester Code ConverterConverterMealy-Type NRZ Manchester Code Mealy-Type NRZ Manchester Code ConverterConverter

case (state)

S_0: if (B_in==0) next_state=S_1;

else begin

next_state=S_2; B_out=1; end

S_1: begin


S_2: next_state=S_0;

default: begin



end

endcase

end

endmodule

case (state)

S_0: if (B_in==0) next_state=S_1;

else begin


S_1: begin


S_2: next_state=S_0;

default: begin



end

endcase

end

endmodule

1-67

Moore Sequence RecognizerMoore Sequence RecognizerMoore Sequence RecognizerMoore Sequence Recognizer

module moore_seq_det (output D_out, input D_in,

En, clk, reset);


parameter s_idle=3’d0;

s_0=3’d1;

s_1=3’d2;

s_2=3’d3;

s_3=3’d4;

always @ (negedge clk)

if (reset==1) state<= S_idle; else state <= next _state;

assign D_out = (state == S_3);

module moore_seq_det (output D_out, input D_in,

En, clk, reset);


parameter s_idle=3’d0;

s_0=3’d1;

s_1=3’d2;

s_2=3’d3;

s_3=3’d4;

always @ (negedge clk)

if (reset==1) state<= S_idle; else state <= next _state;

assign D_out = (state == S_3);

1-68

Moore Sequence RecognizerMoore Sequence RecognizerMoore Sequence RecognizerMoore Sequence Recognizer

always @ (state, En, D_in) begin

case (state)

S_idle: if (En) begin

if (D_in) next_state=S_1;

else next_state=S_0; end

else next_state=S_idle;

S_0: if (D_in) next_state=S_1; else next_state=S_0;




default: next_state=S_idle;

endcase

end

endmodule

always @ (state, En, D_in) begin

case (state)

S_idle: if (En) begin

if (D_in) next_state=S_1;

else next_state=S_0; end

else next_state=S_idle;





default: next_state=S_idle;

endcase

end

endmodule

1-69

Synthesis of AccumulatorSynthesis of AccumulatorSynthesis of AccumulatorSynthesis of Accumulator

module Add_Accum_1 (

output reg [3:0] accum, output reg overflow,

input [3:0] data, input enable, clk, reset_b);


if (reset_b==0) begin accum<=0; overflow<=0; end

else if (enable) {overflow, accum} <= accum + data;

endmodule




wire [3:0] sum; assign {overflow, sum} <= accum + data;


if (reset_b==0) accum<=0;

else if (enable) accum <= sum;

endmodule





if (reset_b==0) begin accum<=0; overflow<=0; end

else if (enable) {overflow, accum} <= accum + data;

endmodule




wire [3:0] sum; assign {overflow, sum} <= accum + data;


if (reset_b==0) accum<=0;

else if (enable) accum <= sum;

endmodule

1-70

Synthesis of Gated Clocks and Clock Synthesis of Gated Clocks and Clock EnableEnableSynthesis of Gated Clocks and Clock Synthesis of Gated Clocks and Clock EnableEnable Designers avoid using gated clocks as lead to timing

problems. Low power designs disable clocks to disable usless

switching.module gated_clock (output reg Q, input data, data_gate, clock, reset_b);

assign gclock = clock & data_gate;

always @ (posedge gclock, negedge reset_b)

if (reset_b==0) Q<=0; else Q<=data;

endmodule

module enabled_clock (output reg Q, input data, data_gate, clock, reset_b);

always @ (posedge clock, negedge reset_)

if (reset_==0) Q<=0; else if (data_gate) Q<=data;

endmodule

Designers avoid using gated clocks as lead to timing problems.

Low power designs disable clocks to disable usless switching.

module gated_clock (output reg Q, input data, data_gate, clock, reset_b);

assign gclock = clock & data_gate;

always @ (posedge gclock, negedge reset_b)

if (reset_b==0) Q<=0; else Q<=data;

endmodule

module enabled_clock (output reg Q, input data, data_gate, clock, reset_b);

always @ (posedge clock, negedge reset_)

if (reset_==0) Q<=0; else if (data_gate) Q<=data;

endmodule

1-71

Operator GroupingOperator GroupingOperator GroupingOperator Grouping

Use parenthesis to form sub-expressions to influence outcome of synthesis.

module operator_group (output [4:0] sum1, sum2, input a, b, c, d);

assign sum1 = a + b + c + d;

assign sum2 = (a + b) + (c + d);

endmodule;

Use parenthesis to form sub-expressions to influence outcome of synthesis.

module operator_group (output [4:0] sum1, sum2, input a, b, c, d);

assign sum1 = a + b + c + d;

assign sum2 = (a + b) + (c + d);

endmodule;

1-72

Expression SubstitutionExpression SubstitutionExpression SubstitutionExpression Substitution

module multiple_reg_assign ( output reg [4:0] data_out1, data_out2,

input [3:0] data_a, data_b, data_c, data_d, input sel, clk);


data_out1 = data_a + data_b; data_out2 = data_out1+ data_c;

if (sel==1’b0) data_out1 = data_out2 + data_d;

end

endmodule

module expression_sub ( output reg [4:0] data_out1, data_out2,



data_out2 = data_a + data_b + data_c;

if (sel==1’b0) data_out1 = data_a + data_b + data_c+ data_d;

else data_out1 = data_a + data_b;

end

endmodule

module multiple_reg_assign ( output reg [4:0] data_out1, data_out2,



data_out1 = data_a + data_b; data_out2 = data_out1+ data_c;

if (sel==1’b0) data_out1 = data_out2 + data_d;

end

endmodule

module expression_sub ( output reg [4:0] data_out1, data_out2,



data_out2 = data_a + data_b + data_c;

if (sel==1’b0) data_out1 = data_a + data_b + data_c+ data_d;

else data_out1 = data_a + data_b;

end

endmodule

1-73


module expression_sub_nb ( output reg [4:0] data_out1, data_out2,



data_out2 <= data_a + data_b + data_c;

if (sel==1’b0) data_out1 <= data_a + data_b + data_c+ data_d;

else data_out1 <= data_a + data_b;

end

endmodule

module expression_sub_nb ( output reg [4:0] data_out1, data_out2,



data_out2 <= data_a + data_b + data_c;

if (sel==1’b0) data_out1 <= data_a + data_b + data_c+ data_d;

else data_out1 <= data_a + data_b;

end

endmodule

1-74


1-75

Synthesis of loopsSynthesis of loopsSynthesis of loopsSynthesis of loops

A loop in a cyclic behavior is said to be static or data-independent if the number of iterations can be determined by the compiler before simulation.

Static loops with no internal timing controls are synthesized into combinational logic.

module for_and_loop (output reg [3:0] out, input [3:0] a, b);

reg [2:0] i;

always @ (a, b) begin

for (0; i<=3; i=i+1)

out[i] = a[i] & b[i];

end

endmodule

A loop in a cyclic behavior is said to be static or data-independent if the number of iterations can be determined by the compiler before simulation.

Static loops with no internal timing controls are synthesized into combinational logic.

module for_and_loop (output reg [3:0] out, input [3:0] a, b);

reg [2:0] i;

always @ (a, b) begin

for (0; i<=3; i=i+1)

out[i] = a[i] & b[i];

end

endmodule

1-76

Synthesis of loopsSynthesis of loopsSynthesis of loopsSynthesis of loops

module count_ones # (parameter data_width=4, count_width=3)(output reg [count_width-1:0] bit_count, input [data_width-1:0] data, input clk, reset);

reg [count_width-1:0] index; reg [data_width-1:0] temp;

always @ (posedge clk)

if (reset) bit_count=0;

else begin

bit_count = 0; temp = data;

for (index=0; index<data_width; index=index+1) begin

bit_count = bit_count + temp[0]; temp = temp >> 1;

end

end

endmodule

module count_ones # (parameter data_width=4, count_width=3)(output reg [count_width-1:0] bit_count, input [data_width-1:0] data, input clk, reset);

reg [count_width-1:0] index; reg [data_width-1:0] temp;

always @ (posedge clk)

if (reset) bit_count=0;

else begin

bit_count = 0; temp = data;

for (index=0; index<data_width; index=index+1) begin

bit_count = bit_count + temp[0]; temp = temp >> 1;

end

end

endmodule

Documents

COE 405 Synthesis of Combinational & Sequential Logic Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals