COE 405 Design and Synthesis of DataPath Controllers Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals

COE 405COE 405 Design and Synthesis of Design and Synthesis of

DataPath ControllersDataPath Controllers

COE 405COE 405 Design and Synthesis of Design and Synthesis of

DataPath ControllersDataPath Controllers

Dr. Aiman H. El-Maleh

Computer Engineering Department

King Fahd University of Petroleum & Minerals

Dr. Aiman H. El-Maleh

Computer Engineering Department

King Fahd University of Petroleum & Minerals

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OutlineOutlineOutlineOutline

Design and Synthesis of RISC Stored Program Machine (SPM)

Universal Asynchronous Receiver Transceiver (UART)

Design and Synthesis of RISC Stored Program Machine (SPM)

Universal Asynchronous Receiver Transceiver (UART)

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RISM SPM ArchitectureRISM SPM ArchitectureRISM SPM ArchitectureRISM SPM Architecture

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RISC SPM Instruction FormatRISC SPM Instruction FormatRISC SPM Instruction FormatRISC SPM Instruction Format

Short Format Long Format

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RISC SPM Instruction SetRISC SPM Instruction SetRISC SPM Instruction SetRISC SPM Instruction Set

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Controller ASM ChartsController ASM ChartsController ASM ChartsController ASM Charts

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RISC SPM ModuleRISC SPM ModuleRISC SPM ModuleRISC SPM Module

module RISC_SPM #(parameter word_size=8, Set1_size=3, Set2_size=2)(

input clk, rst);

// Data Nets

wire [Set1_size-1:0] Sel_Bus_1_Mux;


wire zero;

wire [word_size-1:0] instruction, address, Bus_1, mem_word;

// Control Nets

wire Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write;

module RISC_SPM #(parameter word_size=8, Set1_size=3, Set2_size=2)(

input clk, rst);

// Data Nets



wire zero;

wire [word_size-1:0] instruction, address, Bus_1, mem_word;

// Control Nets

wire Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write;

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RISC SPM ModuleRISC SPM ModuleRISC SPM ModuleRISC SPM Module

Processing_Unit M0_Processor (instruction, address, Bus_1, zero, mem_word, Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus_1_Mux, Sel_Bus_2_Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, clk, rst);

Control_Unit M1_Controller (Sel_Bus_2_Mux, Sel_Bus_1_Mux, Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write, instruction, zero, clk, rst);

Memory_Unit M2_Mem (mem_word, Bus_1, address, clk, write);

endmodule

Processing_Unit M0_Processor (instruction, address, Bus_1, zero, mem_word, Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus_1_Mux, Sel_Bus_2_Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, clk, rst);

Control_Unit M1_Controller (Sel_Bus_2_Mux, Sel_Bus_1_Mux, Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write, instruction, zero, clk, rst);

Memory_Unit M2_Mem (mem_word, Bus_1, address, clk, write);

endmodule

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Memory Unit ModuleMemory Unit ModuleMemory Unit ModuleMemory Unit Module

module Memory_Unit #(parameter word_size=8, memory_size=256)(

output [word_size-1:0] data_out,

input [word_size-1:0] data_in, address,

input clk, write);

reg [word_size-1:0] memory[memory_size-1:0];

assign data_out = memory[address];

always @ (posedge clk)

if (write) memory[address] <= data_in;

endmodule

module Memory_Unit #(parameter word_size=8, memory_size=256)(

output [word_size-1:0] data_out,

input [word_size-1:0] data_in, address,

input clk, write);

reg [word_size-1:0] memory[memory_size-1:0];

assign data_out = memory[address];

always @ (posedge clk)

if (write) memory[address] <= data_in;

endmodule

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Processing Unit ModuleProcessing Unit ModuleProcessing Unit ModuleProcessing Unit Module

module Processing_Unit #(parameter word_size=8, op_size=4, Sel1_size=3, Sel2_size=2)(

output [word_size-1:0] instruction, address, Bus_1,

output Zflag,

input [word_size-1:0] mem_word,

input Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC,

input [Sel1_size-1:0] Sel_Bus_1_Mux,


input Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, clk, rst);

wire [word_size-1:0] Bus_2;

wire [word_size-1:0] R0_out, R1_out, R2_out, R3_out;

wire [word_size-1:0] PC_count, Y_value, alu_out;

wire alu_zero_flag;

wire [op_size-1:0] opcode = instruction[word_size-1:word_size-op_size];

module Processing_Unit #(parameter word_size=8, op_size=4, Sel1_size=3, Sel2_size=2)(

output [word_size-1:0] instruction, address, Bus_1,

output Zflag,

input [word_size-1:0] mem_word,

input Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC,



input Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, clk, rst);

wire [word_size-1:0] Bus_2;

wire [word_size-1:0] R0_out, R1_out, R2_out, R3_out;

wire [word_size-1:0] PC_count, Y_value, alu_out;

wire alu_zero_flag;


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Processing Unit ModuleProcessing Unit ModuleProcessing Unit ModuleProcessing Unit Module

Register_Unit R0 (R0_out, Bus_2, Load_R0, clk ,rst);




Register_Unit Reg_Y (Y_value, Bus_2, Load_Reg_Y, clk ,rst);

Register_Unit #(1) Reg_Z (Zflag, alu_zero_flag, Load_Reg_Z, clk ,rst);

Register_Unit Add_R (address, Bus_2, Load_Add_R, clk ,rst);

Register_Unit IR (instruction, Bus_2, Load_IR, clk ,rst);

Program_Counter PC (PC_count, Bus_2, Load_PC, Inc_PC, clk ,rst);

Multiplexer_5ch Mux_1 (Bus_1, R0_out, R1_out, R2_out, R3_out, PC_count, Sel_Bus_1_Mux);

Multiplexer_3ch Mux_2 (Bus_2, alu_out, Bus_1, mem_word, Sel_Bus_2_Mux);

Alu_RISC ALU (alu_out, alu_zero_flag, Bus_1, Y_value , opcode);

endmodule





Register_Unit Reg_Y (Y_value, Bus_2, Load_Reg_Y, clk ,rst);

Register_Unit #(1) Reg_Z (Zflag, alu_zero_flag, Load_Reg_Z, clk ,rst);

Register_Unit Add_R (address, Bus_2, Load_Add_R, clk ,rst);

Register_Unit IR (instruction, Bus_2, Load_IR, clk ,rst);

Program_Counter PC (PC_count, Bus_2, Load_PC, Inc_PC, clk ,rst);

Multiplexer_5ch Mux_1 (Bus_1, R0_out, R1_out, R2_out, R3_out, PC_count, Sel_Bus_1_Mux);

Multiplexer_3ch Mux_2 (Bus_2, alu_out, Bus_1, mem_word, Sel_Bus_2_Mux);

Alu_RISC ALU (alu_out, alu_zero_flag, Bus_1, Y_value , opcode);

endmodule

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Register Unit ModuleRegister Unit ModuleRegister Unit ModuleRegister Unit Module

module Register_Unit #(parameter word_size=8)(

output reg [word_size-1:0] data_out,

input [word_size-1:0] data_in,

input load, clk, rst);

always @ (posedge clk, negedge rst)

if (rst == 1'b0) data_out <= 0;

else if (load) data_out <= data_in;

endmodule

module Register_Unit #(parameter word_size=8)(

output reg [word_size-1:0] data_out,


input load, clk, rst);


if (rst == 1'b0) data_out <= 0;

else if (load) data_out <= data_in;

endmodule

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Program Counter ModuleProgram Counter ModuleProgram Counter ModuleProgram Counter Module

module Program_Counter #(parameter word_size=8)(

output reg [word_size-1:0] count,


input Load_PC, Inc_PC, clk, rst);


if (rst == 1'b0) count <= 0;

else if (Load_PC == 1'b1) count <= data_in;

else if (Inc_PC == 1'b1) count <= count+1;

endmodule

module Program_Counter #(parameter word_size=8)(

output reg [word_size-1:0] count,


input Load_PC, Inc_PC, clk, rst);


if (rst == 1'b0) count <= 0;

else if (Load_PC == 1'b1) count <= data_in;

else if (Inc_PC == 1'b1) count <= count+1;

endmodule

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Multiplexer ModulesMultiplexer ModulesMultiplexer ModulesMultiplexer Modules

module Multiplexer_5ch #(parameter word_size=8)(

output [word_size-1:0] mux_out,

input [word_size-1:0] data_a, data_b, data_c, data_d, data_e,

input [2:0] sel);

assign mux_out = (sel==0) ? data_a : (sel==1) ? data_b : (sel==2) ? data_c : (sel==3) ? data_d : (sel==4) ? data_e : 'bx;

endmodule



input [word_size-1:0] data_a, data_b, data_c,

input [1:0] sel);

assign mux_out = (sel==0) ? data_a : (sel==1) ? data_b : (sel==2) ? data_c : 'bx;

endmodule



input [word_size-1:0] data_a, data_b, data_c, data_d, data_e,

input [2:0] sel);

assign mux_out = (sel==0) ? data_a : (sel==1) ? data_b : (sel==2) ? data_c : (sel==3) ? data_d : (sel==4) ? data_e : 'bx;

endmodule



input [word_size-1:0] data_a, data_b, data_c,

input [1:0] sel);

assign mux_out = (sel==0) ? data_a : (sel==1) ? data_b : (sel==2) ? data_c : 'bx;

endmodule

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ALU ModuleALU ModuleALU ModuleALU Module

module Alu_RISC #(parameter word_size=8, op_size=4,

// opcodes

NOP = 4'b0000,

ADD = 4'b0001,

SUB = 4'b0010,

AND = 4'b0011,

NOT = 4'b0100,

RD = 4'b0101,

WR = 4'b0110,

BR = 4'b0111,

BRZ = 4'b1000)(

output reg [word_size-1:0] alu_out,

output alu_zero_flag,

input [word_size-1:0] data_1, data_2,

input [op_size-1:0] sel);

module Alu_RISC #(parameter word_size=8, op_size=4,

// opcodes

NOP = 4'b0000,

ADD = 4'b0001,

SUB = 4'b0010,

AND = 4'b0011,

NOT = 4'b0100,

RD = 4'b0101,

WR = 4'b0110,

BR = 4'b0111,

BRZ = 4'b1000)(

output reg [word_size-1:0] alu_out,

output alu_zero_flag,

input [word_size-1:0] data_1, data_2,

input [op_size-1:0] sel);

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ALU ModuleALU ModuleALU ModuleALU Module

assign alu_zero_flag = ~| alu_out;

always @(sel, data_1, data_2)

case(sel)

NOP: alu_out = 0;

ADD: alu_out = data_1 + data_2;

SUB: alu_out = data_1 - data_2;

AND: alu_out = data_1 & data_2;

NOT: alu_out = ~ data_2;

default: alu_out = 0;

endcase

endmodule

assign alu_zero_flag = ~| alu_out;

always @(sel, data_1, data_2)

case(sel)

NOP: alu_out = 0;

ADD: alu_out = data_1 + data_2;

SUB: alu_out = data_1 - data_2;

AND: alu_out = data_1 & data_2;

NOT: alu_out = ~ data_2;

default: alu_out = 0;

endcase

endmodule

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Control Unit ModuleControl Unit ModuleControl Unit ModuleControl Unit Module

module Control_Unit #(parameter word_size=8, op_size=4, state_size=4, src_size=2, dest_size=2, Sel1_size=3, Sel2_size=2)(

output [Sel2_size-1:0] Sel_Bus_2_Mux, output [Sel1_size-1:0] Sel_Bus_1_Mux,

output reg Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write,

input [word_size-1:0] instruction,

input zero, clk, rst);

// State Codes

parameter S_idle=0, S_fet1=1, S_fet2=2, S_dec=3, S_ex1=4, S_rd1=5,

S_rd2=6, S_wr1=7, S_wr2=8, S_br1=9, S_br2=10, S_halt=11;

// Opcodes

parameter NOP=0, ADD=1, SUB=2, AND=3, NOT=4, RD=5, WR=6, BR=7, BRZ=8;

// Sources and Destination Codes

parameter R0=0, R1=1, R2=2, R3=3;

module Control_Unit #(parameter word_size=8, op_size=4, state_size=4, src_size=2, dest_size=2, Sel1_size=3, Sel2_size=2)(

output [Sel2_size-1:0] Sel_Bus_2_Mux, output [Sel1_size-1:0] Sel_Bus_1_Mux,

output reg Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write,

input [word_size-1:0] instruction,

input zero, clk, rst);

// State Codes

parameter S_idle=0, S_fet1=1, S_fet2=2, S_dec=3, S_ex1=4, S_rd1=5,

S_rd2=6, S_wr1=7, S_wr2=8, S_br1=9, S_br2=10, S_halt=11;

// Opcodes

parameter NOP=0, ADD=1, SUB=2, AND=3, NOT=4, RD=5, WR=6, BR=7, BRZ=8;

// Sources and Destination Codes

parameter R0=0, R1=1, R2=2, R3=3;

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reg [state_size-1:0] state, next_state;

reg Sel_ALU, Sel_Bus_1, Sel_Mem;

reg Sel_R0, Sel_R1, Sel_R2, Sel_R3, Sel_PC;

reg err_flag;


wire [src_size-1:0] src= instruction[src_size+dest_size-1:dest_size];

wire [src_size-1:0] dest= instruction[dest_size-1:0];

// Mux selectors

assign Sel_Bus_1_Mux[Sel1_size-1:0]=Sel_R0?0:Sel_R1?1:Sel_R2?2:

Sel_R3?3:Sel_PC?4:3'bx;

assign Sel_Bus_2_Mux[Sel2_size-1:0]=Sel_ALU?0:Sel_Bus_1?1:Sel_Mem?2:2'bx;

always @(posedge clk, negedge rst) begin: State_transitions

if (rst==0) state<= S_idle; else state<=next_state; end

reg [state_size-1:0] state, next_state;

reg Sel_ALU, Sel_Bus_1, Sel_Mem;

reg Sel_R0, Sel_R1, Sel_R2, Sel_R3, Sel_PC;

reg err_flag;


wire [src_size-1:0] src= instruction[src_size+dest_size-1:dest_size];

wire [src_size-1:0] dest= instruction[dest_size-1:0];

// Mux selectors

assign Sel_Bus_1_Mux[Sel1_size-1:0]=Sel_R0?0:Sel_R1?1:Sel_R2?2:

Sel_R3?3:Sel_PC?4:3'bx;

assign Sel_Bus_2_Mux[Sel2_size-1:0]=Sel_ALU?0:Sel_Bus_1?1:Sel_Mem?2:2'bx;

always @(posedge clk, negedge rst) begin: State_transitions

if (rst==0) state<= S_idle; else state<=next_state; end

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always @(state, opcode, src, dest, zero) begin: Output_and_next_state

Sel_R0=0; Sel_R1=0; Sel_R2=0; Sel_R3=0; Sel_PC=0;

Load_R0=0; Load_R1=0; Load_R2=0; Load_R3=0; Load_PC=0; Inc_PC=0;

Load_IR=0; Load_Add_R=0; Load_Reg_Y=0; Load_Reg_Z=0; write=0;

Sel_Bus_1=0; Sel_ALU=0; Sel_Mem=0; err_flag=0;

next_state = state;

case (state)

S_idle: next_state = S_fet1;

S_fet1: begin

next_state = S_fet2;

Sel_PC = 1;

Sel_Bus_1=1;

Load_Add_R = 1;

end

always @(state, opcode, src, dest, zero) begin: Output_and_next_state

Sel_R0=0; Sel_R1=0; Sel_R2=0; Sel_R3=0; Sel_PC=0;

Load_R0=0; Load_R1=0; Load_R2=0; Load_R3=0; Load_PC=0; Inc_PC=0;

Load_IR=0; Load_Add_R=0; Load_Reg_Y=0; Load_Reg_Z=0; write=0;

Sel_Bus_1=0; Sel_ALU=0; Sel_Mem=0; err_flag=0;

next_state = state;

case (state)

S_idle: next_state = S_fet1;

S_fet1: begin


Sel_PC = 1;

Sel_Bus_1=1;

Load_Add_R = 1;

end

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S_fet2: begin next_state = S_dec;

Sel_Mem= 1;

Load_IR = 1;

Inc_PC=1; end

S_dec: case(opcode)

NOP: next_state = S_fet1;

ADD, SUB, AND: begin

next_state = S_ex1;

Sel_Bus_1 = 1;

Load_Reg_Y=1;

case (src)

R0: Sel_R0=1; R1: Sel_R1=1;

R2: Sel_R2=1; R3: Sel_R3=1;

default: err_flag=1; endcase

end

S_fet2: begin next_state = S_dec;

Sel_Mem= 1;

Load_IR = 1;

Inc_PC=1; end

S_dec: case(opcode)

NOP: next_state = S_fet1;

ADD, SUB, AND: begin

next_state = S_ex1;

Sel_Bus_1 = 1;

Load_Reg_Y=1;

case (src)

R0: Sel_R0=1; R1: Sel_R1=1;

R2: Sel_R2=1; R3: Sel_R3=1;


end

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NOT: begin

next_state = S_ex1;

Load_Reg_Z=1;

Sel_ALU=1;

case (src)

R0: Sel_R0=1; R1: Sel_R1=1;

R2: Sel_R2=1; R3: Sel_R3=1;


case (dest)

R0: Load_R0=1; R1: Load_R1=1;



end // NOT

NOT: begin

next_state = S_ex1;

Load_Reg_Z=1;

Sel_ALU=1;

case (src)

R0: Sel_R0=1; R1: Sel_R1=1;

R2: Sel_R2=1; R3: Sel_R3=1;


case (dest)




end // NOT

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RD: begin

next_state = S_rd1;

Sel_PC=1;

Sel_Bus_1 = 1;

Load_Add_R=1;

end // RD

WR: begin

next_state = S_wr1;

Sel_PC=1;

Sel_Bus_1 = 1;

Load_Add_R=1;

end // WR

RD: begin

next_state = S_rd1;

Sel_PC=1;

Sel_Bus_1 = 1;

Load_Add_R=1;

end // RD

WR: begin

next_state = S_wr1;

Sel_PC=1;

Sel_Bus_1 = 1;

Load_Add_R=1;

end // WR

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BR: begin

next_state = S_br1;

Sel_PC=1;

Sel_Bus_1 = 1;

Load_Add_R=1;

end // BR

BRZ: if (zero==1) begin

next_state = S_br1;

Sel_PC=1;

Sel_Bus_1 = 1;

Load_Add_R=1;

end

else begin


Inc_PC=1; end

BR: begin

next_state = S_br1;

Sel_PC=1;

Sel_Bus_1 = 1;

Load_Add_R=1;

end // BR

BRZ: if (zero==1) begin

next_state = S_br1;

Sel_PC=1;

Sel_Bus_1 = 1;

Load_Add_R=1;

end

else begin


Inc_PC=1; end

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default: next_state=S_halt;

endcase //opcode

S_ex1: begin

next_state=S_fet1;

Load_Reg_Z=1;

Sel_ALU=1;

case (dest)

R0: begin Sel_R0=1; Load_R0=1; end




default: err_flag=1;

endcase

end

default: next_state=S_halt;

endcase //opcode

S_ex1: begin

next_state=S_fet1;

Load_Reg_Z=1;

Sel_ALU=1;

case (dest)





default: err_flag=1;

endcase

end

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S_rd1: begin

next_state=S_rd2;

Sel_Mem=1;

Load_Add_R=1;

Inc_PC=1;

end

S_rd2: begin

next_state=S_fet1;

Sel_Mem=1;

case (dest)




end

S_rd1: begin

next_state=S_rd2;

Sel_Mem=1;

Load_Add_R=1;

Inc_PC=1;

end

S_rd2: begin

next_state=S_fet1;

Sel_Mem=1;

case (dest)




end

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S_wr1: begin

next_state=S_wr2;

Sel_Mem=1;

Load_Add_R=1;

Inc_PC=1;

end

S_wr2: begin

next_state=S_fet1;

write=1;

case (src)

R0: Sel_R0=1; R1: Sel_R1=1;

R2: Sel_R2=1; R3: Sel_R3=1;


end

S_wr1: begin

next_state=S_wr2;

Sel_Mem=1;

Load_Add_R=1;

Inc_PC=1;

end

S_wr2: begin

next_state=S_fet1;

write=1;

case (src)

R0: Sel_R0=1; R1: Sel_R1=1;

R2: Sel_R2=1; R3: Sel_R3=1;


end

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S_br1: begin

next_state=S_br2;

Sel_Mem=1;

Load_Add_R=1;

end

S_br2: begin

next_state=S_fet1;

Sel_Mem=1;

Load_PC=1;

end

S_halt: next_state=S_halt;

default: next_state=S_idle;

endcase

end

endmodule

S_br1: begin

next_state=S_br2;

Sel_Mem=1;

Load_Add_R=1;

end

S_br2: begin

next_state=S_fet1;

Sel_Mem=1;

Load_PC=1;

end

S_halt: next_state=S_halt;

default: next_state=S_idle;

endcase

end

endmodule

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RISC SPM Program ExecutionRISC SPM Program ExecutionRISC SPM Program ExecutionRISC SPM Program Execution

module test_RISC_SPM #(parameter word_size=8)();

reg rst;

wire clk;

reg [8:0] k;

Clok_Unit M1 (clk);

RISC_SPM M2 (clk, rst);

// define probes

wire [word_size-1:0] word0, word1, word2, word3, word4, word5, word6,

word7, word8, word9, word10, word11, word12, word13, word14,

word128, word129, word130, word131, word132, word133, word134,

word135, word136, word137, word138, word139, word140, word255;

module test_RISC_SPM #(parameter word_size=8)();

reg rst;

wire clk;

reg [8:0] k;

Clok_Unit M1 (clk);

RISC_SPM M2 (clk, rst);

// define probes

wire [word_size-1:0] word0, word1, word2, word3, word4, word5, word6,

word7, word8, word9, word10, word11, word12, word13, word14,

word128, word129, word130, word131, word132, word133, word134,

word135, word136, word137, word138, word139, word140, word255;

module Clock_Unit (output reg clock);parameter delay =0; parameter half_cycle=10;initial begin #delay clock=0; forever #half_cycle clock=~clock; endendmodule

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assign word0=M2.M2_MEM.memory[0], word1=M2.M2_MEM.memory[1],

word2=M2.M2_MEM.memory[2], word3=M2.M2_MEM.memory[3],













word140=M2.M2_MEM.memory[140];

assign word0=M2.M2_MEM.memory[0], word1=M2.M2_MEM.memory[1],














word140=M2.M2_MEM.memory[140];

1-34


initial #2800 $finish;

initial begin: Flush_Memory

#2 rst=0;

for (k=0; k<=255; k=k+1) M2.M2_MEM.memory[k]=0;

#10 rst=0;

end

initial begin: Load_program

#5 //opcode_src_dest

M2.M2_MEM.memory[0]=8'b0000_00_00; // NOP

M2.M2_MEM.memory[1]=8'b0101_00_10; // Read 130 to R2

M2.M2_MEM.memory[2]=130;





initial #2800 $finish;

initial begin: Flush_Memory

#2 rst=0;

for (k=0; k<=255; k=k+1) M2.M2_MEM.memory[k]=0;

#10 rst=0;

end

initial begin: Load_program

#5 //opcode_src_dest

M2.M2_MEM.memory[0]=8'b0000_00_00; // NOP







1-35




M2.M2_MEM.memory[9]=8'b0010_00_01; // Sub R1-R0 to R1

M2.M2_MEM.memory[10]=8'b1000_00_00; // BRZ


M2.M2_MEM.memory[12]=8'b0001_10_11; // Add R2+R3 to R3

M2.M2_MEM.memory[13]=8'b0111_00_00; // BR


// Load data

M2.M2_MEM.memory[128]=6; M2.M2_MEM.memory[129]=1;



M2.M2_MEM.memory[139]=8'b1111_00_00; // HALT

M2.M2_MEM.memory[140]=9; end

endmodule



M2.M2_MEM.memory[9]=8'b0010_00_01; // Sub R1-R0 to R1

M2.M2_MEM.memory[10]=8'b1000_00_00; // BRZ


M2.M2_MEM.memory[12]=8'b0001_10_11; // Add R2+R3 to R3

M2.M2_MEM.memory[13]=8'b0111_00_00; // BR


// Load data




M2.M2_MEM.memory[139]=8'b1111_00_00; // HALT

M2.M2_MEM.memory[140]=9; end

endmodule

1-36


1-37

Universal Asynchronous Receiver Universal Asynchronous Receiver Transmitter (UART)Transmitter (UART)Universal Asynchronous Receiver Universal Asynchronous Receiver Transmitter (UART)Transmitter (UART) Most computers and microcontrollers have one or

more serial data ports used to communicate with serial input/output devices

The serial communication interface, which receive serial data, is often called a UART (Universal Asynchronous Receiver-Transmitter)

One application of a UART is the modem (modulator-demodulator) that communicates via telephone lines

Most computers and microcontrollers have one or more serial data ports used to communicate with serial input/output devices

The serial communication interface, which receive serial data, is often called a UART (Universal Asynchronous Receiver-Transmitter)

One application of a UART is the modem (modulator-demodulator) that communicates via telephone lines

1-38

Universal Asynchronous Receiver Universal Asynchronous Receiver Transmitter (UART)Transmitter (UART)Universal Asynchronous Receiver Universal Asynchronous Receiver Transmitter (UART)Transmitter (UART) Features of UARTs

• Data (D) is transmitted one bit at a time

• When no data is being transmitted, D remains high

• To mark the transmission, D goes low for one bit time, which is referred to as the start bit

• When text is being transmitted, ASCII code is usually used

• ASCII is 7-bit in length the 8th bit is used for parity check

Features of UARTs • Data (D) is transmitted one bit at a time

• When no data is being transmitted, D remains high

• To mark the transmission, D goes low for one bit time, which is referred to as the start bit

• When text is being transmitted, ASCII code is usually used

• ASCII is 7-bit in length the 8th bit is used for parity check

1-39

Universal Asynchronous Receiver Universal Asynchronous Receiver Transmitter (UART)Transmitter (UART)Universal Asynchronous Receiver Universal Asynchronous Receiver Transmitter (UART)Transmitter (UART)

• After 8 bits are transmitted, D must go high for at least one bit time

• When receiving, the UART detects the start bit, receives the 8 data bits, and converts the data to parallel form when it detects the stop bit

• The UART must synchronize the incoming bit stream with the local clock

The number of bits transmitted per second is often referred to the BAUD rate

• After 8 bits are transmitted, D must go high for at least one bit time

• When receiving, the UART detects the start bit, receives the 8 data bits, and converts the data to parallel form when it detects the stop bit

• The UART must synchronize the incoming bit stream with the local clock

The number of bits transmitted per second is often referred to the BAUD rate

1-40

Block Diagram of a UARTBlock Diagram of a UARTBlock Diagram of a UARTBlock Diagram of a UART

1-41

UART TransmitterUART TransmitterUART TransmitterUART Transmitter

Input Signals:Load_XMT_datareg: assertion in state idle asserts Load_XMT_DR which loads Data_Bus into XMT_dataregByte Ready: assertion causes Load_XMT_shftreg to assert which loads contents of XMT_data into XMT_shftregT_byte: assertion initiates transmission of a byte of data including start, stop and parity bits.BC_lt_Bcmax: indicates status of bit counter Output Signals:Load_XMT_DR, Load_XMT_shftregStart: signals start of transmission by dropping XMT_shftreg[0] to 0Shift: directs XMT_shftreg to shift by one bit towards LSB and fill with stop bit 1Clear: clears bit_count

1-42

UART Transmitter ASMD ChartUART Transmitter ASMD ChartUART Transmitter ASMD ChartUART Transmitter ASMD Chart

1-43

UART Transmitter OperationUART Transmitter OperationUART Transmitter OperationUART Transmitter Operation

1-44

UART Transmitter ModuleUART Transmitter ModuleUART Transmitter ModuleUART Transmitter Module

module UART_XMTR #(parameter word_size=8)

output Serial_out,

input [word_size-1:0] Data_bus,

input Load_XMT_datareg, Byte_ready, T_byte, clock, rst_b);

Control_Unit M0 (Load_XMT_DR, Load_XMT_shftreg, start, shift, clear, Load_XMT_datareg, Byte_ready, T_byte, BC_lt_Bcmax, Clock, rst_b);

Datapath_Unit M1 (Serial_out, BC_lt_Bcmax, Data_Bus, Load_XMT_DR, Load_XMT_shftreg, start, shift, clear, Clock, rst_b);

endmodule

module UART_XMTR #(parameter word_size=8)

output Serial_out,

input [word_size-1:0] Data_bus,

input Load_XMT_datareg, Byte_ready, T_byte, clock, rst_b);

Control_Unit M0 (Load_XMT_DR, Load_XMT_shftreg, start, shift, clear, Load_XMT_datareg, Byte_ready, T_byte, BC_lt_Bcmax, Clock, rst_b);

Datapath_Unit M1 (Serial_out, BC_lt_Bcmax, Data_Bus, Load_XMT_DR, Load_XMT_shftreg, start, shift, clear, Clock, rst_b);

endmodule

1-45

UART Transmitter Datapath ModuleUART Transmitter Datapath ModuleUART Transmitter Datapath ModuleUART Transmitter Datapath Module

Datapath_Unit #(word_size=8, size_bit_count=3, all_ones={(word_size+1){1'b1}})(

output Serial_out, BC_lt_Bcmax,

input [word_size-1:0] Data_Bus,

input Load_XMT_DR, Load_XMT_shftreg, start, shift, clear, Clock, rst_b);

reg [word_size-1:0] XMT_datareg;

reg [word_size:0] XMT_shftreg;

reg [size_bit_count:0] bit_count;

assign BC_lt_Bcmax = (bit_count < word_size+1);

always @ (posedge Clock, negedge rst_b)

if (rst_b==0) begin

XMT_shftreg <= all_ones; bit_count<=0;

end

Datapath_Unit #(word_size=8, size_bit_count=3, all_ones={(word_size+1){1'b1}})(

output Serial_out, BC_lt_Bcmax,

input [word_size-1:0] Data_Bus,

input Load_XMT_DR, Load_XMT_shftreg, start, shift, clear, Clock, rst_b);

reg [word_size-1:0] XMT_datareg;

reg [word_size:0] XMT_shftreg;

reg [size_bit_count:0] bit_count;

assign BC_lt_Bcmax = (bit_count < word_size+1);


if (rst_b==0) begin

XMT_shftreg <= all_ones; bit_count<=0;

end

1-46

UART Transmitter Datapath ModuleUART Transmitter Datapath ModuleUART Transmitter Datapath ModuleUART Transmitter Datapath Module

else begin: Register_Transfers

if (Load_XMT_DR==1'b1) XMT_datareg<=Data_Bus;

if (Load_XMT_shftreg==1'b1) XMT_shftreg<={XMT_datareg,1'b1};

If (start==1'b1) XMT_shftreg[0]<=0;

If (clear==1'b1) bit_count <= 0;

If (shift==1'b1) begin

XMT_shftreg <= {1'b1, XMT_shftreg[word_size:1]};

bit_count <= bit_count+1;

end

end // Register_Transfers

endmodule

else begin: Register_Transfers

if (Load_XMT_DR==1'b1) XMT_datareg<=Data_Bus;

if (Load_XMT_shftreg==1'b1) XMT_shftreg<={XMT_datareg,1'b1};

If (start==1'b1) XMT_shftreg[0]<=0;

If (clear==1'b1) bit_count <= 0;

If (shift==1'b1) begin

XMT_shftreg <= {1'b1, XMT_shftreg[word_size:1]};

bit_count <= bit_count+1;

end

end // Register_Transfers

endmodule

1-47

UART Transmitter Control Unit ModuleUART Transmitter Control Unit ModuleUART Transmitter Control Unit ModuleUART Transmitter Control Unit Module

Control_Unit #(parameter one_hot_count=3, state_count=one_hot_count, size_bot_count=3, idle=3'b001, waiting=3'b010, sending=3'b100, all_one=9'1_111_111)(

output reg Load_XMT_DR, Load_XMT_shftreg, start, shift, clear,

input Load_XMT_datareg, Byte_ready, T_byte, BC_lt_Bcmax, Clock, rst_b);

reg [state_count-1:0] state, next_state;


if (rst_b==1’b0) state<= idle; else state<=next_state;

always @ (state, Load_XMT_datareg, Byte_ready, T_byte, BC_lt_Bcmax) begin

Load_XMT_DR=0; Load_XMT_shftreg=0; start=0; shift=0; clear=0;

next_state=idle;

Control_Unit #(parameter one_hot_count=3, state_count=one_hot_count, size_bot_count=3, idle=3'b001, waiting=3'b010, sending=3'b100, all_one=9'1_111_111)(

output reg Load_XMT_DR, Load_XMT_shftreg, start, shift, clear,

input Load_XMT_datareg, Byte_ready, T_byte, BC_lt_Bcmax, Clock, rst_b);

reg [state_count-1:0] state, next_state;


if (rst_b==1’b0) state<= idle; else state<=next_state;

always @ (state, Load_XMT_datareg, Byte_ready, T_byte, BC_lt_Bcmax) begin

Load_XMT_DR=0; Load_XMT_shftreg=0; start=0; shift=0; clear=0;

next_state=idle;

1-48

UART Transmitter Control Unit ModuleUART Transmitter Control Unit ModuleUART Transmitter Control Unit ModuleUART Transmitter Control Unit Module

case(state)

idle: if (Load_XMT_datareg==1'b1) begin

Load_XMT_DR=1; next_state=idle; end

else if (Byte_ready==1'b1) begin

Load_XMT_shftreg=1; next_state=waiting; end

waiting: if (T_byte==1'b1) begin

start=1; next_state=sending; end

else next_state=waiting;

sending: if (BC_lt_BCmax==1'b1) begin

shift=1; next_state=sending; end

else begin clear=1; next_state=idle; end

default: next_state=idle;

endcase

end

endmodule

case(state)

idle: if (Load_XMT_datareg==1'b1) begin

Load_XMT_DR=1; next_state=idle; end

else if (Byte_ready==1'b1) begin

Load_XMT_shftreg=1; next_state=waiting; end

waiting: if (T_byte==1'b1) begin

start=1; next_state=sending; end

else next_state=waiting;

sending: if (BC_lt_BCmax==1'b1) begin

shift=1; next_state=sending; end

else begin clear=1; next_state=idle; end


endcase

end

endmodule

1-49

UART Transmitter SimulationUART Transmitter SimulationUART Transmitter SimulationUART Transmitter Simulation

1-50

UART ReceiverUART ReceiverUART ReceiverUART Receiver

UART receiver receives serial bit stream of data, removes start bit and transfers data in parallel.

Transmitter’s clock is not available to receiver; data is not synchronized with receiver’s clock.

Issue of synchronization is resolved by generating a local clock at higher frequency to sample received data

Cycles of Sample_clock will be counted to ensure that data are sampled in middle of bit time.

UART receiver receives serial bit stream of data, removes start bit and transfers data in parallel.

Transmitter’s clock is not available to receiver; data is not synchronized with receiver’s clock.

Issue of synchronization is resolved by generating a local clock at higher frequency to sample received data

Cycles of Sample_clock will be counted to ensure that data are sampled in middle of bit time.

1-51

UART ReceiverUART ReceiverUART ReceiverUART Receiver

Sampling algorithm must:• Verify that a start bit has been received

• Generate samples from 8 bits of the data

• Load the samples data onto the local bus

Frequency of Sample_clock is 8 times of the frequency of the bit clock that transmitted the data.

Arrival of start bit is determined by detection of successive samples of value 0 after the serial input data goes low.

Three additional samples after the first 0 confirm that a valid start bit has arrived.

8 successive bits will be sampled at approximately the center of their bit.

Sampling algorithm must:• Verify that a start bit has been received

• Generate samples from 8 bits of the data

• Load the samples data onto the local bus

Frequency of Sample_clock is 8 times of the frequency of the bit clock that transmitted the data.

Arrival of start bit is determined by detection of successive samples of value 0 after the serial input data goes low.

Three additional samples after the first 0 confirm that a valid start bit has arrived.

8 successive bits will be sampled at approximately the center of their bit.

1-52

UART Receiver Block DiagramUART Receiver Block DiagramUART Receiver Block DiagramUART Receiver Block Diagram

Input Signals:read_not_ready_in: signals that host is not ready to receive dataSer_in_0: asserts while Serial_in is 0SC_eq_3: asserts while Sample_counter=3SC_lt_7: asserts while Sample_counter<7BC_eq_8: asserts while Bit_counter=8

Output Signals:read_not_ready_out: receiver received 8 bitsclr_Sample_counter: clears Sample_counterinc_Sample_counter: inc. Sample_counterclr_Bit_counter: clears Bit_counterinc_Bit_counter: inc. Bit_countershift: causes RCV_shftreg to shift towards LSBload: causes RCV_shftreg to transfre data to RCV_dataregError1: if host is not ready to receive data after last bit sampledError2: if stop bit is missing

1-53

UART Receiver ASMD ChartUART Receiver ASMD ChartUART Receiver ASMD ChartUART Receiver ASMD Chart

1-54

UART Receiver ModuleUART Receiver ModuleUART Receiver ModuleUART Receiver Module

module UART_RCVR #(parameter word_size=8, half_word=word_size/2)(

output [word_size-1:0] RCV_datareg,

output read_not_ready_out, Error1, Error2,

input Serial_in, read_not_ready_in, Sample_clk, rst_b);

Control_Unit M0 (read_not_ready_out, Error1, Error2, clr_Sample_counter, inc_Sample_counter, clr_Bit_counter, inc_Bit_counter, shift, load, read_not_ready_in, Ser_in_0, SC_eq_3, SC_lt_7, BC_eq_8, Sample_clk, rst_b);

Datapath_Unit M1 (RCV_datareg, Ser_in_0, SC_eq_3, SC_lt_7, BC_eq_8, Serial_in, clr_Sample_counter, inc_Sample_counter, clr_Bit_counter, inc_Bit_counter, shift, load, Sample_clk, rst_b);

endmodule

module UART_RCVR #(parameter word_size=8, half_word=word_size/2)(

output [word_size-1:0] RCV_datareg,

output read_not_ready_out, Error1, Error2,

input Serial_in, read_not_ready_in, Sample_clk, rst_b);

Control_Unit M0 (read_not_ready_out, Error1, Error2, clr_Sample_counter, inc_Sample_counter, clr_Bit_counter, inc_Bit_counter, shift, load, read_not_ready_in, Ser_in_0, SC_eq_3, SC_lt_7, BC_eq_8, Sample_clk, rst_b);

Datapath_Unit M1 (RCV_datareg, Ser_in_0, SC_eq_3, SC_lt_7, BC_eq_8, Serial_in, clr_Sample_counter, inc_Sample_counter, clr_Bit_counter, inc_Bit_counter, shift, load, Sample_clk, rst_b);

endmodule

1-55

UART Receiver Datapath Unit ModuleUART Receiver Datapath Unit ModuleUART Receiver Datapath Unit ModuleUART Receiver Datapath Unit Module

module Datapath_Unit #(parameter word_size=8, half_word=word_size/2, Num_counter_bits=4)(

output reg [word_size-1:0] RCV_datareg,

output Ser_in_0, SC_eq_3, SC_lt_7, BC_eq_8,

input Serial_in, clr_Sample_counter, inc_Sample_counter, clr_Bit_counter, inc_Bit_counter, shift, load, Sample_clk, rst_b);

reg [word_size-1:0] RCV_shftreg;

reg [Num_counter_bits-1:0] Sample_counter;

reg [Num_counter_bits:0] Bit_counter;

assign Ser_in_0 = (Serial_in==1'b0);

assign BC_eq_8 = (Bit_counter == word_size);

assign SC_lt_7 = (Sample_counter < word_size-1);

assign SC_eq_3 = (Sample_counter == half_word-1);

module Datapath_Unit #(parameter word_size=8, half_word=word_size/2, Num_counter_bits=4)(

output reg [word_size-1:0] RCV_datareg,

output Ser_in_0, SC_eq_3, SC_lt_7, BC_eq_8,

input Serial_in, clr_Sample_counter, inc_Sample_counter, clr_Bit_counter, inc_Bit_counter, shift, load, Sample_clk, rst_b);

reg [word_size-1:0] RCV_shftreg;

reg [Num_counter_bits-1:0] Sample_counter;

reg [Num_counter_bits:0] Bit_counter;

assign Ser_in_0 = (Serial_in==1'b0);

assign BC_eq_8 = (Bit_counter == word_size);

assign SC_lt_7 = (Sample_counter < word_size-1);

assign SC_eq_3 = (Sample_counter == half_word-1);

1-56

UART Receiver Datapath Unit ModuleUART Receiver Datapath Unit ModuleUART Receiver Datapath Unit ModuleUART Receiver Datapath Unit Module

always @ (posedge Sample_clk)

if (rst_b==1'b0) begin

Sample_counter <=0; Bit_counter<=0; RCV_datareg<=0;

RCV_shftreg<=0; end

else begin

if (clr_Sample_counter == 1) Sample_counter<=0;

else if (inc_Sample_counter == 1)

Sample_counter <= Sample_counter+1;

if (clr_Bit_counter == 1) Bit_counter<=0;

else if (inc_Bit_counter == 1)

Bit_counter <= Bit_counter+1;

if (shift) RCV_shftreg <= {Serial_in, RCV_shftreg[word_size-1:1]};

if (load) RCV_datareg <= RCV_shftreg ;

end

endmodule


if (rst_b==1'b0) begin

Sample_counter <=0; Bit_counter<=0; RCV_datareg<=0;

RCV_shftreg<=0; end

else begin

if (clr_Sample_counter == 1) Sample_counter<=0;

else if (inc_Sample_counter == 1)

Sample_counter <= Sample_counter+1;

if (clr_Bit_counter == 1) Bit_counter<=0;

else if (inc_Bit_counter == 1)

Bit_counter <= Bit_counter+1;

if (shift) RCV_shftreg <= {Serial_in, RCV_shftreg[word_size-1:1]};

if (load) RCV_datareg <= RCV_shftreg ;

end

endmodule

1-57

UART Receiver Control Unit ModuleUART Receiver Control Unit ModuleUART Receiver Control Unit ModuleUART Receiver Control Unit Module

module Control_Unit #(parameter word_size=8, half_word=word_size/2, Num_state_bits=2, idle=2'b00, starting=2'b01, receiving=2'b10)(

output reg read_not_ready_out, Error1, Error2, clr_Sample_counter, inc_Sample_counter, clr_Bit_counter, inc_Bit_counter, shift, load,

input read_not_ready_in, Ser_in_0, SC_eq_3, SC_lt_7, BC_eq_8, Sample_clk, rst_b);

reg [Num_state_bits-1:0] state, next_state;


if (rst_b==1'b0) state <= idle; else state <= next_state;

module Control_Unit #(parameter word_size=8, half_word=word_size/2, Num_state_bits=2, idle=2'b00, starting=2'b01, receiving=2'b10)(

output reg read_not_ready_out, Error1, Error2, clr_Sample_counter, inc_Sample_counter, clr_Bit_counter, inc_Bit_counter, shift, load,

input read_not_ready_in, Ser_in_0, SC_eq_3, SC_lt_7, BC_eq_8, Sample_clk, rst_b);

reg [Num_state_bits-1:0] state, next_state;


if (rst_b==1'b0) state <= idle; else state <= next_state;

1-58


always @ (state, Ser_in_0, SC_eq_3, SC_lt_7, read_not_ready_in) begin

read_not_ready_out=0; Error1=0; Error2=0; clr_Sample_counter=0; inc_Sample_counter=0 ; clr_Bit_counter=0; inc_Bit_counter=0; shift=0; load=0;

next_state = idle;

case (state)

idle: if (Ser_in_0==1'b1) next_state=starting;

else next_state=idle;

starting: if (Ser_in_0==1'b0) begin

next_state=idle;

clr_Sample_counter=1;

end else

always @ (state, Ser_in_0, SC_eq_3, SC_lt_7, read_not_ready_in) begin

read_not_ready_out=0; Error1=0; Error2=0; clr_Sample_counter=0; inc_Sample_counter=0 ; clr_Bit_counter=0; inc_Bit_counter=0; shift=0; load=0;

next_state = idle;

case (state)

idle: if (Ser_in_0==1'b1) next_state=starting;

else next_state=idle;

starting: if (Ser_in_0==1'b0) begin

next_state=idle;


end else

1-59


if (SC_eq_3==1'b1) begin

next_state=receiving;


end else begin

next_state=starting;

inc_Sample_counter=1;

end

receiving: if (SC_lt_7==1'b1) begin



end else begin


if (SC_eq_3==1'b1) begin



end else begin

next_state=starting;


end

receiving: if (SC_lt_7==1'b1) begin



end else begin


1-60


if (!BC_eq_8) begin


inc_Bit_counter=1; shift=1;

end else begin

next_state=idle; clr_Bit_counter=1;

read_not_ready_out=1;

if (read_not_ready_in==1'b1) Error1=1;

else if (Ser_in_0==1'b1) Error2=1;

else load=1;

end

end


endcase

end

endmodule

if (!BC_eq_8) begin


inc_Bit_counter=1; shift=1;

end else begin

next_state=idle; clr_Bit_counter=1;

read_not_ready_out=1;

if (read_not_ready_in==1'b1) Error1=1;

else if (Ser_in_0==1'b1) Error2=1;

else load=1;

end

end


endcase

end

endmodule

1-61

UART Receiver Simulation UART Receiver Simulation UART Receiver Simulation UART Receiver Simulation

1-62

UART Receiver Simulation UART Receiver Simulation UART Receiver Simulation UART Receiver Simulation

Documents

COE 405 Design and Synthesis of DataPath Controllers Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals