Co-optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement

Co-optimization of Memory BIST Grouping,

Test Scheduling, and Logic Placement

Andrew B. Kahng and Ilgweon Kang VLSI CAD LABORATORY, UC San Diego

Design, Automation & Test in Europe March 26th, 2014

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Outline

• Motivation and Contributions• Related Works• ILP Formulation• Heuristic Flow• Experimental Results• Conclusions and Future Work

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Motivation• Memory built-in self-test (MBIST)

– Essential DFT technique in modern SOCs– MBIST design impacts chip resources and quality of test solution– Physical optimizations of MBIST logic: not well-studied

MEM MEM

MEM MEM

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MEM

MEM

MEMMEM

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MEM

BISTBIST

BISTBIST

BIST

TAP

Memory BIST Architecture

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Challenges and Contributions• Challenge: Multiple optimization criteria

– Minimize test time– Minimize number of BIST controllers– Minimize wirelength between BIST logic and memories

• Our work: Three-stage heuristic– Memory partitioning : FM in a weighted hypergraph model– Test scheduling : Integer Linear Program (ILP) formulation– MBIST logic placement : min-weight maximum matching

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Outline


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Related Works• Test scheduling

– Reduction of test time is a fundamental goal in DFT– Typical: scheduling as rectangle packing– Also typical: scheduling as ILP

• Design optimizations for memory BIST controllers– Most works focus on architectural and testing aspects– Chien et al. [2009] propose a memory BIST design optimization

• ILP for clustering of memories to controllers• Studies physical design aspects • Various simplifications: all of a cluster is tested in parallel, no

two clusters tested simultaneously, …

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Outline


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ILP Formulation

• Objective: Minimize test end time• Subject to: Upper bound on test power

• Logical constraints capture parallel and serial testing scenarios

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pow

er

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MEM1MEM2 MEM4

time

Test power limit

Improved test time is possible

Red

uce

d t

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tim

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MBI

ST1

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ST2

pow

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time

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Test power limit

Test time with one solution

MBIST1

MBIST2

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Outline


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Overall Flow

Input: Memories, Constraints

(1) Memory Partitioning with Hypergraph (MLPart [1], FM-style)

(2) Test Scheduling with ILP formulation(CPLEX [2], logical constraints)

(3) Placement of BIST Logic for each Partition ([3], Min-Weight Max-Cardinality Matching)

Output: Memory BIST Groups, Test Schedules, BIST Logic Placements

[1] MLPart. http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Partitioning/MLPart[2] IBM ILOG CPLEX Optimizer. http://www.ilog.com/products/cplex[3] Hungarian algorithm source code. http://www.informatik.uni-freiburg.de/~stachnis/index.html

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Memory Partitioning• Divide memories into k partitions using MLPart

– MLPart: Min-cut hypergraph partitioner based on multilevel FM – k = number of BIST controllers

• Hypergraph: vertices = memories; hyperedge weights reflect test time implications of grouping– Reduced test time if memories with same shape and depth in same group

Example Hypergraph

MEM MEM MEM

MEM

MEM MEM MEM

MEM

Hyperedges: The same shape, depth and test power, respectivelyEdges: Distances < D1, < avg(D1, D2) and < D2, respectively (where D1 < D2)

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Test Scheduling• Solve ILP formulation

– Minimize test time, subject to power constraint– ILP solver: CPLEX Optimizer 12.5.1

• Additional partition (BIST controller) for better test time– Obtain alternative test scheduling solution with extra BIST controller

• {1 BIST controller, 2 BIST controllers} per each partition

Solution with one BIST controller Solution with two BIST controllers

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BIST1

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Est. Test Time 1000

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MEMBIST2

Est. Test Time 900

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Memory BIST Logic Placement• To minimize wirelength between

each BIST and memories• Min-weight maximum-cardinality

matching in a bipartite graph– Apply Hungarian algorithm – Cost: Diameter from a grid to

all memories in a group

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MEMMEM

MEMMEM

MEM

MEMMEM

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Memories in the same BIST group

Possible grids for BIST logic placement

Forbidden grids (intersection with memories)

BIST placement solution

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Outline


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Experimental Setup• Develop MBIST-solver to implement our heuristics

– C++ / g++ 4.8.0– User options include min/max # partitions, min/max # memories in a

partition, max diameter, power constraint, weight parameters, …– MLPart: Memory partitioner– CPLEX 12.5.1: ILP solver

• Testcases: six industrial testcases (from industry partners)

TC #M #P DMAX

TC1 143 13 3900

TC2 150 11 4500

TC3 124 8 2200

TC4 160 13 3400

TC5 137 7 3200

TC6 148 12 4100

TC = testcaseM = #memoriesP = #partitionsDMAX = maximum diameter w/o BIST [μm]

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Our solutions1. Reduce test time by up to 11.57% (Testcase 3)2. Reduce number of BIST controllers by up to 41.6% (Testcase 6)3. Reduce maximum diameter by up to 31.7% (Testcase 6)

Experimental Results

Industrial solution (TC1)• Test time = 1067• # BISTs = 13• Maximum Diameter = 3900μm

Our solution (TC1)• Test time = 969• # BISTs = 12• Maximum Diameter = 2100μm

memories

BIST controller

Large Maximum Diameter Smaller Maximum Diameter

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Outline


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Conclusions and Future Work• Three-step heuristic methodology

– Co-optimization of (1) Memory BIST grouping, (2) test scheduling, and (3) memory BIST logic placement

– Objective: minimize test time for a given #BIST controllers• Handle various serial / parallel testing options in ILP• Minimize diameter of BIST groups less-critical timing, less

need for LVT instances in BIST implementation, etc.

• Future work– Integrate these optimizations into ‘production’ PD flow– Improve hypergraph weighting, scalability of ILP– Improve congestion- and timing-awareness of BIST placement

Thank You!

Documents

Co-optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement