CMOS Today & Tomorrow - spectronet.despectronet.de/...2014/140522_machine_vision_technology_forum/...dal… · Multi-Slope •Rarely outside of research projects •Often shows linearity

CMOS Today & Tomorrow

Uwe Pulsfort

TDALSA Product & Application Support

Teledyne DALSA Confidential and Proprietary

Overview

• Image Sensor Technology Today

• Typical Architectures

• Pixel, ADCs & Data Path

• Image Quality

• Image Sensor Technology Tomorrow

• Architecture Outlook

• Image Quality Outlook

• BSI


CMOS Image Sensor Technology

Today


Image Sensor Architecture - Line

• Pixel Design

• partially Pinned Photo Diode

• Rolling Shutter with CDS

• High Resolution possible with large pixels

• Capable of a few rows only

• Analog Path

• Correlated Double Sampling

• Stand-Alone ADCs

• 12bit, ~50MSps

• High power consumption

• Digital Path

• Serial Data

• LVDS up to 480Mbps per lane

• ~ 40 Mpix/s per lane (2 Pins)

• All Controls on-chip

Column Support Circuits

(BIAS, S&H, etc.)

Column Support Circuits

(BIAS, S&H, etc.)

Horizontal Read Rails

Shift Registers

CDS CDS CDS CDS

ADC ADC ADC ADC

O/F O/F O/F O/F

Horizontal Read Rails

Shift Registers

CDS CDS CDS CDS

ADC ADC ADC ADC

O/F O/F O/F O/F

Timing Core

Temp

SensorPLL

Timing Core

Temp

SensorPLL

Pixel Array Dual Line

7.04um square pixels

• Example Models:

• P4 Series (2k - 16k Resolution)

• Multi-Line Colour sensors


Image Sensor Architecture - Area

• Example Models:

• FALCON 4M60 / 1.4M100, FALCON 2 12M58

• GENIE HM, GENIE TS

• Pixel Design

• Pinned Photo Diode

• Global Shutter

• No or limited CDS

• High Resolution small pixel

• Analog Path

• Gain, Double Sampling

• Column-wise ADC

• 8-11bit, 5-10ms per row

• Digital Path

• Parallel

• LVDS up to 480Mpix per tap

• All Controls on-chip

Clock Generation

Digital Timing Generation

Ro

w D

eco

de

r a

nd

Ro

w D

rive

rsImage Region

Iso

latio

n C

olu

mn

s

Iso

latio

n C

olu

mn

s

Isolation Rows

Isolation & Dark Rows

SPI

MCLK

test pattern

ROI address

row address

Image Array Voltage buffers

Analog Processing

ADC

DATA PATH

10bit

LVDS I/O

COL [0]

EXSYNC

LV

AL

FV

AL

ST

RO

BE

User Optimize

Ramp Generation

Bias Generation

Data Read-Back

ROW [0]


Some Details - Pixel


CMOS Pixel Structures

RSEL

VDDI

CO

L

I

PPD

RRST

3T

RSEL

VDDI

CO

L

I

TG

PPD FD

RRST

4T

5T

RSEL

VDDI

CO

L

I

PRST

TG

PPD FD

RRST

Multi-T


CMOS Pixel Selection

Pixel Features

3-Transistor • Best Fill Factor, high Saturation, simple Architecture

• Elektronic Global Shutter not possible

• Limited possibilities for Adaptation (FW, CCE, NEE, …)

4-Transistor • Rolling Shutter with CDS (low noise)

• Global Shutter without CDS and without Exposure Control

• Better Fill Factor, good saturation level

5-Transistor • “stop action” function comparable to CCD ILT

• Global Shutter with Exposure Control possible

• Good Fill Factor, good saturation level

Multi-T • Many Ideas, few products with 6, 7, 8 or more transistors

• Lowest Fill Factor, lowest saturation level

• Main Goal: Global Shutter with CDS (low noise)

• Pixel determines Basic Function & Capability of System

8


Some Details - ADC


CMOS Image Sensor - ADC Selection

ADC Status

Single Slope • Commonly used (various Models), 10-14bit

• No Linearity issues, low power consumption (up to ~Gbps)

• Low complexity, allows narrow column pitch

• Conversion rate limited by linear Ramp and counter

Successive

Approximation /

Algorithmic

• Best candidate for 2nd place in Image Sensors

• Potential to reach lowest power consumption

• Requires complex circuitry within a column

• Very tight connection between: column pitch, power, bit depth and bit

rate - specifications need to be traded-off against each other

Multi-Slope • Rarely outside of research projects

• Often shows linearity issues between coarse and fine steps

Sigma Delta • Rare in the past, gaining with increasing bit depth and bit rate

• Very fast, with oversampling; enables high bit depth and rate

• Requires complex analog an digital circuitry

• High power consumption and complicated column construction

11


Some Details - Outputs


CMOS Outputs

Output Status

Analog • Standard in CCD and older CMOS, today in special cases

• 50-80 Mpix/s/pin, ADC components in camera

CMOS I/O • Typical for communication with Sensor

• Slow (and today rare) to output data, 5-10 Mpix/s/pin

LVDS / Sub-LVDS • Typical Data Format, sometimes also for communication

• Hardware Layer of the CameraLink Standard

• ~30mW/lane (10mW/lane), 20-60 Mpix/s/lane, fully digital, robust

SerDes • Computer Standard today: CPU, memory, SATA, PCIx,…

• Hardware Layer of the CLHS Standards (FALCON2, P4)

• ~10mW/lane, 80-250 Mpix/s/lane, fully digital, robust

• No application in CMOS Image sensors as yet

• Digital data rate influences Line Rate and power consumption

13


CMOS in Imaging...

• Enables higher Integration

• ADC, biasing, controls integrated in chip

• Programmable, self or single-trigger Operation

• Delivers higher Speed

• Fast ADCs and/or highly parallel Processes

• High digital Data rates with low power consumption

• Offer extended Functionality

• Integration Control: Global Shutter, Exposure Control

• Frame-to-Frame Functions: Windowing, Gain, Resolution, ...

• Application Adaptation: Bit depth, Snap Shot Mode, ...

• Special functions: Wide Dynamic Range, shutter modes, ...


Image Quality


~10ke- SAT

Signal: ~ 7.00ke-

Background: ~ 4.00ke-

Contrast: 54% SNR: ~70

Good readability with 4x Gain

Between Saturation and Noise

• Reduce Noise

• Global Shutter ~10 e- desirable

• Today ~1/1000 FW (DNR 60dB)

~10ke- SAT

Signal: ~ 5.25ke-

Background: ~ 4.25ke-

Contrast: 21% SNR: ~10

Despite 4x Gain SNR in dark regions is too

low - noise needs to be reduced

~40ke- SAT

Good image content, but Display-DNR

hinders readability

Bright spots saturated -

Higher FW required

• Full Well - maintain or increase

• 30-40ke- desirable

Future Technologie needs to:


Sensitivity

• number of photons is limited by system

• Sensor should capture all photons

• Fill Factor (FF) measures “photons available per pixel”

• Also influences acceptance angle, colour reproduction and MTF

• Sensor needs to convert all photons into electrons

• Quantum Efficiency (QE) measures “photons converted per pixel”

• Silicon property, can be influenced through process technology

• Wavelength dependent

• Typical Spec is “eff. QE”, measured as FF*QE

• Goal: More Electrons per Pixel with same Lighting


Optisches Pixel Design

electrical

layers

optical layers

Wafer and Photodiode

Acceptance Angle Fill Factor

electrical

layers

optical layers

microlens

Wafer and Photodiode


Outside the visual Spectrum

• Typical QE (e.g. TD Falcon2)

• Monochrome vs. Colour

• Infrared Capture

• Silicon up to ~1100nm

• “Thick-EPI” Wafer Material

• NIR and VIS filter layers

• UV Capture < 400nm

• UV-transparent Coverglass

• Special process steps 0.0%

5.0%

10.0%

15.0%

20.0%

25.0%

250 275 300 325 350 375 400

QE

[%

]

Wavelength (nm)

UV Erfassung

SPEZ

STD

e.g. IR

Enhanced


CMOS Image Sensor Technology

Tomorrow


The Future Architecture - I

Merging Development

• Shorter Pixel-to-Digital Path

• Reduced Noise with same functionality (e.g. Gain)

• 12bit Column ADC with ~1 MSps, ~12bit DNR

• Serial High-Speed Outputs

• Up to 3 Gbps - 250 Mpix/s per Pin, 8b/10b encoding

Line Scan Area Scan • Cost Efficient 1-Line

• Fast Multi-Line (> 4n)

• Higher Sensitivity

• TDI-Capability

• High Colour Quality

• Line Rates above 100 kHz

• Smaller Pixel (1-4 mm)

• Highest Resolution, lowest $/Mpix

• Trade-Offs in FW, NEE

• Larger Pixel (4-8 mm)

• Increasing Resolution (>12M)

• FW remains, reduced noise

• Frame Rates with 2+ GPix/s


The Future of Image Quality

• Area & Linescan Sensors: Reduced Noise

• Direct Pixel-to-ADC and Column-wise ADC Technology

• CDS Technology

• Also: High Full Well, Higher Resolution, High Fill Factor

• Multi-Line Sensors: Higher Sensitivity

• More Rows per Pixel TDI Principle

• Special Applications:

• Colour Linescan with n rows per colour or m colours

• Wide Dynamic Range

• High Full Well, reduced noise higher Dynamic Range

• Higher Fill Factor (e.g. Back-Side Illumination (BSI))


BSI Back-Side Illumination

• Back-Side Illumination

• Wafer thinned to mm

• Readout at front-side

• Advantages

• High Fill Factor (no circuitry in light path)

• High QE (Stack optimized for optics, not electronics)

• More space in pixel for circuitry

• Technology increasingly available

• Wafer Thinning & Treatment for CCD and CMOS

• Optimization of specialized processes

• Still expensive, but increasing availability will reduce cost

Std. Wafer Ausgedünnter Wafer

e

Elektrisch Aktive Pixel ohne Einfluß

auf Lichtpfad

e

Optisch & Elektrisch Aktive Pixel

reduzieren Füll Faktor


Thank You for your

Attention!

Questions ?

Reducing the cost

of products we use

everyday

Inspecting electronic

components

Documents

CMOS Today & Tomorrow - spectronet.despectronet.de/...2014/140522_machine_vision_technology_forum/...dal… · Multi-Slope •Rarely outside of research projects •Often shows linearity