CMOS Technology for Computer Architectsusers.ics.forth.gr/~jacob/cmos4arch/handouts/lec6_1pp.pdf · HDL Synopsys NCVlog activity(f) netlist & constr. netlist & delays ... sdf/sdc

Iakovos MavroidisGiorgos Passas

Manolis Katevenis

GREECE FORTH−ICS / EURECCA & UoC

CMOS Technology for Computer Architects

Lecture 6: Project & EDA Tutorial

Outline

CMP Overview

Course Project

EDA Flow

Technology Files

Giorgos Passas, FORTH−ICS, Spring 2012

DDR Controller

DDR Controller

MAC

MAC

PCIe

PCIe

DDR DDR

DDR DDR

MAC

PHY

PCIe

XAUI

Chip Multiprocessor Overviewtop level

1

- 90nm...20nm CMOS - 100s sq-mm - 10s Watts

- DRAM & IO interfaces - 10s Gb/s

- Tiles - 10s MB SRAM - 100s processors - 10s Tb/s network


P

M

M

North

South

West East

Chip Multiprocessor Overviewtile

2

- Processor - 1/4 x tile - RISC? VLIW?

- Cache Memory - 3/4 x tile - how many levels?

- Network - 1/10 x tile - topology? flow ctrl?


South

North

localhost

crossbarWest

East

Chip Multiprocessor Overviewcrosspoint

3

- 2D Mesh

- NEWS Routing - dimension ordered

- Buffered Flow Control - credits

www.csd.uoc.gr/~hy534


P

M

M

South

West East

Chip Multiprocessor Overviewtile

4

- Processor - 1/4 x tile - RISC? VLIW?

- Cache Memory - 3/4 x tile - how many levels?

- Network - 1/10 x tile - topology? flow ctrl?

cmos4arch LEC. 6 - 14:

NETWORK & MEMORY design


all−to−one commun all−to−all communone−to−one commun

part 1: part 2: part 3:

xbar &sched.

mux &arbiter

why wires are a problem power optimizations realistic interconnect

5

Course Projectoverview

part 4: CMP simulation for xbar power analysis


ediNetelectronic design for interconnection Networks

6

32x32x24Gb/s design point

- EDA environment I developed in my PhD

- Custom placement- Standard automatic routing - route wires, not packets- Standard extract RC

- Library of network elements - tile, wire, mux, xbar, buffer, ...

- Parameterized scripts - automatic configuration


A CB

outin

1 whi le ( )2 c l k = c lk +1;3

4 C = B;5

6 B = A;7

8 f s c a n f (A) ;9

10 f p r i n t f (C) ;

1 always@ ( posedge c l k )2 i = in ;3

4 always@ ( posedge c l k )5 out = i ;6

7 always@ ( posedge c l k )8 $d i sp lay ( out ) ;

7

EDA Flowcircuit example

structural verilog means "think HW"


CV f

.vcd

.vHDL

CadenceCadenceSOC EncounterDesign Compiler(structural)

HDL SynopsysNCVlog

netlist.v .v

netlist

activity (f)

RC2

syn simpnrsrc

ewire

8

EDA Flow

tool


1 module ewire ( in , c lk , out ) ;2 input in , c l k ;3 output out ;4 reg i , out ;5

6 always@ ( posedge c l k )7 i = in ;8

9 always@ ( posedge c l k )10 out = ibu f ;11

12 endmodule

1 module ewire ( in , c lk , out ) ;2 input in , c l k ;3 output out ;4 wire i ;5

6 DFQD1 i r e g ( .D( in ) ,7 .CP( c l k ) , .Q( i ) ) ;8

9 DFQD1 out reg ( .D( i ) ,10 .CP( c l k ) , .Q( out ) ) ;11

12 endmodule

9

EDA Flowverilog files (src -> syn)

compile

(tech mapping)


optimization needstopographical information

?

10

EDA Flow

verilog files (syn -> pnr)


1 module ewire ( in , c lk , out ) ;2 input in , c l k ;3 output out ;4 wire i ;5


9

10

11

12

13

14

15 DFQD1 out reg ( .D( i ) ,16 .CP( c l k ) , .Q( out ) ) ;17 endmodule

1 module ewire ( in , c lk , out ) ;2 input in , c l k ;3 output out ;4 wire i , i b u f // . . .5


9 CKND6 FE OFC13 i ( . I ( i ) ,10 .ZN(FE OFN13 i ) ) ;11 // . . .12

13

14 DFQD1 out reg (15 .D(FE OFN16 i ) ,16 .CP( c l k ) , .Q( out ) ) ;17 endmodule

11

EDA Flowverilog files (syn -> pnr)

optDesign

(restructuring, buffer insertion)


1 module tbench ;2 reg in , c l k ;3 wire out ;4

5 ewire EWIRE( in , c lk , out ) ;6

7 i n i t i a l8 $dumpfi le ( ” ewire . vcd” ) ;9 in <= 0 ;

10 c l k = 0 ;11 f o r ev e r12 #50 c l k = ˜ c l k ;13

14 always @ ( posedge c l k )15 #2 in <= ˜ in ;16 endmodule

12

EDA Flowverilog files (pnr -> sim)

pnr netlist

value change dump


CV f

.vcd

.vHDL

CadenceCadenceSOC EncounterDesign Compiler(structural)

HDL SynopsysNCVlog

activity(f)

netlist & delaysnetlist & constr..v & .sdc.v

RC

& .sdf

2

syn simpnrsrc

ewire

13

EDA Flow

sdf/sdc files


1 (CELL2 (CELLTYPE ” ewire ” )3 (INSTANCE)4 (DELAY5 (ABSOLUTE6 (INTERCONNECT FE OFC13 i/Z out reg /D

( 0 . 2 0 1 : : 0 . 2 0 1 ) ( 0 . 1 9 9 : : 0 . 1 9 9 ) )

1 s e t sd c v e r s i on 1 .82

3 s e t u n i t s −time ns −r e s i s t a n c e kOhm −capac i t ance pF−vo l tage V −cu r r en t mA

4

5 c r e a t e c l o c k [ g e t p o r t s c l k ] −per iod 1

14

EDA Flowsdf/sdc files

sdf - standard delay format (pnr -> sim)

sdc - synopsys design constraints (syn -> pnr)

1GHz


1 s e t t a r g e t l i b r a r y $EDI TSYNLIB2

3 analyze −format v e r i l o g $EDI CPATHSRC/$EDI CTOP. v4 e l abo r a t e $EDI CTOP5

6 c r e a t e c l o c k c l k −per iod $EDI CDELAY7

8 s e t d r i v i n g c e l l − l i b c e l l $EDI CINR $in9 s e t l o ad $EDI COUTC $out

10

11 compile12 r ep o r t t im ing13 r ep o r t a r e a14

15 wr i t e −format v e r i l o g −output $EDI CPATHSYN/$EDI CTOP. v16 wr i t e sd c $EDI CTOP. sdc

15

EDA Flowdesign compiler script (tcl)

.db tech file

syntax check & tech indy mapping

opt for speed

tech mapping & opt


1 s e t l e f f i l e $EDI TPNRLIBLEF2

3 s e t t ime l i b $EDI TPNRLIBLIB4

5 s e t n e t l i s t $EDI CPATHSYN/$EDI CTOP. v6 s e t t im i n g c on f i l e $EDI CTOP . sdc7

8 commitConfig9

10 setMultiCpuUsage −localCpu 211

12 loadFPlan $EDI CTOP. fp13

14 l o a d I oF i l e $EDI CTOP. i o15

16 r e s t o r eP l a c e $EDI CTOP. p lace17 #placeDes ign

16

EDA Flowsoc encounter script (tcl)

.lef tech file

.lib tech file

die dimensions

pin assignment

placement


1 globalNetConnect VDD −type pgpin −pin $EDI TVDD − i n s t ∗

2 globalNetConnect VSS −type pgpin −pin $EDI TVSS − i n s t ∗

3 s rou te

4

5 setExtractRCMode −engine preRoute

6

7 optDesign

8

9 setNanoRouteMode −routeTopRoutingLayer $EDI CL

10 g loba lDeta i lRoute

11

12 extractRC −o u t f i l e $EDI CTOP . cap

13

14 r ep o r t t im ing

15

16 wr i t e s d f $EDI CTOP. sd f

17

18 saveDesign $EDI CTOP

17

EDA Flowsoc encounter script (tcl)

routing in M1 just to measure power

restructuring, buffer insertion

restore using GUI


1 s e t EDI TSYNLIB TSMC−65nm/TSMCHOME/2 d i g i t a l /Front End/ t iming power no i s e /3 NLDM/ tcbn65gp lus 200a / tcbn65gpluswc.db4 s e t EDI TPNRLIBLIB TSMC−65nm/ . . .5 t cbn65gp lu swc . l i b6 s e t EDI TPNRLIBLEF TSMC−65nm/ . . .7 t cbn65gp lu s 9 lmT2. l e f8

9 s e t EDI CPATH ˜cmos4arch / ed ine t /121/ ewire /65nm10

11 s e t EDI CDELAY 512 s e t EDI CX 800013 s e t EDI CY 3 .614 s e t EDI CL 415 s e t EDI CINR BUFFD416 s e t EDI COUTC 0 .002008

18

EDA Flow

tool configuration


1 exec dc shel l−xg−t << { sou rce $EDI LPATH/ s y n . t c l }2

3 exec encounter −nowin − in i t $EDI LPATH/ pn r . t c l4

5 exec n cv e r i l o g tbench .v $EDI CTOP.v $EDI TSIMLIB+acc e s s+r

6

7 exec encounter −nowin − in i t $EDI LPATH/ powe r . t c l

19

EDA Flow

tool run

Giorgos Passas, FORTH−ICS, Spring 2012 20

CMOS Technology Filesdatasheets

X1, ..., X20 Height = Standard Cell Row Height

.lef filealso includes interconnect characteristics

Giorgos Passas, FORTH−ICS, Spring 2012 21

CMOS Technology Filesdatasheets

.lib file

Next Lecture 7

wire models, cost, and performance

Documents

CMOS Technology for Computer Architectsusers.ics.forth.gr/~jacob/cmos4arch/handouts/lec6_1pp.pdf · HDL Synopsys NCVlog activity(f) netlist & constr. netlist & delays ... sdf/sdc