Slide 1

CMOS RF Integrated Systems--Trends and Challenges

May 3, 2001Chicago, IL

David J. Allstot

Boeing-Egtvedt Chair Professor

Department of Electrical EngineeringUniversity of WashingtonSeattle, WA 98195-2500

Tel: 206-221-5764; Fax: 206-543-3842

allstot@ee.washington.edu

Slide 2

Outline

• RF Active and Passive Devices v/s Scaling Roadmap

• Monolithic Inductors v/s Monolithic Transformers

• Single-Ended v/s Fully-Differential RF Circuits

• Compact Modeling / Simulated Annealing Optimization

• CMOS RF Circuit Examples: LNA, DA, PA, etc.

Slide 3

SIA National Technology Roadmap

Year First Product Shipment 1997 1999 2001 2003 2006 2009 2012

MPU FETs/cm**2 8M 14M 16M 24M 40M 64M 100M

ASIC CHIP SIZE (mm**2) 480 800 850 900 1000 1100 1300

ASIC PACKAGE PINS/BALLS 1100 1500 1800 2200 3000 4100 5500

ASIC CLOCK FREQ. (MHZ) 300 500 600 700 900 1200 1500

MAX. WIRING LEVELS 6 6 or 7 7 7 7 or 8 8 or 9 9

MIN. LOGIC VDD (V) 1.8-2.5 1.5-1.8 1.2-1.5 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6

POWER (HAND HELD) (W) 1.2 1.4 1.7 2 2.4 2.8 3.2

POWER (HEAT SINK) (W) 70 90 110 130 160 170 175

Key Issues: Cascodes Problematic at Low Voltages

More metal layers for inductors/transformers

Gate Length (nm) 180 140 120 100 70 50 35

Slide 4

CM013MS1P8M

1.2/2.5V

CM018MS1P6M

1.8/3.3V

CM025MS1P5M

2.5/3.3/5V

CM010MS1P9M

CM025RF1P5M

2.5/3.3/5V CM018RF

1P6M1.8/3.3V

CM013RF1P8M

1.2/2.5V

CM010RF1P9M

BiC0353P4M3.3V

SiGeBiC0353P4M3.3V

SiGeBiC0183P6M

1.8/3.3V

RF CMOSMS CMOS RF BiCMOS

1999 2000 2001 2002 2003 2004

TSMC Mixed-Signal/RF Technology Roadmap

Slide 5

Small-signal model

sig

dsT

gsT

RRRR

ff

Cgm

f

++=

=

max

2π

G

S

DRg

Cgs

Ri

Cgb

Rsub

Cgd

gmVgs Rds

Rs

Vgs

+

-

5.1:

)/(21 22min

≈+++=

PNote

RwCgPRRNF igsmsg

E. Morifuji, et al., “Future persepectiveand scaling down roadmap for RF CMOS,”Symposium on VLSI Circuits, pp. 165-166,1999.

Slide 6

Ft, Fmax and Vdd vs Technology

Technology (nm)

050100150200250300

ft an

d fm

ax (G

Hz)

0

100

200

300

400

500

Vdd

(V)

0.5

1.0

1.5

2.0

2.5

3.0

ft (experiment)ft (calculation)fmax (experiment)fmax (calculation)Vdd

Slide 7

Roadmap of Linearity (IP3 at gm=40mS) and P1dB

1.92.02.23.64.14.96.74.7Id(mA)

1116201921222321IP3(dBm)

3.62.93.05.56.57.08.87.0Id(mA)

8

80

11

60

1.2

1

70

2005

-1

60

6

35

---

---

35

2009

4

70

9

50

---

---

50

2007

9

140

16

100

3.9

17

120

2001

11

240

17

150

6.7

21

180

1997

7109P1dB(dBm)

171516IP3(dBm)

2.64.47.0Id(mA)

100140250Gate Length (nm)

110170280Wg(µm)

80110200Wg(µm)

91916IP3(dBm)

200319991995Year

Wg=200µmconstant

Wg:scaledWith Lg

Wg:optimizedscaling

IP3 = 10log(gm/gm3) + 12.2dBm; 12.2dBm is a fudge factor

Slide 8

Technology (nm)

050100150200250300

IP3

and

P1d

B (d

Bm

)

-5

0

5

10

15

20

25

NFm

in (c

alcu

latio

n)

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

IP3

P1dB

NFmin

IP3 , P1dB and NFmin vs Technology

Slide 9

Silicon Spiral Inductor

Cross Section

underpass

Rs

W

S

G

via

Top View

Rs – Series resistanceW – WidthS – SpacingG – Inner core gap

Cox – Oxide capacitanceRsub – Substrate resistanceCsub – Substrate capacitancetm – Metal thicknesstox – Oxide thickness

M2

M1 viaCp

S G

Rsub

Cox

Csub

Dielectric

Dielectric

Si

tm

passivation

tox

ρ

Slide 10

Substrate Loss due to Magnetic Coupling

q Lenz’s law – “An induced electromotive forcegenerates a current that induces a countermagnetic field that opposes the magnetic fieldgenerating the current.” V = -N (∆φ / ∆t)

q Isub reduced by high resistivity substrate

B(t)

-I-I I I

Isub -Isub

Slide 11

q Thicker oxide

q Low-k dielectric

Resistive Loss in Epi due to E-Field Penetration

q Reduced by Pattern Ground Shield [1]

§ Tradeoff: Lower self-resonant frequency fSR

[1] C. Yue, et al, “On-chip Spiral Inductors with Patterned Ground Shields for Si-based RF IC’s,” JSSC, May 98, pp. 743 - 752

Heavily Doped BulkE

Heavily Doped BulkE

q Reduced by high resistivity

Slide 12

Conductor Loss

q Series Rs – reduce by strapping 2 or moremetal lines; use Cu

q Skin effect –

q δ - skin depth, µ - permeability, σ - resistivity§Avoid using wide metal lines

ωσµδ

⋅⋅= 2

Slide 13

Eddy Currents in Planar Inductor

q Generation of eddy currents in the planarinductor decreases the inductance§Use large inner core gap – G (120µm)

…Ieddy

Icoil

Icoil Icoil

Beddy

Bcoil

Slide 14

Impact of Technology Advancement on Inductors

q More metal layers for strapping → less seriesresistance, Rs

q Copper metal → lower series resistance

q Low-k dielectric → improves substrate loss

Slide 15

Figure 1a Figure 1b Figure 1c

Coupled Inductors/Transformers

A=planar transformer; B=stacked transformer;C=planar inductor

Table 1Structure Number of turns Metallization

Transformer a Planar (Fig. 1a) 3 Metal 5Transformer b Planar (Fig. 1a) 4 Metal 5Transformer c Planar (Fig. 1a) 5 Metal 5Transformer d Planar (Fig. 1a) 4 Metal 5 shorted to

Metal 4Transformer e Non-planar (Fig 1b) 4 Metal 5 spiral on

Metal 4 spiralInductor (Fig 1c) 5 Metal 5

0.25 µm CMOS transformer test chip

Slide 16

L Rseries

Rseries L

Cox

Cox

Csi

Rsi

Cox

Rsi

Csi

Cox Cc k

*

*

L

Cc

L Rseries

Rseries Cox

Cox

Csi

Rsi

*

* k

Lumped-Element Transformer Models

Table 2L(nH) k R (Ohms) Cox (pF) Cc (pF) Csi (pF) Rsi(Ohms)

Trans a 3.3 0.71 9.0+2.0f 0.10 0.005 0.7 8Trans b 5.2 0.75 11+3.5f 0.18 0.01 0.0005 2Trans c 7.9 0.79 16+5.2f 0.29 0.06 0.005 4Trans d 5.5 0.78 8.1+3.6f 0.19 0.02 0.001 3Trans eupper/lower

3.1 / 3.4 0.92 9.5+1.0f /18+1.0f

0.06 / 0.21 0.10 0.001 1

Inductor 6.9 12+5.0f 0.086 0.09 0.4 6

FastHenry (MIT) used to estimate inductance; L is assumedfreq. Independent above. It actually varied by about 10% from1GHz to 4GHz so including a freq. Dependent inductancewould increase model accuracy.

Slide 17

|S21| Measured

|S11| Fitted

|S11| Measured

|S21| Fitted

∠S21 Measured

∠S21 Fitted ∠S11 Fitted

∠S11 Measured

Figure 4a

Figure 4b

Figure 4) Measured and modeled (fitted) s-parameters for the 3-turn transformer in metal 5 (transformer a).a) S11 and S21 magnitude, and b) S11 and S21 angle.

|S21| Measured

|S11| Fitted |S11| Measured

|S21| Fitted

∠S11 Fitted ∠S11 Measured

∠S21 Measured ∠S21 Fitted

Figure 5a

Figure 5b

Figure 5) Measured and modeled (fitted) s-parameters for the 4-turn transformer in metal 5 (transformer b).a) S11 and S21 magnitude, and b) S11 and S21 angle.

S11, S22 Measurements; Symmetrical Transformers

Slide 18

|S11| Fitted

|S11| Measured

|S22| Fitted

|S22| Measured

|S12| Fitted

|S12| Measured

∠S11 Fitted ∠S11 Measured

∠S22 Fitted ∠S22 Measured

∠S12 Fitted

∠S12 Measured

Figure 8a

Figure 8b

Figure 8c Figure 8d

Figure 8) Measured and modeled (fitted) s-parameters for the 4-turn transformer with primary in metal 5and secondary in metal 4(transformer e). a) S11 and S22 magnitude, b) S12 magnitude (identical to S21), c)S11 and S22 angle, d) S12 angle (identical to S21).

S-Measurements; Non-symmetrical Transformers

Slide 19

4 Turn Trans. (M5 via to M4) 3 Turn Trans. (M5)

4 Turn Trans. (M5)

5 Turn Trans. (M5)

Inductor

Table 3L (nH) Q SRF (GHz)

Trans adifferential mode

5.6 5.6 peak@3.2GHz

6.7

Trans bdifferential mode

9.1 4.8 peak@2.0GHz

3.9

Trans cdifferential mode

14 3.6 peak ?@1.3GHz

2.5

Trans ddifferential mode

9.8 5.9 peak@1.7GHz

3.7

Inductor 6.9 3.5 peak@2.0GHz

6.5

Transformer/Inductor Q-Factor/Resonant Freq

Slide 20

Substrate Noise Effects

Digital CktsAnalog Ckts

Substrate

Digital CktsAnalog CktsGuard ring

Substrate

Slide 21

Isolation of Substrate Noise in Differential Circuits

q Excellent substrate noise isolation was foundin differential circuits§All noise signals coupled to the substrate appear

as common mode signals on the differentialoutputs

Slide 22

900 MHz CMOS Low-Noise Amplifier

RFinM1 M2

M3 M4

T1

RFout

M5 M6

T3

driver stage

T2

input stage

Vdd

Vbias

ac ground

Iref

M22

M44

M66 M666

M8

biasing

start-up

Rb2Rb1

M7

(c)

L1

L2

R1

R2

Cox2Rsi1

Rsi1

Rsi2 Rsi2

RcRc

Cox1

Cox2

Cox 1

Csi2

Cc Cc

Csi1

Csi2

Csi1

k

(b)

A

BC

E

F GH

Dsegment 1

segment 2

• First fully-differential CMOS LNA and first CMOS RF circuitto employ monolithic transformers

Slide 23

900 MHz CMOS Low-Noise Amplifier (cont.)• J.J. Zhou and D.J. Allstot, “A fully-integrated CMOS 900 MHz LNA usingmonolithic transformers,” ISSCC Digest ofTechnical Papers, pp. 132-133, Feb. 1998.

• J.J. Zhou and D.J. Allstot, “Monolithictransformers and their application in adifferential CMOS RF low-noise amplifier,”IEEE J. Solid-State Circuits, pp. 2020-2027,Dec. 1998.

• Supply Voltage = 3 V

• Power Dissipation = 18 mW

• Noise Figure = 4.1 dB

• S21 = 12.3 dB; S12 = -33.0 dB

• 1 dB Compression (input) = -16dBm

• Technology: 3-metal 0.6um CMOS

• Key Trend: Fully-Differential RF Circuits toReject Switching Noise

Slide 24

0.5-5.5 GHz 5 dB CMOS Distributed Amplifier

Initial Analytic Design

Load

Source

3.0V

RFC

1.49n

1.86n 1.86n

1.49n

2.82n 2.82n 2.26n

2.26n

706f 706f 706f 706f

1.86n

2.82n

338f

1.50n50

237f

0.99n

237f

0.99n 50

1.0V

338f

1.50n

Coupling50p

Coupling50p

309.90.9

309.90.9

309.90.9

309.90.9

50p

50p

Another key trend: Parametric modeling and

aggressive optimization

Slide 25

0.5-5.5 GHz 5 dB CMOS Distributed Amplifier (cont.)

Initial Design--Simulation Results with and w/o Inductor Parasitics

Without

Inductor

Parasitics

With

Inductor

Parasitics

0 dB-10 dB

1 2 3 4 5 6GHz

Poor Response. Smith Chart? Parasitic-Aware Design!

Slide 26

Parametric Inductor Modeling: Analytic/Experimental

Port 1 Port 2

R1(f)

L 1(f) L 2(f)R2(f)

C3(f)

R3(f)

L Lind1 = A1f 3+A2f2+A3f+A4

A1 = B1L5+B2L4+B3L3+B4L2+B5L+B6

6 components total for model

L

Lind1

ind2

ind3

f ittedinductormodels

Lind2 = A1f 3+A2f2+A3f+A4

L ind3 = A 1f3+A2f2+A3f+A4

4 freq. coeff. per component(24 total for model)

6 ind. coeff. per freq. coeff.(144 total)

3 Measured Inductors: (Min, Mid, Max) Fit Measured S Params toMOMENTUM. Use MOMENTUM for Interpolation

Slide 27

Simulated Annealing Optimization Loop

ModelGenerator

Inductor

HP Momentum

MeasuredResults

Analytic Models(Greenhouse)

Matlab(Model Fitting) T-Circuit

Simple

Model

Model LibraryModifyCircuit

New HSpiceCircuit

Spice Simulator

PerformanceEvaluation

SimulatedAnnealingAlgorithm

MetropolisCriterion

CoolingSchedule

Inductor Modeling Detail

Optimization Detail

Key Result for RF Design

Slide 28

0.5-5.5 GHz CMOS Distributed Amplifier

• First fully-monolithic 0.6 µm CMOS DA and first to besynthesized using simulated-annealing custom CAD tool.

Gate Line

Load200f

Drain Line

Source

200f

0.75n20

3V 50150f

150f

50p

502.0n

2.0n

50p

200f

50p 200f

2.5n

2.5n2.0n

50p

0.75n

200f

2.0n

200f

(LD2)

(LD3)(CD)

Square-spiral monolithic inductor

(LG1)4.0n

2520.6

1.29n(LG2)

0.87n(LG3)

1000f(CG)0.95V

Bias

(LD1)4.0n

3.0n

700f

1.25n

Bias

Packagemodeled as 2-port subcircuit(...)

(LD1)4.0n

(LD1)4.0n

2520.6

2520.6

2520.6

(LG1)4.0n

(LG1)4.0n

Independent VariablesSimulated Annealing

Parasitics

Slide 29

0.5-5.5 GHz CMOS Distributed Amplifier (cont.)

• B. Ballweber, R. Gupta, and D.J. Allstot, “Fully-integrated CMOS RF amplifiers,” ISSCCDigest of Technical Papers, pp. 72,73,448, Feb. 1999.

• B. Ballweber, R. Gupta, and D.J. Allstot, “A fully-integrated 0.5-5.5 GHz CMOSdistributed amplifier,” IEEE J. Solid-State Circuits, pp. 231-239, Feb. 2000.

Analytic Design(w/Parasitics)

Analytic Design(Ideal)

Final OptimizedDesign

Final OptimizedDesignAnalytic Design

(w/Parasitics)Analytic Design

(Ideal)-1000-800-600-400-200

0200

Ph

ase

s

21

(deg

rees

)

1 2 3 4 5 6 7 8Frequency (GHz)

1 2 3 4 5 6 7 8Frequency (GHz)

-40

-30

-20-10

010

Gai

n |s

21| (

dB

)

0.79mmxmm; 0.6um CMOS

Test Results from Single-Ended Dist. Amplifier

Slide 30

0.5-5.5 GHz CMOS Distributed Amplifier (cont.)

Mag

nitu

de (d

B)

Frequency (GHz)

ForwardGainS21

InputMatch

S11

OutputMatch

S22

ReverseIsolation

S12

1 2 3 4 5 6 7 8-40

-30

-20

-10

0

10

Mag

nitu

de (d

B)

Frequency (GHz)0.5 1 1.5 20

2

4

6

8

Measured

s-parameter

values

Measured

NF

(1.8GHz)

Power Dissipation = 83mW

Slide 31

0.5-8.5 GHz CMOS Fully-Differential Dist. Amplifier

• First fully-monolithic fully-differential 0.6 µm CMOS DA.Key Idea: Wideband due to elimination of inductor sourcedegeneration. Also achieves digital switching noise rejection.

Slide 32

Simulations--Simulated Annealing Optimization

Before

After

Before

After

Slide 33

0.5-8.5 GHz CMOS Fully-Differential Dist. Amplifier

5 10 15

-40

-20

0

SDD

11

5 10 15

-40

-20

0

SD

D12

5 10 15

-40

-20

0

Frequency [GHz]

SD

D21

5 10 15

-40

-20

0

Frequency [GHz]

SD

D22

5 10 15

-40

-20

0

5 10 15

-40

-20

0

5 10 15

-40

-20

0

Frequency [GHz]5 10 15

-40

-20

0

Frequency [GHz]

5 10 15

-40

-20

0

SC

D11

5 10 15

-40

-20

0

SC

D12

5 10 15

-40

-20

0

Frequency [GHz]

SC

D21

5 10 15

-40

-20

0

Frequency [GHz]

SC

D22

5 10 15

-40

-20

0

5 10 15

-40

-20

0

5 10 15

-40

-20

0

Frequency [GHz]5 10 15

-40

-20

0

Frequency [GHz]

Measured mixed-mode S-parameters in [dB] of fully-differential distributed amplifier

Slide 34

Comparative Results--Single-ended v/s Differential

Fully-Differential

Distributed Amplifier

Single-ended

Distributed Amplifier [9]

Differential Gain, SDD21 5 ± 1.5dB (1.5 - 7.5GHz) 6.1 ± 1.3dB (0.5 – 4GHz)

Unity Gain Bandwidth 8.5GHz 5.5GHz (Probed)

4GHz (Pakaged)

Noise Figure 8.7 – 13dB (1 – 2GHz) 5.4 – 8.2dB (1 – 2GHz)

Isolation, SDD12 -22dB -20dB

Power dissipation 216mW (VDD=3.0V) 103.8mW (VDD=3.0V)

Chip Size 1.3mm x 2.2mm 1.4mm x 0.8mm

Technology 0.6µm standard CMOS 0.6µm standard CMOS

Slide 35

0.5-8.5 GHz CMOS Fully-Diff. Dist. Amp. (cont.)

• H.-T. Ahn and D.J. Allstot, “A0.5-8.5 GHz fully-differentialCMOS distributed amplifier,”IEEE J. Solid-State Circuits,2001. (To appear)

Note: Hee-Tae Ahn is currentlywith National Semiconductor, Inc.

Key Points: Fully-DifferentialTopologies for rejection of digitalswitching noise and elimination ofsome inductive feedback effects.Simulated annealing optimizationfor robust design accuracy.

Slide 36

900 MHz CMOS Class-C Power Amp Output Stage

• First fully-monolithic fully-balanced 0.6 µm CMOS PA.Achieved 55% drain efficiency due to inductor modeling/CADoptimization (basically simulated-annealing load-pull method).

R

VddVb

vin_p

50Ω

Vdd/2

Slide 37

900 MHz 100 mW CMOS Class-C Power Amp (cont.)

• R. Gupta and D.J. Allstot,“Fully-Monolithic CMOS RFPower Amplifiers: RecentAdvances,” IEEECommunications Magazine,vol. 37, pp. 94-98, April1999.

•R. Gupta, B. Ballweber, andD.J. Allstot, “Design andoptimization of CMOS RFpower amplifiers,” IEEE J.Solid-State Circuits, Jan. 2001.

• S21 = 6.0 dB

• S11 = -6.15 dB

• S12 = -25.6 dB

• PAE = 30 %

Slide 38

Simulated Annealing is computationally intensive: 40,000

simulations for PA Output Stage; 4 days on Sun Ultra-10

Simulated Annealing does not guarantee an optimimum

solution; Acceptable solutions are statistical in nature.

Simulated Annealing Statistical Design Space

Slide 39

Past, present and futurePast, present and future

Year 2002Year 2002

Mbps1 10 1000.1

Out

door

Stationary

Walk

Vehicle

Indo

or

Stationary/Desktop

WalkMob

ility

HiperLAN/2IEEE802.11a

User Bit rates

LAN

3Gcellular

HomeRFBluetooth

2G cellular

Wide Area Network (WAN)-Large coverage-High cost

Personal Area Network (PAN)- Connectivity- Cable replacement-Low cost

Local Area Network/Access- High speed- Hot spot- Moderate cost

MBSMBS

Slide 40

HIPERLAN family

PHY

(17 GHz)

150 + Mbps

PHY

(5 GHz)

20 + Mbps

PHY

(5 GHz)

20 + Mbps

PHY

(5 GHz)

20 + Mbps

DLCDLCDLCMAC

HIPERLAN TYPE 4

Wireless ATM

Interconnect

HIPERLAN TYPE 3

Wireless ATM

Remote access

HIPERLAN TYPE 2

Wireless ATM

Indoor access

HIPERLAN TYPE 1

Wireless LAN

Slide 41

Spectrum allocation @ 5Spectrum allocation @ 5 GHz GHz

5100

U-NII, Unlicensed

5200 5400 5600 58005300 5500 5700

High Speed Wireless Access

5.15 - 5.30

5.15 – 5.35

5.470 -5.725HiperLAN, License exempt

5.725 - 5.825

5.15 - 5.25

EuropeEurope455 MHz455 MHz

JapanJapan100 MHz100 MHz

USUS300 MHz300 MHz

200 mW EIRP200 mW EIRP 1W EIRP1W EIRP

200 - 800 mW EIRP200 - 800 mW EIRP 1W EIRP1W EIRP

Slide 42

Conclusions

• Fast improvement in RF Devices v/s scaling trends

• Slow improvement in Passive devices v/s scalingtrends

• Implementation of Fully-Differential RF circuits ... A lamixed-signal circuits in recent years

• Modeling/Optimization key to robust RF designs

• CMOS RF Wireless LAN at 5GHz (Atheros, Radiata,etc.) Products are here!

• Seamless Multi-Standard CMOS Radios (Bluetooth,802.11, etc. -- Mobilian Corporation -- neat productscoming!