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CMOS Model’s FLAG Control System
Tigran PetrosyanPhD student of “Microelectronic Circuits and Systems“Interdepartmental Chair of State Engineering University of Armenia (SEUA),
R&D Engineer of “SYNOPSYS Armenia” CJSC
2Contest
• Evolution of CMOS transistors models • Results of CMOS transistors models evolution • Drawbacks of existing approaches• Proposed approaches for model speed and accuracy increase • Target function definition for CMOS model speed and accuracy increase• Proposed flow for model speed and accuracy increase• Example Accuracy and speed increase flow application • Accuracy and speed increase flow application results• CMOS model speed and accuracy increase software structure and functionality• FLAG software graphical interface• FLAG efficiency estimation
3CMOS transistors models evolution (1)
N+ N+
P- bulk
drain
gate
source
Gate oxide
BSIM1
⎪⎪⎪⎪
⎩
⎪⎪⎪⎪
⎨
⎧
⋅
⎟⎟⎠
⎞⎜⎜⎝
⎛⋅
⋅
=
==
++==
=
q
nomTBKtm0V
nomTT at, i0n
Nlntm0V2s
s1KsFbVth0
VThideal.V
thV chΦ
ΦΦ
4CMOS transistors models evolution (2)
BSIM4
th.(6)V
th.(5)V
th.(4)V
th.(3)V
th(2)V
th(1)V
thidealV=
thV ΔΔΔΔΔΔ ++++++
bseffV
oxmT
oxT
2_K
bseffV-
soxm
Tox
T
1K=
th(1)V ⋅⋅⋅⋅ ΦΔ
bm.V-
s2K2-
2=
1K Φγ ⋅⋅
bx.V)
s-
bx.V-
s(
s2
)s
-bx.
V-s
()2
-1
(=
2K
+⋅
⋅
ΦΦΦ
ΦΦγγ
ûxC
chN
siq2
=1
⋅⋅⋅ εγ
ûxC
ch.N
siq2
=2
⋅⋅⋅ εγ
si2
2t
Xch
Nq-
s=
tX
εΦ ⋅
⋅⋅
( ) ⎥⎦⎤
⎢⎣⎡ ⋅⋅⋅
bcV
14-2
1-
bcV-
bsV+
1-
bcV-
bsV0.5+
bcV=Vbseff δδδ
22K*4
21K
+s0.9=bcV Φ⋅
seffL
effLN+1
ûxmT
ûxT
1K=
th(2)V ΦΔ ⋅⋅⋅⋅
( ) ( )sbiVtwLeffLeffW
VT1D2etw2L
effLeffWVT1D
eVTOD4thV φΔ −−
+−
= ⋅⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
( ) ( )
sio2
depXoxTsit0l
bsVtabEta0Et0LeffL
VT1De2t0L*2
effLVT1D
e6thV eff
ε
ε
Δ
⋅⋅
⋅⋅⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
⋅
=
++=⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛
⎟⎟⎟
⎠
⎞
⎜⎜⎜
⎝
⎛ ⋅⋅
5CMOS transistors models evolution (3)
BSIM5 - new physical effects
))oxacc
VCIGBACC(1
)oxacc
VBIGBACC(AIGBACCTOXEBexp(aux1
V
thV2TOVE
1NTOX
TOXETOXREF
AeffLeffW=hI
⋅⋅
⋅⋅⋅⋅⋅⋅
⋅⋅⋅⎟⎠⎞
⎜⎝⎛⋅⋅
+
−−
))oxdep
VACCINVCIGB(1
)oxdep
VBIGBINV(AIGBINVTOXEDexp(aux2
V
thV2TOVE
1NTOX
TOXETOXREF
C¿ýýL¿ýýW=hI
⋅⋅⋅
⋅⋅⋅⋅⋅⋅
⋅⋅⋅⎟⎠⎞⎜
⎝⎛⋅⋅⋅
+
−−
))ûxde
VACCINVCIGB(1
)oxde
VBIGC(AIGCTOXEFexp(
tV*NIGC
VTH0gseVexp1log
tV
NIGCgse
V2TOVE
1NTOX
TOXETOXREF
E¿ýýL¿ýýW=hI
⋅⋅⋅
⋅⋅⋅⋅⋅
⋅⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
⎟⎟⎠
⎞⎜⎜⎝
⎛⋅⋅
⋅⋅⋅⋅⎟⎠⎞
⎜⎝⎛⋅⋅⋅
+
−−
−+
oxCLW
21
sC
sC ⋅⋅⋅==
oxCLW
32
chC ⋅⋅⋅=
0=³ñC=³ÏCûùëǹCLW=Ñá.ѳC ⋅⋅
h.bC+
d.bC+
s.bC=
dbC
CUI ⋅⋅= ω
6Results of CMOS transistors models evolution
New physical effect
BSIM1 BSIM4tmash 1,5-2 times
BSIM1 BSIM4tmash 1,7-2,5 times
Web-site: http://www.intel.com/technology/silicon/mooreslaw/index.htm
Analysis complexity Parameters
number growth IC elements
number growth
Need in increase of model speed and accuracy
ModelEquation
Complication
7
Computational gates application flow
bsVcU+2)ox)/TbseffVgs((VbU)ox)/TbseffVgs((VaU+10μ
=¿ýýμ⋅+++⋅ mobmod=1
2)/Tox)thV+gsteff((VbU+)/Tox)thV2+gsteff((V)bseffVcU+a(U+11μ
=¿ýýμ⋅⋅⋅ mobmod=2
Input parameters
Calculation equation
Calculation equation
Calculation equation
Calculation equation
Output results
K1
K2
Kn
1. Trade-off between number of operations and achieved accuracy in avery computational case
Proposed approaches for model speed and accuracy increase (1)
8
L8
L0
L1
L2
L3
L4
L5
L6
L7gm
CMRRr»Éù
W LNSS T NSUB Tûx
Cûx
GAMMA
PHI
egap
Vth
Id
PHIms
VFB
VT0
2. Elimination of information lack and excess during calculations
Proposed approaches for model speed and accuracy increase (2)
9
Transistor model computation flow
Proposed approaches for model speed and accuracy increase (3)
10
Trees of computational gates
Proposed approaches for model speed and accuracy increase (4)
11
3. Different accuracy for transitions depending on demands occurring during current computational situation
4. Model universality: independency from modelin circuit, technological process, circuit base, etc.
5. CMOS transistor compatibility with other electrical elements’ models (diodes, resistors, etc): no need in recalculations during modeling with such models
Hierarchy of adaptation criteria used in CMOS transistor’s model
Proposed approaches for model speed and accuracy increase
12
Target function
→machE min
Limitation
Δ Δ<calc alow ε ε<calc alow&
S1,2...,iiii ,bPa =≤≤
Δ = −r r
calc calc realY Y
ε −=
r r
rcalc realcalc
calc
Y YY
= == =r
calc ij ij i 1,2,...,t;j 1,2,...,qY F(AC f(G ))
= ==
= = Ψ =∑n
mach mach ij ij i 1,2....,t;j 1,2,...,qd 1
E t (AC f(G )),
= == − < Δr
ij ij i 1,2,...,t;j 1,2,...,q real alowF(AC f(G )) Y
ε= == −<
r
rij ij i 1,2,...,t;j 1,2,...,q Çñ³ Ï .alow
real
F(AC f(G )) YY
S1,2...,iiii ,bpa =≤≤
ψ = == = →mach ij ij i 1,2....,t;j 1,2,...,qE (AC f(G )), min
Target function definition for CMOS model speed and accuracy increase
13
Definition of CMOS model and number of models in hierarchy of equations
Designed IC preliminary and fast simulation with low accuracy
Simulation results for designed IC meet specification
Definition of model flags for designed and reference circuit
Designed and reference circuit description formation
Simulation of reference circuit
Simulation results for reference IC meet specification
Simulation of designed IC
Technological information, simulation condition and specification input
9
1
2
3
4
5
6
7
8
Start
End
yes
yes no
no
Proposed flow for model speed and accuracy increase
14Example
Accuracy and speed increase flow application (1)
M1
VDD
VDDIO
IN
VSS
DOUT
M2
M3
M4
M5 M6
M8M7
VDD
M9
M10M11
M12
Low to high level shifter
Parameters Typical Min Max Dimension
Core supply (VDD) 1,2 1,08 1,32 V
I/O supply (VDDIO) 2,5 2,25 2,75 V
Clock frequency 240 120 - MHc
Temperature 25 125 -40 ûC
Power dissipation 10 - 11 uWt
Level shifter operating conditions
15
parameters typical min max Dimension
Simulation time 64 - 70 s
Calculations results
accurse 99 97 - %
Technology TSMC65 - - -
Thick oxide transistor yes - - -
Thin oxide transistor yes - - -
Channel length - 65 - nm
Level shifter specification and technology information
Simplified simulation results
Example Accuracy and speed increase flow application (2)
16
Simulation time dependence from number of computational gates for TSMC65
Frequency simulation results for gate capacitive and tunneling currents
Example Accuracy and speed increase flow application (3)
17
0,0248 % 1,7%
57,14 í 84.97 í
FLAG BSIM 4.4.0
More accurate results need more time
Gain
1,67%
27.83 s/47%
Accuracy and speed increase flow application results
Average relative error with this model
Time needed for simulation with this model
18CMOS model speed and accuracy increase software structure and
functionality
Control subsystem
Database of values for CMOS IC typical units’ computational gates
Subsystem of fast and low accuracy simulation
Subsystem of technological information input
User graphical interfaceSubsystem of final calculation of computational gates
Gate switch formation for typical units
Process of calculation equation selection
Structure of model accuracy and speed increase FLAG software
Estimation of technological process
Estimation of working frequencies
Accounting parameters for threshold voltage
Supply voltage accounting
19FLAG software graphical interface
Input of model separate parameter
IC simulation parameter selection
20FLAG efficiency estimation (1)
Processing steps Synopsys Cadence FLAG
Comparative
gain
(%)
Synopsys/ Cadence
Preliminary model
construction- - 3,2ñ -
IC preliminary
simulation- - 61,21ñ -
Model switch
optimizations - - 1,12ñ
IC simulation time
18,4Å 21,2Ä 6,2Å 61,12%/ 73,4%
IC simulation
accuracy96,1% 96,2% 98,4% 2,3%/2,2%
USB TX block-diagram
USB TX simulation time comparison
21
Processing steps Synopsys Cadence FLAG
Comparative gain(%)
Synopsys/
Cadence
Preliminary model
construction- - 30,3min -
IC preliminary
simulation- - 10,46h -
Model switch
optimizations - - 39min
IC simulation time
10,6day 10,2day 1,5day 81,1%/ 79,8%
IC simulation
accuracy82,5% 82,2% 96,9% 14,4%/ 14,7%
Simulated digital unit
Digital unit’s simulation results1` Real chip measurements, 2` simulated with FLAG, 3` simulated with Nanosim
FLAG efficiency estimation (2)
22
Thank you
