BASICS OF VLSI LAB REPORT II

MONSOON 2012 Page 1

CMOS INVERTER STATIC AND DYNAMIC CHARACTERISTICS

SUBMITTED BY

Davis Oommen Abraham(M101233EC)

Richu Jose Cyriac(M120128EC)

AIM

To study static characteristics of CMOS inverter. To study the robustness of CMOS inverter by varying temperature and

supply voltage scaling. To study the dynamic characteristics of CMOS inverter in both pre-layout and

post-layout simulations. TOOLS

CADENCE MICROSOFT EXCEL

A. STATIC CHARACTERISTICS OF CMOS INVERTER

THEORY Important terms:

VOH: max output voltage when output is “1” Vin : input voltage to inverter Vout : output voltage of inverter VM : threshold voltage of inverter is defined as the point at which Vin is equal to the Vout VOL: min output voltage when output is “0” VIH : min input voltage which can be interpreted as “1” VIL : max input voltage which can be interpreted as “0”

VIH and VIL are the points at which 1

dVindVout

Threshold voltage (VM) for a non velocity saturated device is given by:

rVVrVV TpDDTn

M

1)(

where n

p

kkr

eqn(1)

Also,

IHOHMH VVN , where MHN is Noise margin high eqn(2)

OLILML VVN , where MLN is Noise margin low eqn(3)

BASICS OF VLSI LAB REPORT II

MONSOON 2012 Page 2

Region of operation: The region of operation of the nMOSFET and pMOSFET at various inputs is summarized below.

VIN VOUT nMOSFET pMOSFET

<VT,n VOH Cut-off Linear VIL Approx. VOH Saturation Linear VM VM Saturation Saturation VIH Approx.VOL Linear Saturation

>VDD + VT,p VOL Linear Cut-off

Table1.1 Defining different regions of a CMOS static characteristics

OBSERVATIONS

Fig 1.1 Extraction of MV , IHV , ILV , OHV , OLV Fig1.2 : VTC of CMOS inverter as a function of PMOS width INFERENCES

Rail to rail voltage swing is seen Gain is maximum at VM Static CMOS inverter can be used as an analog amplifier in transition region owing to its high gain Changing the width ratio shifts the Voltage transfer curve (VTC) Increasing width of PMOS or NMOS moves VM (threshold voltage of inverter) towards VDD or GND Logic levels are not dependent upon relative device sizes ie. CMOS inverter is a ratioless logic

-15

-10

-5

0

5

0 0.5 1 1.5 2

Out

put V

olta

ge(V

)

Input Voltage(V)

Vout

Derivative VoutVin=Vout,line

0

0.5

1

1.5

2

0 0.5 1 1.5 2

Out

put V

olta

ge(V

)

Input Voltage(V)

Wp/Wn=1

Wp/Wn=2

Wp/Wn=3

Wp/Wn=4

BASICS OF VLSI LAB REPORT II

MONSOON 2012 Page 3

B. EFFECT OF STATIC CHARACTERISTICS WITH RESPECT TO TEMPERATURE OBSERVATIONS

Fig 2.1 VTC of CMOS inverter as a function of Temperature Fig 2.2 VTC of CMOS inverter as a function of supply voltages

Parameters Wp = 1 Wn

Wp = 2 Wn

Wp = 3 Wn

Wp = 4 Wn

Wp = 5.83 Wn

VOH 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V VIH 822.5mV 946.5mV 1.01V 1.06V 1.09V VOL 0 V 0 V 0 V 0 V 0 V VIL 501.02 mV 594.8 mV 667 mV 727 mV 757.6 mV VM 689 mV 784.31 mV 828.62 mV 872.4 mV 900.8 mV NMH 977.7 mV 853.5 mV 790 mV 740 mV 710 mV NML 501.02 mV 594.8 mV 667 mV 727 mV 757.6 mV

Table 1.2 Extracted parameters from CMOS inverter characteristcs.

INFERENCES

DC characteristic of static CMOS inverter turns out to be rather insensitive to temperature variations.

The effect of power supply scaling is observed by varying power supply voltages without varying transistor voltages. Characteristics observed are similar to inverter eventhough the supply voltages is not large enough to turn the transistors on. The subthreshold currents are sufficient to switch the gate between high and low levels and to provide enough gain to produce appreciable VTC’s. This factor has to be considered since supply voltage is being scaled with technology.

00.20.40.60.8

11.21.41.61.8

2

0 1 2

Out

put V

olta

ge(V

)

Input Voltage(V)

218K

273K

300K

373K

423K

-0.5

0

0.5

1

1.5

2

2.5

3

0 1 2

Out

put V

olta

ge(V

)

Input Voltage(V)

Vdd=0V

Vdd=0.56V

Vdd=1.39V

Vdd=2.50V

BASICS OF VLSI LAB REPORT II

MONSOON 2012 Page 4

C. DYNAMIC CHARACTERISTICS AT PRE-LAYOUT AND POST-LAYOUT SIMULATIONS THEORY The parasitic capacitances extracted according to how layout is designed might be critical in affecting actual performance of the device. The main difference between the pre-layout and post-layout simulation is that the delays in the interconnections are taken into account in the post-layout simulation. The materials can be different types of metal, poly-silicon, and they introduce resistance and capacitance in the interconnections between the components and form a RC circuit. As a result, the interconnections require a finite charge up time and a delay is created. Post-layout simulation is important in a VLSI design as it uses a more accurate model to measure the performance of the design. Also it can be used to measure how good of the placement and routing is. If the post-layout simulation has a large difference from the pre-layout one, that means the placement and routing of layout design may not be good enough, and a greater effort should be put in the placement and routing.

DELAY PARAMETERS

)]([ 1)(4ln2)(

,

,

,

,

DD

nTDD

nTDD

nT

nTDDn

loadPHL

VVV

VVV

VVkC ……………………………...eqn(4)

)]([ 1),(4

ln,

,2)( ,

DD

pTDD

pTDD

pT

pTDDp

loadPLH

VVV

VVV

VVkC

………………………………eqn(5)

2

PLHPHLPavg

…………………………………………………………………………………………eqn(6)

PLH -time delay between %50V of falling input voltage and the %50V of rising output voltage PHL - time delay between %50V of rising input voltage and the %50V of falling output voltage Cload -Capacitance associated with CMOS

OBSERVATIONS

Fig 3.1: Variation of output from low-high when input goes from high to low

-5.00E-01

0.00E+00

5.00E-01

1.00E+00

1.50E+00

2.00E+00

0.00E+00 5.00E+01 1.00E+02 1.50E+02

Vol

tage

(V)

Time(s)

Vout (V)

BASICS OF VLSI LAB REPORT II

MONSOON 2012 Page 5

Fig 3.2 Ringing exhibited at high frequency

Parameter Pre Layout

Post Layout

PLH 0.023 ns 0.034 ns PHL 0.027 ns 0.029ns Pavg 0.025 ns 0.031 ns

Table 3.1 Delay parameters of CMOS inverter at pre-layout and post-layout simulations.

INFERENCES

Delay has been increased in post-layout simulation when compared to pre-layout simulation. A visible hump is present in the pre layout simulation. This could be due to the inductance in the MOSFET which

has to be taken into consideration at high frequencies. Since this is a pre-layout where wire and via inductances are not being considered, the presence of inductance points to the fact that MOSFET should be modeled along with an inductor at high frequencies.