Class2!10!11 12 Differential Signaling

7/31/2019 Class2!10!11 12 Differential Signaling

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12/4/2002

Differential Signaling

Introduction

Reading Chapter 6


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12/4/2002Differential Signaling

2

Agenda Differential Signaling Definition

Voltage ParametersCommon mode parametersDifferential mode parameters

Current mode logic (CML) bufferRelate to parametersModeling & simulation

Timing parametersClock recoveryEmbedded clock

AC couplingCommon mode responseIssues with simulation

8B10B encodingDC balanced codes

Duty Cycle distortionCycle


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3

Single Ended Signaling All electrical signal circuits require a loop or return

path. Single ended signal subject several means ofdistortions and noise.

Ground or reference may move due to switching currents(SSO noise). We touched on this in the ground conundrumclass.

A single ended receiver only cares about a voltage that isreferenced to its own ground.Electromagnetic interference can impose voltage on a singleended signal.Signal passing from one board to another are subject to thelocal ground disturbance.

We can counteract many of these effect by addingmore ground.

As frequencies increase beyond 1GHz, 80% of thesignal will be lost.


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Review of threshold sensitivity

The wave is referenced to either Vcc or Vss.Consequently the effective DC value of the wave willbe tied to one of these rails.

The wave is attenuated around the effective DCcomponent of the waveform, but the reference doesnot change accordingly. Hence the clock trigger pointbetween various clock load points is very sensitive todistortion and attenuation.

TxVss

Vss Rx2

Long lineVss Rx1

Short line


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5

Differential Signaling Any signal can be considered a loop is completed by two wires. One of the wires in single ended signaling is the ground plane Differential signaling uses two conductors

The transmitter translates the single input signal into a pairof outputs that are driven 180 out of phase.The receiver, a differential amplifier, recovers the signal as the differencein the voltages on the two lines.

Advantages of differential signaling can be summed up as follows

Differential Signaling is not sensitive to SSO noise.A differential receiver is tolerant of its ground moving around.If each wire of pair is on close proximity of one and other. electromagneticinterference imposes the same voltage on both signals. The differencecancels out the effect.Since the AC currents in the wires are equal but opposite and proximal,radiated EMI is reduced.

Signals passing from one board to another are not subject to the local grounddisturbances.As frequencies increase beyond 1GHz, up to 80% of the signal may be lost,but difference still crosses 0 volts.

There are still loss issues for differential signaling but only come into play in high losssystem. Most single ended systems assume approximately 15% channel loss.


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Differential Signaling - Cons

The cost is doubling the signal wires, butthis may not be so bad as compared toadding grounds to improve single endedsignaling.

Routing constraint: Pair signals need tobe routed together.Differential signal have certain

symmetry requirements that may poserouting challenges.


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Differential Signal Parameters

Voltage on line 1 = a

Voltage on line 2 = b Differential voltage d = a-b Common mode voltage c= (a+b)/2 Odd mode signal, o = (a-b)/2

Even mode signal, e = (a+b)/2 Signal on line 1 a = e+o Signal on line 2 b = e-o Useful relations; o = d/2; e = c

Line 1 Line 2

Reference


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8

Propagation Terms to Consider

Differential mode propagationCommon mode propagationSingle ended mode (uncoupled)

propagationThis is when the other line is not drivenbut terminated to absorbed reflections.

Transmission line matrixes will reflectthese modes.


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9

Differential Microstrip Example

Z0 Zse:=

Sse .0000ns

ft=Sse L00C00:=Zse .00000=Zse

L00

C00:=

Sc .1111ns

ft=Sc L00 L00

+( ) C00C00

( )

:=Zco mm .00000

=Zcomm

L00 L00+

C00C00:=

Sd .0000ns

ft=Sd L00L00( ) C00C00+( ):=

Zdiff .11111=Zdiff 0L00L00

C00C00+:=

inductance and

capacitance matrixes

C00

C00

C00

C00

L00

L00

L00

L00

Transmission

line

C00 C00:=C00 C00:=C00 .000000000-00

farad

in:=C00 .000000000

-11farad

in:=

L00 L00:=L00 L00:=L00 .000000000-0

henry

in:=L00 .000000000-0

henry

in:=

SE: single ended = uncoupled


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10

Differential Impedance

Coupling between lines in a pair alwaysdecreases differential impedanceDifferential impedance is always less

that 2 times the uncoupled impedanceDifferential impedance of uncoupled

lines is 2 times the uncoupled impedance.


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Propagation Velocities

For TEM structures, (striplines)Differential mode, Common Mode, andsingle ended velocities are the same

For Non TEM and Quasi-TEM structures

(microstrip)Differential mode, Common Mode, andsingle ended velocities and impedances arenot the same.

Common mode can be converted todifferential mode at a receiver and result ina differential signal disturbance.


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Example of Common Mode

Line 1 and line 2 have the same DC offset.

This is DC common mode.It can be defined as an average DC for timeduration of many UI cycles value as well.

Line1 and line 2 have the same AC offset

This is AC common mode AC common mode also result from time

differences (skew) between signal on line 1and line 2. This can result in AC common modeand differential signal loss. The following slide will be used to clarify the

above


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Differential Signaling Basics

For long channels, at GHz frequencies, signaltend look like sine waves.

The artificial offset common to line 1 and 2has an average of 1 and varies around thataverage by +/-0.1 in a period manor.

Voltages a and b are respective of signals on lines and0 0

We will use a GHz sine wave for the signal and offset defined below0

offseti .0 modti

ns

0

f ns,

.0+:= ramp wave centered around 0

ai sin 0 f ti( ) offseti+:= bi sin 0 f ti( ) offseti+:=


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Individual signalsPlot individual line voltages and offset voltage

0 .111 .000 .00 .000 .000 00

.000

.000

0

.000

.0000

ai

bi

offset i

ti

ns

Devices need to have enough common mode dynamic voltage rangeto receive or transmit the waveforms. In this case the signalsswing between -0.1 and 2.1.

The sine wave amplitude is 1 and peak to peak is 2. Signal a and b is what would be observed with 2 oscilloscope probes


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Differential Mode Signal

0 .111 .000 .00 .000 .000 00

0

0

0

0

a b

t

ns

Plot Differential voltage

The differential amplitude is 2 and peak to peak is 4which is 2 times the individual signal peak to peakamplitude.

Notice the distortions are gone.


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Common Mode Signal

The DC common mode signal is 1 The AC common mode signal is .2 v peak to peakSome may specifications may call this 0.1 v peak from the DCaverage

We will add this common mode to the signals a and b

Plot common mode voltage

0 0 0 0 0 0.11

.11

0

.00

ai bi+

0

ti

ns


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Add 150 ps skew to signal b

Plot individual line voltages and offset voltage

0 .111 .000 .00 .000 .000 00

.000

.000

0

.000

.000

0

ai

bi

offseti

ti

ns

Waveforms do not look so good. We even have what appears to be non-monotonic

behavior.


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Differential signal looks OK

0 .111 .000 .00 .000 .000 00

0

0

0

0

a b

t

ns

Plot Differential voltage

max a b( ) min a b( ) .0000=

However we lost differential signal amplitude. It used to be 4 peak to peak and now is

3.562.


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Common mode measurements are different

0 0 0 0 0 0

.00

0

.00

0

ai bi+

0

ti

ns

Plot common mode voltage

meana b+

0

0= maxa b+

0

mina b+

0

.1111=

max meana b+

0

max

a b+

0

mean

a b+

0

min

a b+

0

,

.0000=

Average is still 1. Peak to peak is 0.944 but peak is 0.504 AC common mode signals can be converted to differential


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PWB structures that introduce Skew

An escape froma BGA orconnector pinsintroduces

skew

This is anexample of

skewcompensation


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Bends introduce skew

Back to backbendscompensate for

skew fromfrequenciesbelow 2 GHz.

Back to backbendscompensate for

skew fromfrequenciesbelow 2 GHz.


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More Terms: Balanced and Unbalanced

Good Agilent Technologies article on balance

and unbalanced signalinghttp://we.home.agilent.com/upload/cmc_upload/tmo/d

Unbalanced signaling in reference to ground

Balanced signaling is referenced only to theother port terminal.

If each channel is identical, then this suggests avirtual AC ground between the two terminals. It

is often useful to allow this AC ground to be a DCvoltage to biasing devices.
http://we.home.agilent.com/upload/cmc_upload/tmo/downloads/EPSG084733.pdfhttp://we.home.agilent.com/upload/cmc_upload/tmo/downloads/EPSG084733.pdf


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Ethernet 10/100BASE-T example

TN0

TP050

50

50

50

TransformerFilter

Common-mode choke

Unbalanced Balanced


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Low Voltage Differential Signaling: LVDS 200MHz 500 MHz Range

Published by IEEE in 1995 Lacks robustness for GHz Signaling Well suite distributing system clocks Good noise margin Common mode impedance has wide range provide

buffer design flexibility Differential impedance is optimize around 100 Differential receiver switching thresholds are

tighter than for single ended logic.

Most device require external termination and biasresistors Does not have capacitance or package spec. This

severely limits GHz operation


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Current Mode Logic Emerging technology

No real spec yet but can infer operation fromspecs like PCI Express , Infiniband, USB,SATA, etc. Tx and Rx lines are separate

The Tx driver steers current between thedifferential terminals AC coupling between Tx and Rx with a series

capacitor provides common mode designflexibility Termination is in buffers. This may require

compensation or a band gap reference toinsure a tight resistance range.


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Example of Simple CML Differential Behavioral Circuit

Vcc

Vss

I_source

r_termn,C_term

r_termp,C_term

0 00 00 000

0

Data Pulses

0 00 00 000

.11

0

Data Waves

wave t( ) 0 epulse t( )

0

per

ns:=

Wavep t( )

Wavep t( ) 0r_termn balancep

Waven t td( ) 0

Waven t td( )r_termn balancen

PositiveTerminal

NegativeTerminal

This exponentdetermines wave

shape

This switchtime offset

Balance betweenfor FET switch

2

nd lectur

e


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Example of Sensitivities: I, balance, C

Vcc

I_source

More prominentfor faster edges


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Example of Sensitivities: Slew, Skew, R

Vcc

I_source

+/skew

R/F slew


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Serial Differential

GHz transmission will have many UIs ofdata in transit on the interconnect atany points in time.Hence it becomes useful to think of this

as serial data transmission.Often multiple single channels are

ganged in parallel to achieve even higher

data throughput.

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AC coupling issues

Series capacitors can build up charge

difference between differentialterminals for the following reasons.

Unequal numbers of zero and ones

Duty cycle (UI) distortion.The solution is to use a data code that isDC balanced.

8B10B (8 bit 10 bit) with disparity is onesuch code

Tight UI control is a basic requirementfor keeping the signal eye open

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Eye Diagram The eye diagram is a convenient way to represent

what a receiver will see as well as specifyingcharacteristics of a transmitter. The eye diagram maps all UI intervals on top of one

and other. The opening in eye diagram is measure of signal

quality. This is the simplest type of eye diagram. The are

other form which we will discuss later

Eye Diagram

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Creating eye diagram

Plot periodic voltage time ramps (sawtooth waves) on x verses the voltagewave on Y. Can be done with Avanwaves expression

calculator and can be saved in aconfiguration file.

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Create ramp with expression builder

Start ofrelative eyeposition

Time of eyestartUnit Interval

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Copy Ramp to X Axis

Use middle button to drag ramp toCurrent X-Axis

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Voltage and period volt-time ramp

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Clocking The one thing omitted in the suggests in the

previous slides on eye diagrams was the chopfrequency.We assumed it was UI. This is simple for

simulation. Time marches along and all signalsstart out synchronized in time. This is nottrue for real measurement since edges willsignificantly jitter and make it difficult todeterminate where the exact UI is positioned. Presently, there are basically two forms of

GHz+ clockingEmbedded clockingForwarded clocking

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Embedded clocking

This what is used in Fiber Channel, Gigabit

Ethernet, PCI Express, Infiniband, SATA,USB, etc. The clock is extracted from the data

There is requirement that data transitions are ata minimum rate. 8B/10B guarantees this. Wediscuss this in more detail later.

A phase interpolator is normally used to extractthe clock from the data. We discussed the phaseinterpolator in the clocking class. The phaseinterpolator is tied to the PCI Express-like jitterspec: Median and Jitter outlier.

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Jitter Median and Outlier Spec

Eye opening is defined from a stable UI.

Jitter median used to determine a stable UIIt is used as a reference to determine eye opening Jitter Outlier is used to guarantee limits of

operation

Jitter Median

Jitter outlier

Eye diagram

UI

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Forwarded Clocking The Tx clock is sourced and received down

stream. The clock is a Tx data buffersynchronized with the Tx data bits. A synchronization or training sequence on a

data line is used to adjust the receiver clockso that it is in phase synchronization with thedata. The caveat is that the actual data clock lags

the real data by a few cycles. The whole idea is that the jitter introduced

over these cycles would be smaller than thejitter associated with two the PLLs used toprovide base clocks for an embedded clockdesign.

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Aspects of AC coupling

We will explore issues with AC coupling with a

simulation example. First we will create a simple CML differential

model Next we will tie it to a differential

transmission line and a terminator. Assignment 7 is to reproduce these effects

with a HSPICE program. The outputAvanwaves with a power point story summary

what you will hand in. The basis for our work will be last semesters

testckt.sp deck

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Behavioral Data Model Example

12 bit of repeating data

010101 001001 v(t) data

UI = 500 psTr=Tf=100ps

.).)*(( tve

Rterm=50Cterm=0.25pf

Vswing = 800 mV

I=Vswing/(50||50)/2

Wave shape*

* Refer to first course

3rdle

ctur

e

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AC coupled Differential Circuit

nH0

nH0

nH0

nH0

. pf00

. pf00

. pf00 . pf00

ma11

n11

n00

.00gHz

/ mV1111

Vcc

+

-

VCR+

-

VCR

00

00

0000

AC coupling caps arenormally larger, butare scaled down to

illustrate commonmode effects

0 to 1V

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Top Level HSPICE CODE

Modified

Convenience

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No initial conditions on DC blocking caps 300 ns of simulation time! Cblkn pkg2_nb pkg2_n 1nf $ic=400mv

Cblkp pkg2_pb pkg2_p 1nf $ic=400mv 101010 101010 repeating 12 bit pattern

Differential

Single ended

Reproduce this at

package 2 (receiver)


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N l l fi d


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Not completely fixed

Initial voltage for D+ and D+ is not 0 so

there is a step response when the wavereaches the receiver.We can fix this by multiplying both n

and p control waves for the VCR(voltage controlled resistor) by 0 forthe first cycle.

This forces the DC solution at the otherend of the line to 0 volts differential.

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Insure both legs start at same voltage

Qualifying voltage

Qualifying voltagep control voltage

Qualifying voltagen control voltage

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R lt P tt d


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Results Pretty good

Differential

Single ended

Reproduce this at

package 2 (receiver)

May have to ignore

first 1-2 cycles

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l h b


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Now lets change bit pattern 100000001010

The pattern creates a DC charge to be built up in thecap The solution is to create a code that has equal

amount of 1s and zeros. This is the rational for 8bit10 bit (8b10b) coding

Differential

Single ended

Reproduce this atpackage 2 (receiver)

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C Off


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Crossing Offset

The crossing offset is the horizontal

line that is in the vertical center of theeye and it should be at 0 volts for adifferential signal.

The amount of offset is the average DCvalue. A simple approximation is oneminus the ratio of ones to zeros times

the received vswing/2.This does not included edge shape effects

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R f 5 d 6


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Repeat patterns of 5 ones and 6 zeros

000

0 00

0 .1111=

Approx. offset


Hint:start eyediagramat 200 ns


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12/4/2002

8b/10b encoding and background

Courtesy ofScott Gardiner, Intel

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8b/10b Si l S h


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8b/10b - Simple Scheme

The encoding is comprehended in a set oftables which conform to a set ofpredetermined rules

Helpful Hint: Complete tables that give all

the literal 10b encodings do exist- and theycomprehend all of the encoding rules

8 bits are encoded into 10 bits


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8b/10b Ch t C ti s


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8b/10b Character Conventions Both Data Characters and Special Control

Characters exist; (nomenclature: D.a.b &K.a.b)D/K = Signifies Data or Controla = 5 bit block to be encoded

b = 3 bit block to be encoded Set of Available Data and ControlCharacters

Data (D.a.b)

D0.0-D31.0, D0.1-D031.1, .... D0.7 D31.7All 256 Possible 8-bit Data characters (00 through FFHEX)

Control (K.a.b)K28.0 K28.7, K23.7, K27.7, K29.7, K30.7

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8b/10b DC b l i & Di it


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8b/10b - DC balancing & Disparity

Never more than 5 consecutive 1s or 0sallowed in a row (consecutively)..i.e. themaximum run rate is 5 to maintain a DCbalanced transmission.

This guarantees the lowest frequency tobe 1/10 of the max frequency. i.e. only 1decade data bandwidth required.

With 8b/10b, either positive (RD+) ornegative (RD-) disparity encoding ispossible

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8b/10b Disparity


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8b/10b - Disparity

Disparity is the difference between the

number of ones and zeros...positive andnegative disparity refer to an excess of onesor zeros respectively.

Note: neutral disparity is said to occur whenRD+ and RD- encoding are identical-meaningthey will eachhave the same number of onesand zeros (there are some exceptions)

A given sub-block or symbol can have an actualdisparity number of either a zero (neutral), +2or 2, though the Running Disparity is said onlyto be Positive, Negative or Neutral.

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8b/10b Running Disparity


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8b/10b Running Disparity

The Running or Current Disparity (a

binary value of + or -) is tracked by theTX/RX and is computed at every sub-block boundary and at each symbol

boundary. The value from one sub-block or symbol

is used with that of the next sub-block

or symbol to give a running orcurrent status.

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8b/10b Running Disparity Algorithm


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8b/10b Running Disparity Algorithm For a given encoding of a byte, the starting disparity

is what existed at the end of the previous symbol

The running disparity is then calculated first for the6 bit sub-block, comprehending the startingdisparity value;

The 6 bit sub block disparity valueis then used asthe starting disparity when the running disparitycalculated for the 4 bit sub-block

The running disparity for the entire 10 bit symbol isnow the sameas the running disparity found at theend of the 4 bit sub-block (and the runningdisparity at the beginning of the next symbol /6 bitsub-block is the sameas that found at the end ofthe this symbol)

Again, a given sub-block or symbol can have an actualdisparity number of either a zero (neutral), +2 or 2,though the Running Disparity is only said to bePositive, Negative or Neutral.

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b/ b l l l h


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8b/10b - Running Disparity Calculation Algorithm:

Assumptions: The 8b to 10b encoding has

already been done; A current disparity value isalready assumed Process: Calculate the disparity for the

leftmost 6 bits first, keeping in mind the

current disparity value before entering thealgorithm. Then calculate the disparity for therightmost 4 bits keeping in mind the disparityvalue determined after analyzing the previous 6bits. The disparity for both the 6-bit and the4-bit blocks should be calculated as follows:

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8b/10b R i Di it C l l ti M th d


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8b/10b - Running Disparity Calculation Method Method:

If # of 1s > 0s

Disparity = Positive (1)Else if # of 0s > 1s

Disparity = Negative (0)Else if 6-bit = 000111

Then Disparity = Positive (1)

Else if 6-bit = 111000Then Disparity = Negative (0)

Else if 4-bit = 0011Then Disparity = Positive (1)

Else if 4-bit = 1100Then Disparity = Negative (0)Else Disparity = Disparity (if none of the above, then the disparity

value doesnt change)

Note: Assuming a encoding, more1s across the entire 10b code

yields positive

disparity, more 0s yields negative

disparity, and even #s of 1s and

0s yields neutral disparity

(i.e. disparity is the same as it wasbefore).

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8b/10b Di it & E di E l


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8b/10b - Disparity & Encoding Example:

Transmitter keeps running track of current

disparity (it is either RD, RD+ or neutral)Neutral means the disparity tracker keeps theprevious RD- or RD+ value

A Running Disparity of RD+ is always followedby an RD- encoding and vice versa

If Running Disparity is RD+, the following isencoded for the data byte F1:

HGF EDCBA abcdei fghj11110001 1000110111(RD- encoding)

If Running Disparity is RD-, the following isencoded for the data byte F1:

HGF EDCBA abcdei fghj111 10001 100011 0001(RD+ encoding)

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8b/10b Di it & E di E l


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8b/10b - Disparity & Encoding Example:

Note that the number of ones and zeros in the

currently chosen encoding works to balance out theoffset in the number of ones and zeroes (tracked bythe Running Disparity value) from the previousencoding

I.E. : Dont confuse the definition of Positive Disparity with

the RD+ encoding choice!Positive Disparity means there is a current running total ofmore onesthanzeros!Thus, an RD+ encoding generally has more zeros thanones!

Also note that it is possible that the 4-bit sub-block

of a RD- or RD+ symbol encoding can yield a negativeor positive disparity, respectively thus forcing morethan one RD- encoding to be used consecutively

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Summary: Example conversion


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Summary: Example conversion

HEX Data Byte (8b) to be Encoded

OR

Binary Data Byte (8b) to be Encoded

10b Encoded symbol (RD-) 10b Encoded symbol (RD+)

F1

100011 0111 100011 0001

1111 0001

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P ssibl P tt ns


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Possible Patterns Repeating Comma [K28.5] Pattern (RD- followed by

RD+):001111 1010 110000 0101 001111 1010 110000 0101(RD-) (RD+) (RD-) (RD+)

6 bit encoding starts with an RD- and uses an positivedisparity encoding.6 bits encoding yields an RD+..4-bitencoding starts with a RD +4-bit encoding picks a negative

(or neutral encoding) and thus yields a neutral and thuskeeps the RD+. Checks out.

Low Frequency Pattern?? (D30.0 (RD- followed byRD-)

011110 0100 011110 0100 011110 0100 011110 0100

(RD-) (RD-) (RD-) (RD-)100001 1011 100001 1011 100001 1011 100001 1011

(RD+) (RD+) (RD+) (RD+)

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Possible Patterns


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Possible Patterns High transition density/frequency pattern:

D21.5 (RD- followed by RD+)

101010 1010 101010 1010 101010 1010 101010 1010(RD-) (RD+) (RD-) (RD+)

Low transition density pattern:K28.7 (RD-) & D24.3 (RD+) (although K28.7 is reserved....)

001111 1000 001111 1000 001100 1100 001111 1000 001100 1100(RD-) (RD+) (RD-) (RD+)D24.6 (RD-) & D24.6 (RD+)1100110110 0011000110 1100110110 0011000110

(RD-) (RD+) (RD-) (RD+)

Composite pattern:D30.7 (RD-) & D13.7 (RD-)011110 0001 101100 1000 011110 0001 101100 1000

(RD-) (RD-) (RD-) (RD-)

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References


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References

Infiniband Architecture Release Specification 1.0

October 24, 2000, Volume 2, Section 5.2x (beginning with page 66) Franaszek & Widmer (IBM) Patent # 4,486,739

December 4, 1984, Byte Oriented DC Balanced 8B/10B PartitionedBlock Transmission Code

3GIO Architecture Specification- Key Developer Draft

August 21, 2001, Appendix C, pg148-154 ANSI X3.230-1994, clause 11 (and also IEEE 802.3z, 36.2.4).

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Other sources of common mode


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Other sources of common mode

A DC voltage will build up across the blockingcapacitor if the charge and discharge is not equal.

We have see this can happen if the number of bits isunbalance.

Another source of imbalance is possible if the dutycycle of the one and zeros is not 50%.

This can happen in two waysThe time for a one differs from that of a zero. This can becaused by edge jitter.The rising time and falling time are miss matchedOn the next slide we will take our example with101010101010 pattern and change the rise time to 50 ps andfall time to 150 ps for the single ended signals

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CM offset from tr/tf mismatch


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CM offset from tr/tf mismatch


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Class2!10!11 12 Differential Signaling