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7/31/2019 Chuong 4 Ngoai Vi Va Lap Trinh Asm
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201 ASPCu trc ngoi vi v lp trnh iu khin
bng ngn ng Assembly
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Mc tiu
Cc kin thc t c sau lp hc: Cu trc ca ngoi vi v cc thanh ghi iu
khin c lin quan.
Khi to cc ngoi vi. Phng php lp trnh cho ngoi vi:ngt(Interrupt) v hi vng (Polling).
Vit chng trnh ng dng iu khinngoi vi.
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Cc kin thc cn c
L tng, bn nm bt c nhngkin thc sau: Lp trnh Assembler
Tp lnh c bn dng Mid-Range T chc b nh d liu v b nh chng
trnh
Mi trng lm vic MPLAB IDE
S dng cng c MPLAB ICD2 caMicrochip
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Mc lc
n li cc kin thc v cu trc, tp lnhca dng Mid-Range v b cng c PIC Ngt trong vi iu khin PIC dng Mid-
Range.
Thc hnh: Vit chng trnh ngt. Gii thiu v ngoi vi Cc cng vo/ra Cc b nh thi (Timer).
Timer0 Timer1
Thc hnh v Timer1 Timer 2
Thc hnh v Timer2
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Mc lc (tt.)
Module CCP (Capture/Compare/PWM) Thc hnh: PWM v So snh u ra B so snh tn hiu tng t B chuyn i tn hiu tng t sang s
(ADC) Thc hnh: ADC
Module giao tip UASART
Module giao tip I2C Thc hnh: giao tip vi cm bin nhit qua
module I2C
Tng kt
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n li v cu trc v cccng c pht trin ca dng
Mid-Range
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S khi dng PIC Mid-Range
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B nh chng trnh
Dung lng ti a: 8K words (8k x 14bits/word)/ 1byte =
14Kbytes b nh
Reset Vector: 0000h
B m chng trnh (PC) si n a ch ny khi reset
Interrupt Vector: 0004h
B m chng trnh (PC) s
i n a ch ny khi ngt xyra.
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PC v Stack
B m chng trnh 13 bit. PCL Kt qu ALU (8-bits)hoc OPCODE (11-bits)
PCH Cc bit chn trangca b nh chng trnh
Cp nht t PCLATH Xc nh trang hin ti
ca b nh chng trnh
8 nh Stack Lu gi tr ca
b nh chng trnh (PC) PUSHES
CALL/Interrupt POPS
RETURN, REFIE, RETLW
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S b nh d liu
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Cc thanh ghi chc nng c bitSFRs
Khi nim v thanhghi chc nng
c truy xut
tng t cc thanhghi khc
Mt vi thanh ghi c
trong tt c cc bank(PCLATH, INTCON, ..)
Slide 11Bin son: Phm Nguyn Huy Cng
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Thanh ghi STATUS
Bao gm
Trng thi ktqu cc phpton ca ALU
Trng thi
RESET Cc Bit chn
bank cho bnh d liu
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Tp lnh PIC16 35 lnh word n
Tt c u c thc thi trong mt chu k lnh, trlnh r nhnh
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Cc cng c c sdng
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MPLAB IDE
MPLAB IDE (Intergrated Deverlopment Environment) Tch hp cc cng c pht trin ca Mircochip v cacc hng khc.
Mi trng son tho chng trnh
Bin dch chng trnh Hp dch chng trnh hp ng
H tr m phng, chy debug ngay trn mch (In-Circuit Debugger) s dng cc cng c pht trin
Np chng trnh Lin kt vi phn mm PROTEUS
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MPLABIDE
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ICD 2( In Circuit Debugger)
MPLABIDE l cng c h np chngtrnh v g ri chng trnh theo thigian thc.
c/ghi ln b nh v vng EEDATA ca PIC Np cc bit cu hnh
G ri theo thi gian thc
Xa b nh chng trnh
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PICDEM 2 Plus Board
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Ngt (Interrupt)
Ph h t (I t t)
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Phng php ng t (Interrupt) vhi vng (Polling)
Thng thng chng ta mong mun b x l thc hinmt cng vic no khi c mt s kin xy ra
C 2 phng php kim tra s xut hin ca mts kin
Hi vng (Polling): Kim tra lin tc ti cc thi im khc nhau ca
chng trnh ng dng Ngt (Interrupt):
Ngt chng trnh chnh v bt u mtchng trnh phc v s kin ngt (ISR) khi skin ngt xy ra
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Kim tra vng
bsf PORTA,1 ;Set bit 1 ca;ca PORT A
btfss INTCON,TMR0IF ;Kim tra c;ngt timer 0;trong thanh ghi
;INTCONv b;qua lnh k;tip nu bit;ny c set
Goto $-1 ;quay tr li
;lnh pha trn
bcf PORTA,1 ;Xa bit 1 caPORT A
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Ngtreset code 000h
goto start;===========================
int_vector code 004h
refie ;tr li t;ngt
;===========================
main codestart ;nhn khi u main
code
end
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Cho php ngt xy ra
Vi iu khin phi c thng bo rngcc ngt s c dng Mt s cc thanh ghi c cha cc bit iu
khin vic cho php ngt xy ra hay khng: Thanh ghi iu khin ngt (INTCON)
Thanh ghi ngt ngoi 1 (PIE1)
Thanh ghi ngt ngoi 2 (PIE2)
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Cc iu kin Logic ca ngt
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Th h hi INTCON
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Thanh ghi INTCON
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Kch hot ngt ni
INTCON
GIE
Interrupt detectedon RB0/INT Pin!!
0
goto $ address
Stack
0 0 0 0 0 0 011
INTE INTF
1
Int_vect CODE 004h;xo c ngt ngoi
bcf INTCON,INTF
retfie
Main CODEStart
; khi to INTCONclrf INTCON
;kch hot ngt ngoi
;trn chn INT RB0 chn 33
bsf INTCON,INTE
;kch hot ngt tngbsf INTCON,GIE; lp ti chgoto $
Program Counter
goto $ address
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Ngt Ngoi vi
2 thanh ghi cho php ngt ngoi vi Thanh ghi ngt ngoi 1 (PIE1)
Thanh ghi ngt ngoi 2 (PIE2)
2 thanh ghi hin th cc yu cu ngtngoi vi cho mi ngt (cc c) Thanh ghi yu cu ngt ngoi 1 (PIR1)
Thanh ghi yu cu ngt ngoi 2 (PIR2)*C s c thit lp ngay c khi
ngt khng c cho php27Bin son: Phm Nguyn Huy Cng
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Thanh ghi PIE1 v PIR1
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Thanh ghi PIE2 v PIR2
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Kch hot mt ngt ngoi vi (Timer1)
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Tr ngt
Tr ngt Thi gian t s kin ngt cho ti khi thc
thi lnh ti a ch 0004h
Ngt ng b (ngt ni) Tr khong 3 chu k my ( Tcy)
Ngt khng ng b (ngt ngoi) Tr khong 3 3.75 chu k my
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Lu trng thi hot ng trc
Trong khi ngt Ch c gi tr ca b m chng trnh l
c lu li ( trn stack) Gi tr ca cc thanh ghi c th b thay i
sau khi phc v ngt Cc thanh ghi cn c lu li
Thanh ghi W
Thanh ghi STATUS PCLATH Cc thanh ghi c nh ngha bi ngi
dng
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u tin ngt
Vi iu khin PIC dng Mid-Range t ttc cc s kin ngt cng mt mc u tin
Ngi s dng phi lm cc vic sau: Xc nh ngun ngt
Xc nh trnh t phc v ngt
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V d v u tin ngt
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Bi thc hnhNgt
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Ngt
Mc ch ca phn ny Lm th no thit lp v khi ng mt
ngt trong mt vi iu khin PIC dng Mid-Range
Lm quen hn vi MPLAB IDE, PICDEM2Plus v ICD2
Xy dng mt project
S dng IDC thit lp mt im ngt
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Lu gii thut
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Th nghim c th
Cng tc S3 c ni vi chn RB0/INTtrn PORTB Thanh ghi nhn m lu s ln m
S3 c nhn S dng MPLAB v ICD xc lp im
Breakpoint trong chng trnh, quan sts thay i gi tr ca thanh ghi nhn
m
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Cn nh
Chc nng cc bit ca thanh ghi INTCON u cm J6 phi c tho ra chn INTEhot ng
Vit chng trnh con c nhim v chng
rung (debounce) Lc b tn hiu to ra do nhng rung ng c
hc ca S3
Lm th no xc lp mt im Breakpoint vca s quan st (Watch Window) trongMPLAB
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Bi Gii Lab Ngt
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NGOI VI
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N i i d PIC Mid
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Ngoi vi ca dng PIC Mid range
Cc cng I/O Cc b timer (0,1,2) CCP (Capture/Compare/PWM)
Cc b so snh B chuyn i ADC Truyn thng AUSART Giao tip ni tip
IC v SPI
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Ln n 35 ng vo/ra hai chiu- Nhiu chn c kt hp vi cc chc nngngoi vi
Kh nng li dng cao- Ln n 25mA
Thao tc trc tip vi tng chn ch trong vng 1chu k lnh
Hu ht cc I/O u c chc nng bo v ESD Mc nh khi reset- Cc chn Analog vn gi chc nng Analog- Cc chn Digital l cc chn Input
Tng quan v I/O
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Mi PORTx (A,B,C,D,E) u c mt thanh ghi iu khinTRISx
Thanh ghi PORTB:
D LIU
1= chn tng ng ca PORTB s l INPUT
0= chn tng ng ca PORTB s l OUTPUT
Cc thanh ghi TRISx - PORTx
44
D liuCu hnh hng d liu
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Cu Hnh Ng Vo Analog
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C 2 cch cu hnh ng vo Analog l cc ngDigital:
1) S dng thanh ghi Analog Select (ANSEL vANSELH) Cho loi c nhiu hn 8 chn Analog
Hoc2) S dng thanh ghi iu khin ADC1(ADCON1)
Cho loi c 8 chn Analog hoc t hn
Cu Hnh Ng Vo Analog
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Cu Hnh Ng Vo Analog
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Khi to cc chn I/O
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Khi to PortB:- T RB4 n RB7 l Digital Inputs- T RB0 n RB3 l Digital Outputs
Khi to cc chn I/Odng Digital
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Thit lp Interrupt v Pull up cho
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Cc chn ca PortB u c bng ty chn cho Interrupt-on-change v Weak pull-up (in tr ko ln)Thanh ghi Weak pull-up ca portB(WPUB)
Thit lp Interrupt v Pull-up choPORTB
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Cc b nhthi (Timer)
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Timer c dng cho nhiu ng dng nh:- nh thi gian khi ng s kin- m s kin
- To xung clock
TIMER
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SO SNH CC TIMER
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SO SNH CC TIMERTIMER0 TIMER1 TIMER2
Kch thc thanhghi
8-bit (TMR0) 16-bit(TMR1H:TMR1L)
8-bit (TMR2)
Xung clock( Ni) Fosc/4 Fosc/4 Fosc/4
Xung clock(Ngoi) Chn T0CKI Chn T0CKI hay bdao ng Timer1
(T1OSC)
Khng c
Clock Scaling
Available ( phngii)
Prescaler 8-bit
(1:21:256)Prescaler 3-bit
(1,2, 4, 8)Prescaler
(1:1,1:4,1:8)
Postcaler
(1:11:16)
S kin xy ra ngt
v v tr ca c ngt
Khi c trn
FFh00h(TMR0IF trong
INTCON)
Khi c trn
FFFFh0000h(TMR1IF trong
PIR1)
TMR2 ph thuc
vo PR2(TMR2IF) trong
PIR2)
C th nh thc"PIC khi ang hotng ch ng
(sleep)
NO YES NO
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S khi Timer 0
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S khi Timer 0
scaled clockTMR0
T0CKI
pin
Fosc/4
prescalerWatchdog Timer
ng b
WDT out
Thanh ghi OPTION
RBPU INTEDG TOCS TOSE PSA PS2 PS1 PS0
Chn ngun xungchoTMR01 = TOCK1, 0 = Fosc/4
Chn cnh ngun xung1 = tngTMR0 khi c chuyn mc high to low0 = increment khi c chuyn mc low to high
Ch nh Prescaler1= gn cho WDT0= gn cho Timer 0
Bit la chn b chia
PS2 PS1 PS0TMR0RATE
0 0 0 1:2
0 0 1 1:4
0 1 0 1:8
0 1 1 1:16
1 0 0 1:32
1 0 1 1:64
1 1 0 1:128
1 1 1 1:256
8
DATA BUS
S khi Timer 0
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scaled clockTMR0
T0CKI
pin
Fosc/4
B chiaWatchdog Timer
synchronize
8
DATA BUS
Timer 1 c th c ln ghi
TMR0IF
INTCON register
Nu s dng xung ngoi (TOCKI) th n s c vi xung ni
S khi Timer 0
Timer 1 trn t FF sang 00 khi c s c set
S khi Timer 0
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S khi Timer 0
S khi Timer 0
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S khi Timer 0
PSA=0
PSA=1
Khi to gi tr cho Timer 0
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Khi to gi tr cho Timer 0S tng ca Timer 0
C bo trn
C ngt ny s t ln 1 khi Timer 0 trn,k c khi cc ngt b kha
La chn xung clock cho Timer 0
(Xung ngoi hay ni)
Xc lp b chia tn s(presscaler) cho Timer0
Gi tr b chia
=1 :16
Xa gi tr m ca Timer 0 (xa thanh ghi TMR0)
Xa c ngt Timer 0
Khi to b chia tn s cho Timer0 l 1:16 bng cch acc gi tr thch hp vo thanh ghi OPTION
Ngt TMRO b kha, lm tun t trn bit c (TMR0IF)
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S KHI TIMER 1
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S KHI TIMER 1
T1CKIpin
T1OSCT1OS0
T1OSI
prescalersynchronize
Fosc/4
TMR1H TMR1L
Enable
TMR1ONThanh ghi T1CON
Chn ngun xung Clock1 = External (T1CKI)0 = Internal (FOSC/4)
LP Oscillator Enable1 = T1OSC selected0 = T1CKI can be used
T1CKPS1 T1CKPS0 T l
1 1 1:8
1 0 1:4
0 1 1:2
0 0 1:1
Timer1 On1 = Kch hot Timer1
T1GINV TMR1GE T1CKPS1T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
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S KHI TIMER 1
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S KHI TIMER 1
Tn s thch anh /4
Prescaler Synchronize
Thanh ghi iu khin Timer 1 (T1CON)
T1CKI
T1OSI
T1OS0
59
ng b xung m ng vo Timer11 = khng cn ng b xung ng vo0 = ng b xung clock ng vo vi xungclock bn trong (FOSC/4)
Cho php xung m vo Timer 1Cho php o xung ng vo Timer1
T1CKPS1T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ONT 1GINV T MR1GE
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Khi to ngt Timer1
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Main Code
Start
;khi to bng cch xo c ngt Timer1
banksel PIR1
bcf PIR1, TMR1IF
;kch hot ngt Timer1
banksel PIE1bsf PIE1, TMR1IE
;kch hot ngt tng v ngt ngoi vi
bsf INTCON, PEIEbsf INTCON, GIE
Khi to ngt Timer1
INTCON
PIE1
1
GIE PEIE
TMR1IE
1
1
PIR1
TMR1IF
0
TMR1H
1 1 1 1 1 1 1 10 0 0 0 0 0 0 0
TMR1L
1 1 1 1 1 1 0 11 1 1 1 1 1 1 01 1 1 1 1 1 1 10 0 0 0 0 0 0 0
1
KHI TO NGT TIMER 1
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KHI TO NGT TIMER 1
Bit ng vo xung clockca b chia(T1CKPS)
Bit cho php Timer 1dao ng (T10SCEN)
Bit la xungclock ngun(TMR1CS)
TMR1 ON
Xa thanh ghi TMR1
Xa c ngt TMR1IF trong thanh ghi PIR1
Khi to thanh ghi T1CON cho
Bt Timet 1
Kim tra c ngt lien tc
TRN NH !!
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Bi tp thchnh TIMER 1
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Bi tp thc hnh Timer 1
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Bi tp thc hnh Timer 1
Mc ch ca th nghim ny l lm quenvi s vn hnh ca Timer
V
Tng kinh nghim trong vic cho phpngt cc thit b ngoi vi
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Gii thut
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Gii thutChng trnh ngt
Lu trng thi
Xa IF
Np Timer 1
Chp tt LED 0
C
Khng
5 ln ?
Tr v trng thi
Chp tt LED 3
Chng trnh chnh
Vng lp chnhNOP
Khnglm g
Cho php ngt Timer 1,
Cho php ngt
Cho php ngt thit b ngoi vi
Khi to Timer1
Ngun xung clock
B chia tn s
Np gi tr u cho thanh ghi Timer1 ngt xy ra saumi
100 000 chu k lnh
Khi to PORTB
Thot
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Lab Timer1
Yu cu- Thit lp Timer1 ly xung nhp t Fose/4- Thit lp gi tr b chia trc (pre-scaler)ca Timer1 l 1:2- a gi tr 0x3CB0 (65,536 50,000) vo thanh ghi m caTimer1- Khi ng Timer1- Cho php ngt Timer1, ngt ton cc v ngt ngoi vi hot ng
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Bn cn bit
- Hot ng ca cc thanh ghi INTCON, T1CON1, TMR1H,TMR1L v PIE1
-Vi gi tr 0x3CB0 v pre-scale cho 2, Timer1 s trn sau100.000 chu k
- Lp trnh ng dng trong chng trnh ngt o trng
thi ca LED
Li gii cho Timer 1 Lab
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;chn ngun xung clock,thit lp pre-scale vi t l 1:2;Np gi tr 3CB0 H vo Timer1 v cho Timer1 hot ng
;************************************************************************
mov1w 0x3C ; ### gi tr u cho TMR1L v TM1Hmovwf TMR1H ; ###movlw 0xB0 ; ###movwf TMR1L ; ###
bsf T1CON, T1CKPS0; ### nh dng prescale cho 2
bsf T1CON, T1CKPS1 ; ###bsf T1CON, TMR1CS ; ### nhn ngun xung clock t Fosc/4bsf T1CON, TMR1ON ; ### TMR1 bt u hot ng
;;************************************************************************
; Cho php ngt Timer1, ngt ton cc v ngt ngoi vi hot ng;************************************************************************
bsf STATUS, RP0 ; ### ch ti BANK1bsf PIE1, TMR1IE ; ### cho php ngt TMR1bsf INTCON, GIE ; ### cho php ngt ngoi vibsf INTCON, PEIE ; ### cho php ngt ton ccbcf STATUS, RP0 ; ### tr v bank0
Li gii cho Timer 1 Lab
S khi Ti 2
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S khi Timer2
Prescaler1:1, 1:4, 1:16
COMPARATOR
TOUTPS3TOUTPS2 TOUTPS1TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Postscaler
1:1 1:16
Fosc/4
Timer2 ON1 = Timer2 enabled
T2CKPS1 T2CKPS2 Scale
0 0 1:1
0 1 1:4
1 X 1:16
TMR2 TMR2OUTPUT
PR2
Timer2 Control Register (T2CON)
S khi Timer2
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S khi Timer2
69
Prescaler1:1, 1:4, 1:16
COMPARATOR
TOUTPS3TOUTPS2 TOUTPS1TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Postscaler
1:1 1:16
Fosc/4
Timer2 ON1 = Timer2 enabled
T2CKPS1 T2CKPS2 Scale
0 0 1:1
0 1 1:4
1 X 1:16
TMR2
TMR2
OUTPUT
PR2
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 SCALE
0 0 0 0 1:1
0 0 0 1 1:2
0 0 1 0 1:3
0 0 1 1 1:4
0 1 0 0 1:5
0 1 0 1 1:6
0 1 1 0 1:7
0 1 1 1 1:8
1 0 0 0 1:9
1 0 0 1 1:10
1 0 1 0 1:11
1 0 1 1 1:12
1 1 0 0 1:13
1 1 0 1 1:14
1 1 1 0 1:15
1 1 1 1 1:16
Thanh ghi iu khin Timer2 (T2CON)
Bin son : Phm Nguyn Huy Cng
S khi Ti 2
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S khi Timer2
Thanh ghi iu khin Timer2 (T2CON)
70
Khi to Timer2
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Khi to Timer2
;cm ngt Timer2 trong thanh ghi PIE1.
;Xa c ngt TMR2IF trong thanh ghi PIR1banksel PIE1bcf PIE1,TMR2IEbanksel PIR1bcf PIR1,TMR2IF
;Khi to gi tr thanh ghi T2CON Postscaler = 1:15,;Prescaler = 1:16, Timer2 ngng hot
ngmovlw b10000000movwf T2CON
;Xa thanh ghi TMR2banksel TMR2clrf TMR2
;Khi to cc gi tr cho thanh ghi PR2banksel PR2movlw b10000000mowf PR2
;Timer2 bt u m lnbanksel T2CONbsf T2CON,TMR2IF
;cm ngt Timer2, hi vng c ngt caTimer2
btfss PIR1,TMR2IFgoto $-1 71
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Bi tp thc hnhTimer2
72Bin son: Phm Nguyn Huy Cng
Lab Timer2
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Lab Timer2
Yu cu- Chn ngun xung clock cho Timer2- Thit lp t l b chia tn s trc(prescaler)- Thit lp t l b chia tn s sau(postscaler)
- Cho Timer2 chy- Khi to ngt ca Timer 2, cho phpngt xy ra.
73
Gii thut
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Gii thut
Np gi tr bn ucho PORTB
Set up Timer2
Period,Prescaler,Postscaler
Cho php ngt
NOP
Chng trnh chnh
Lu cng vic chnh
Tng b mTimer2 ngt
Xut 3 bit trng s thpca b ra LED
Quay v cng vic chnh
Kt thc
Chng trnh ngt
Chi tit Lab Timer2
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Chi tit Lab Timer2
Yu cu
Thit lp t l prescaler ca Timer2 l 1:4
Thit lp t l postscaler ca Timer2 l 1:13 Cho Timer2 chy
Thit lp gi tr hai bit GIE and PEIE trong thanhghi iu khin ngt (INTCON)
Cho php ngt Timer2 (trong thanh T2CON)
75Bin son: Phm Nguyn Huy Cng
Bn cn bit
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Bn cn bit
Nhng thanh ghi chc nng c bit c lin quan trong
bi thc hnh ny l: INTCON (iu khin ngt)
PIE1.. (Cho php ngt ngoi vi 1)
PR2...(Thanh ghi n nh chu k cho Timer2)
T2CON..( iu khin Timer2)
Vi gi tr c thit lp trong thanh ghi PR2 l 250,
prescaler bng 4, postscaler bng 13, sau 13 ms Timer2 sngt (khong 1/80 second), vi tn s dao ng 4 MHz (Fosc/4= 1Mhz )
76Bin son: Phm Nguyn Huy Cng
Bi gii cho Timer2 Lab
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Bi gii cho Timer2 Lab
; nh cu hnh Timer2 prescaler =4, PR2 = 250, postscaler = 13 v cho php;Timer2 on
BANKSEL T2CON ; chn bank cha thanh ghi T2CON
movlw 0x60 ; ### set TMR2 postscaler = 1:13
movwf T2CON ; ###
bsf T2CON, T2CKPS0 ; ### set TMR2 prescaler = 1:4
bsf T2CON , TMR2ON ; ### bt TMR2
; cho php ngt Timer2, ngt ton cc v ngt ngoi vi
bsf STATUS,RP0 ; tr n BANK1
bsf PIE1,TMR2IE ; ### cho php ngt TMR2
bsf INTCON,PEIE ; ### cho php ngt ngoi vibsf INTCON,GIE ; ### cho php ngt ton cc
bsf STATUS,RP0 ; quay v BANK0
77Bin son: Phm Nguyn Huy Cng
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CAPTURE/COMPARE/
PWM MODULE
78Bin son: Phm Nguyn Huy Cng
Tng quan v Capture/ Compare/
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Tng quan v Capture/ Compare/PWM (CCP)
Bt s kin (Capture)
Xc nh khong thi gian tn ti ca mt s kin bnngoi c phn nh thng qua mt ng vo ca vi iu khin
So snh (Compare)
Thay i trng thi ca mt chn ng ra hoc thc hin ccthao tc trong mt chng trnh ngt sau mt khong thigian nht nh
iu ch rng xung (Pulse Width Modulation -PWM)
To ra dng xung vung c duty-cycle thay i c ti
mt tn s xc nh ng ra
Cung cp nhng tnh nng to s thun li cho vickt ni vi nhng dng mch iu khin cu
Module CCP c mi lin h cht ch vi Timer1 v Timer2
79Bin son: Phm Nguyn Huy Cng
Tng quan v Capture/Compare/
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Tng quan v Capture/Compare/PWM (CCP)
CaptureXc nh khong thi gian tn ti ca mt s kin bnngoi c phn nh thng qua mt ng vo ca vi iukhin
CCP MODE TIMER RESOURCE
Capture Timer 1
So snh Timer 1
PWM Timer 2
- To ra dng xung vung ng ra ti mt tn sxc nh- Cung cp nhng tnh nng ni bc cho kh nng linkt ni
Module CCP c mi lin h cht ch vi Timer1
v Timer280Bin son : Phm Nguyn Huy Cng
Thanh ghi iu khin CCP
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Thanh ghi iu khin CCP
Thanh ghi iu khin CCP1P1M P1M0 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
BIT CHC NNGCCP1M
nh cu hnh hot ng cho module nh: ng voCapture, ng ra so snh, hoc PWM
CCP1 Thit lp rng xung iu ch: 2 Bit thp (8 bit caoc cha trong thanh ghi CCPR1L)
P1M nh cu hnh ng ra ca module PWM. Cc bit chcnng ny ch c nhng module ECCP (EnhancedCCP), cho php cc ng ra c cu hnh dng cuhoc na cu
81Bin son : Phm Nguyn Huy Cng
Thanh ghi iu khin CCP
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Thanh ghi iu khin CCPThanh ghi iu khin CCP1
P1M P1M0 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCPxM3 CCPxM2 CCPxM1 CCPxM0 La chn MODE CCP
0 0 0 0 Capture/ so snh/ PWM off (resets CCP modlue)
0 0 0 1 Khng dng
0 0 1 0 Ch so snh, ng ra o
0 0 1 1 Khng dng0 1 0 0 Ch Capture, mi cnh xung
0 1 0 1 Ch Capture, mi cnh ln
0 1 1 0 Ch Capture, mi cnh ln th 4
0 1 1 1 Ch Capture, mi cnh ln th 16
1 0 0 0 Ch so snh, ng ra ln mc cao
1 0 0 1 Ch so snh, ng ra xung mc thp
1 0 1 0 Ch so snh, Ngt bng phn mm to ra
1 0 1 1 Ch so snh, xung Trigger c bit to ra
1 1 X X Ch PWM82Bin son : Phm Nguyn Huy Cng
Ch Capture
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p
CCPx
TMR1H TMR1L
CCPRxH CCPRxL
Prescaler1, 4, 16
Edge Detectand
System Clock (Fosc)
P1M1 P1M0 CCP1X CCP1Y CCP1M3CCP1M2CCP1M1CCP1M0
CCPxCON
CCPxIF in PIRx
Single Buffered
83Bin son: Phm Nguyn Huy Cng
Ch Capture
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Ch Capture
CCPx
TMR1H TMR1L
CCPRxH CCPRxL
Prescaler1, 4, 16
Edge Detectand
System Clock (Fosc)
P1M1 P1M0 CCP1X CCP1Y CCP1M3CCP1M2CCP1M1CCP1M0
CCPxCON
CCPxIF in PIRx
Single Buffered
CCPxM3 CCPxM2 CCPxM1 CCPxM0 MODE
0 1 0 0 Bt s kin khi xung ng vo c mt cnh xung
0 1 0 1 Bt s kin khi xung ng vo c mt cnh ln
0 1 1 0 Bt s kin cnh ln th 4
0 1 1 1 Bt s kin cnh ln th 16
84Bin son : Phm Nguyn Huy Cng
Khi to Capture
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p
Pht hincnh ln
;Tt module CCPbanksel CCP1CONclrf CCP1CON
;Tt Timer1bcf T1CON,TMR1ON
;Xa gi tr m ca Timer1clrf TMR1Hclrf TMR1L
;Cm tt c cc ngt;ca module CCP
bcf PIR1,CCP1IFbanksel PIE1bcf PIE1,CCP1IE
;Thit lp chn CCP1 l inputbsf TRISC,2
;Thit lp ch bt s kin: bt s ;kin cnh ln th 4
banksel CCP1CON
movlw b00000110movwf CCP1CON
;Bt Timer1bsf T1CON,TMR1ON
;hi vng c ngtbtfss PIR1,CCP1IFgoto $-1
85Bin son: Phm Nguyn Huy Cng
Ch so snh
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TMR1H TMR1L
SO SNHTMR1H:TMR1L
= CCPRxH:CCPRxL
CCPRxH CCPRxL
YES
NO
86Bin son : Phm Nguyn Huy Cng
Ch So snh
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Ch So snh
YESYES CCPx
Special Event Trigger
CCPxIF in PIRx
OUTPUT
LOGIC
P1M1 P1M0 CCP1X CCP1Y CCP1M3CCP1M2CCP1M1CCP1M0
TMR1H TMR1L
COMPARATORDoes
TMR1H:TMR1L =
CCPRxH:CCPRxL??
NO
CCPRxH CCPRxL
CCPxM3 CCPxM2 CCPxM1 CCPxM0 MODE
1 0 0 0 Set ng ra (CCPxIF c set)
1 0 0 1 Xa ng ra (CPPxIF c set)
1 0 1 0
Nhy vo chng trnh ngt x l
(set c ngt CCPxIF, khng c s kin xyra chn CCP1)
1 0 1 1Xy ra cc s kin khc: c CCPxIF cset, module CCP1 s reset Timer1 (hocTimer 2) v bt u thc hin chuyn iA/D.
87Bin son : Phm Nguyn Huy Cng
Khi to ch so snh
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;Tt module CCPbanksel CCP1CONclrf CCP1CON
;Tt Timer1bcf T1CON,TMR1ON
;Xa gi tr m ca Timer1clrf TMR1Hclrf TMR1L
;Cm ngt CCP1;xa tt c cc c ngt
banksel PIE1bcf PIE1,CCP1IEbanksel PIR1bcf PIR1,CCP1IF
;thit lp chn CCP1 l outputbanksel TRISCbcf TRISC,2
;thit lp s kin cho module compare:;set chn CCP1
banksel CCP1CONmovlwb00001000movwf CCP1CON
;Ghi gi tr cn so snh vo cp thanh ghi;CCPR1H:CCPR1L
banksel CCPR1Hmovlwb10000000movwf CCPR1Hclrf CCPR1L
;Bt Timerbsf T1CON,TMR1ON
;Kim tra ngt bng phng php hi vngbtfss PIR1,CCP1IFgoto $-1
88Bin son: Phm Nguyn Huy Cng
Ch PWM
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Tnh hiu iu ch (PWM) pht ra trn 2 chn: CCP1
v CCP2
Thi gian ca 1 chu k, rng xung ca iu chv phn gii c nh r bi nhng thanh ghi sau:
Thanh ghi Gii thchPR2 Ch nh thi gian cho mt chu k xung PWM
T2CON iu khin Timer2
CCPRxL 2 thanh ghi xc nh ca rng xung PWM
CCPxCON 2 Thanh ghi iu khin module CCP
89
S khi PWM
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CCPR1L CCP1
CCP1pin
CCPR1H LATCH
TMR2 incrementing
PR2
Latch
CCP1 Output Pin
COMPARATOR
COMPARATORTMR2 = PR2
DUTY CYCLE VALUE
TMR2 = CCPR1H
DOUBLE
BUFFER
R
S
8
8
(1)
Ch (1): gi tr thanh ghi TMR2 kt hp vi 2 bitFOSC hoc 2 bit xc nh gi tr ca b chia trc tothnh 10 bit xc nh rng xung
10
10
10
Period 1
10
Period
Start
TMR2 Reset to 0sTMR2 Reset to 0s
TMR2 = PR2
DUTY CYCLE VALUE
TMR2 = CCPR1H
0
TMR2 = PR2
Period 2
Khi to PWM
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;Tt chn CCP1 bng cch set cc bit trong thanh ;ghiTRISC ln mc 1banksel TRISCbsf TRISC, 2 ;cu hnh cc chn l ng vo
;Xa Timer2banksel TMR2clrf TMR2
;Thit lp chu k xung v rng xung
movlw b01111111 ;movwf PR2 ;thit lp chu k xungmovlw b00011111 ;movwf CCPR1L ;thit lp rng xung
;thit lp CCP hot ng ch PWM;thit lp cc bit thp ca rng xung l b10movlw b00101100movwf CCP1CON
;cho php chn CCP l ng rabanksel TRISCbcf TRISC,2
;cho PWM hot ng bng cch bt Timer2;cu hnh e Prescaler v Postscaler c t l l 1:1)movlw b00000100movwf T2CON
91Bin son: Phm Nguyn Huy Cng
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PWM
C th PWM
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Cng thc PWM
Period(T) = (PR2 +1) * 4Tosc * TMR2 Prescale Value
Pulse = (CCPR1L,DC1B1,DC1B0) * Tosc * TMR2 Prescale Value
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Bi thc hnh:PWM
94Bin son: Phm Nguyn Huy Cng
Mc ch ca bi thc hnh
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PWM
Lm quen vi module CCP v thit lpcu hnh cho module hot ng ch PWM
Hiu r hn cc tnh nng ca moduleTimer2
Yu cu ca PWM Lab
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Yu cu ca PWM Lab
Ng ra xung PWM CCP1(chn RC2) s phtra m thanh (chn ny c gn vi loa trnmch PICDEM 2 Plus)
Bi thc hnh v PWM s pht ra xung cduty cycle l 50% vi chu k xung l256/(FOSC/4) iu khin buzzer pht ra mthanh.
96Bin son: Phm Nguyn Huy Cng
Tng quan v PWM Lab
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Chng trnh chnh
Thit lp gi tr PR2
Thit lp RC2 l ng ra
Thit lp CCPR1L c duty cycle l 50%
Cu hnh CCP l PWM 8 bit
Bt Timer2, prescaler= 1:1
NOP
97Bin son: Phm Nguyn Huy Cng
Chi tit lab PWM
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Hon tt cc bc sau:
Thit lp chn th 2 ca PORTC(CCP1) l ng ra
Cu hnh CCP hot ng ch
PWM
Xa CCP1X v CCP1Y (8-bit PWM)
Cu hnh Timer2 vi t l prescalerl 1:1
Bn cn bit g
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c b t g
Bi thc hnh c sn on chngtrnh thit lp duty cycle l 50%.
Chn CCP1 l chn RC2 (chn s 2 caPORTC) ca PIC16F877A
Cc thanh ghi chc nng cn ch trong bi thc hnh:
TRISC
T2CON CCP1CON
99
Li gii cho bi thch h PWM
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hnh v PWM;*****************************************************************
; Thit lp chn CCP1 l ng ra;*****************************************************************
bcf TRISC,2 ; ### thit lp chn CCP1 (PORTC) l ng ra
bcf STATUS,RP0 ; chuyn n BANK0movlw 0x80 ; thit lp duty cycle l 50%
movwf CCPR1L
;*****************************************************************
; Thit lp cu hnh hot ng ca module CCP1 l PWM;*****************************************************************
movlw 0x0C ; ###
movwf CCP1CON ; ###
;*****************************************************************
; Cu hnh cc b chia prescaler v postscaler t l 1:1 v bt Timer2;*****************************************************************
bsf T2CON,TMR2ON ; ### bt TMR2
100Bin son : Phm Nguyn Huy Cng
Cu hi cho bi thc hnh PWM
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v PWM
Cu hi:Ti sao ta khng cn phi cho php ccngt hot ng trong ch PWM?
Tr li:PWM s chy ng thi vi b x l ca PICm khng lm gim tc ca b x l
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Bi thc hnh v
B SO SNH
102Bin son : Phm Nguyn Huy Cng
Bi thc hnh v
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Bi thc hnh vB so snh
Mc ch ca bi thc hnh l cng c cc k nng: Thit lp CCP hot ng cu hnh l b so snh
S dng cc c ch th hin tng c bit (SpecialEvent Flag) reset Timer1
Cu hnh CCP to ngt khi Timer1 trn
S dng vector ngt hiu chnh khong thi giangia cc ngt
103Bin son: Phm Nguyn Huy Cng
Tng quan bi thc hnh v
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B so snh
Thit lp CCP hot ng cu hnh l b sosnh Ngt c s dng thay i m thanh cabuzzer.
Trong chng trnh ngt: o trng thi chn RC2/CCP1 (kt ni vi buzzer) Gim thi gian xy ra ngt
Gim gi tr thanh ghi CCPR1L
Reset gi tr thanh ghi m ca Timer1 Hiu ng ca vic gim dn thi gian xy ra ngts iu khin loa pht ra nhng m thanh vui tai
Lu gii thut cho bithc hnh v b so snh
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thc hnh v b so snhChng trnh ngt Chng trnh chnh
Lu thanh ghi
o trng thichn CCP1
Xo c ngt
Gim gi trCCPR1L
RETFIE
ResetTimer1
iu khinBuzzer
Cu hnh chn CCP1l ng ra
Khi to PORTC
Khi to Timer1
Bt Timer1
NOP
105Bin son : Phm Nguyn Huy Cng
Thc hnh v b so snh
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Thc hnh v b so snh
ng dn cha chng trnh ng dng ca bithc hnh:
C:\RTC\201_ASP\Lab5-CCP
Hon tt cc phn sau:
- Thit lp CCP hot ng cu hnh l b so snh,thit lp cc c cho php xy ra s kin c bit(Special Event Trigger) v thit lp CCP1IF
- Thit lp cu hnh hot ng cho Timer1: ngunxung clock l Fosc/4 v t l prescaler l 1:8
- Cu hnh cc thanh ghi chc nng cho phpngt CCP
106Bin son: Phm Nguyn Huy Cng
Bn cn bit
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Bn cn bit
Cc thanh ghi chc nng cn ch trong bithc hnh:
- INTCON (iu khin ngt)- T1CON (iu khin Timer1)
- CCP1CON (iu khin module CCP1)- PIE1 (Cho php/khng cho php cc ngt
ngoi vi)- Cc vector ngt- Gi tr ca CCPR1L sau khi c gim v 0s tng ln 0xFF v tip tc gim
107Bin son : Phm Nguyn Huy Cng
LI GII cho bi thch h b h
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108
hnh v b so snh;
; Thit lp CCP1CON cu hnh CCP1 hot ng cu hnh ca b so; snh, v to ra hiu ng c bit l xo cc thanh ghi m ca Timer1;****************************************************************
movlw 0x0B ; ### gi tr cn thit lp cho CCP1CONmovwf CCP1CON ; a vo thanh ghi CCP1CON
;; Cu hnh Timer 1: ngun xung clock l Fosc/4,; t l chia ca prescaler l 1:8;****************************************************************
movlw 0x30 ; ### Gi tr cn thit lp cho T1CONmovwf T1CON ; ### a vo thanh ghi T1CON
;; Cho php ngt Timer 1, ngt ngoi vi v ngt ton cc
; (Global Interrupt);****************************************************************
bsf PIE1,CCP1IE ; ### cho php ngt CCP1bsf INTCON,PEIE ; ### cho php ngt ngoi vibsf INTCON,GIE ; ### cho php ngt ton cc
Bin son : Phm Nguyn Huy Cng
Cu hi cho bi thc hnh v
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b so snh
Cu hi:PWM khng i hi ngt khi hot ng.Vychng ta c cn ngt khi hot ng cu hnh l
b so snh?
Tr li:Khng nht thit
Ngoi vi lun cp nht gi tr ca c bongt,v vy bn c th la chn trong vic x l ngt:
hi vng gi tr ca c ngt hay p ng trc tipngt.
S la chn ny ph thuc vo yu cu c thca ng dng.
109Bin son: Phm Nguyn Huy Cng
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B SO SNH IN P
110Bin son: Phm Nguyn Huy Cng
TNG QUAN V B SO SNHIN P
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IN P
Module so snh in p- Tn hiu tng t u vo c so snh
vi in p tham chiu v cho kt qu so snh
ng ra di dng tn hiu s
IN P THAM CHIU CAB SO SNH IN P
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in p tham chiu c th c ly t:
Bn ngoi
Bn trong, s dng module to in p tham chiu Cung cp 16 mc in p tham chiu, t 0 n 75%
ca in p VDD
- Mt vi chip hai mc in p tham chiu
VREF+ v VREF- Mt vi chip ch c 1 mc in p tham chiu c nh(0.6V)
- Khng ph thuc vo in p VDD
112Bin son: Phm Nguyn Huy Cng
CC NGT CA B SO SNH
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IN P
Ngt xy ra khi kt qu mc logic ng ra ca b sosnh in p thay i
Mt vi chip dng chung 1 c cho tt c cc bso snh
Mt vi chip c cc c c lp Phi c tn hiu ng ra ca b so snh in p
trc khi xo c ngt
Kt qu so snh c cha trong cc thanh ghi
iu khin CMCON hoc CMxCON0 Reset cc kt qu so snh khng hp l
113Bin son: Phm Nguyn Huy Cng
B so snh v ch ng
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Khi ang ch ng, b so snh vn hot ng Ng ra ca b so snh in p thay i s nh
thc PIC
Sau khi thot khi ch ng, lnh tip theo lnhSleep hoc chng trnh phc v ngt ca b sosnh in p s c thc thi
(Sleep mode)
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Chuyen oi A/D
TNG QUAN V ADC
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z Module chuyn i tn hiu tng t sang tn hiu s Chuyn i tn hiu tng t ng vo sang gi tr nh phn 8 bit hay 10 bit in p tham chiu c th c ly vo t bn ngoi hoc c to ra t
module to in p tham chiu bn trong Ngt c to ra sau khi thao tc chuyn i c hon tt
Ngt ADC cho php nh thc vi iu khin t trng thi ngsang trng thi hot ng bnh thng
Ngo vao Analog
ADC
Ngo ra digital
116Bin son: Phm Nguyn Huy Cng
Thanh ghi iu khin ADCM d l ADC i khi bi 2 th h hi
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ADCS1 ADCS0 CHS2 CHS1 CHS0 ADON
Module ADC c iu khin bi 2 thanh ghi: ADCON0 v ADCON1
Cc chip c nhiu hn 8 ng vo analog c iukhin bi cc thanh ghi khc
Thanh ghi ADCON0 (AD CONtrol register 0)
ADCS Chn ngun xung cock cho b chuyn i AD
Kt hp vi bit ADCS2 ca thanh ghi ADCON1
CHSx bits Chn ng vo analog thc hin chuyn i AD
GO/DONE 1 = ang tin hnh chuyn i A/D
0 = chuyn i A/D hon tt
ADON Cho php module ADC hot ng
BIT CHC NNG
GO/DONE
117Bin son: Phm Nguyn Huy Cng
Cc thanh ghi iu khin ADC Module ADC c iu khin bi 2 thanh ghi:
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ADFM Bit iu khin nh dng kt qu chuyn i AD
1 = ly l bn phi, 0 = ly l bn tri
ADCS2 Chn ngun xung clock cho b chuyn i AD
Kt hp vi cc bit ADCS trong thanh ghi ADCON0
PCFG Thit lp cu hnh cc ng vo
Thit lp cu hnh cc chn I/O l analog hay digital
BIT CHC NNG
Thanh ghi ADCON1 (AD CONtrol register 1)
Module ADC c iu khin bi 2 thanh ghi: ADCON0 v ADCON1
Cc chip c nhiu hn 8 ng vo analog c iu khinbi cc thanh ghi khc
ADFM PCFG3 PCFG0PCFG2 PCFG1ADCS2
118Bin son: Phm Nguyn Huy Cng
Thanh ghi cha kt quchuyn i AD
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chuyn i AD 10 bit cha kt qu chuyn i AD c lu trong 2 thanh ghi:
ADRESH v ADRESL
Ly l bn tri v Ly l bn phi
c iu khin bi bit ADFM trong thanh ghi ADCON1
MSB LSB
MSB LSBADRESH
Ly l bn tri (ADFM = 0)
Ly l bn phi (ADFM = 1)
ADRESL
ADRESH ADRESL
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S khi ca module ADC
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ADC
HoldingCapacitor
Conversionclock scalerFosc
VREF+pin
VREF-pin
Vss
ADRESH ADRESL
ADCON0
ADCS1 ADCS0 CHS2 CHS1 CHS0 ADONGO/DONE
ADCON1
ADFM PCFG3 PCFG1 PCFG0PCFG2ADCS2
Conversion CompleteStart Conversion
AN0
AN1
AN2
AN3
AN4
AN5AN6
AN7Left Justified Right Justified
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
120Bin son: Phm Nguyn Huy Cng
S khi ADC
VddAN7 AN6 AN5 AN4
AN1 AN0AN3 AN2PCFG
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ADC
HoldingCapacitor
Conversionclock scalerFosc
VREF+pin
VREF-pin
Vss
ADRESH ADRESL
ADCON0
ADCS1 ADCS0 CHS2 CHS1 CHS0 ADONGO/DONE
ADCON1
ADFM PCFG3 PCFG1 PCFG0PCFG2ADCS2
Conversion CompleteStart Conversion
0 0 0
AN0
AN1
AN2
AN3
AN4
AN5AN6
AN7
01
Left Justified Right Justified
Port Config Bits
10
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
dd
121Bin son: Phm Nguyn Huy Cng
Thi gian chuyn i AD
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Khi mt knh AD c la chn, cn lu n thi gian np x ca t in (holdingcapacitor)
B ADC 10 bit hon tt chuyn i sau 11chu k xung clock
Cn la chn ngun xung clock hp l
cho hot ng ca b ADC
122Bin son: Phm Nguyn Huy Cng
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Bi thc hnh v ADC
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Bi thc hnh v ADC
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Bi thc hnh gip bn lm quen vi:
Qui trnh thit lp cc hot ng ca moduleADC
Lp trnh iu khin ngoi vi trong chng
trnh chnh, khng s dng chng trnh ngt S dng kt qu thu c ca mt ngoi vi
(ADC) iu khin mt ngoi vi khc (CCP
ch PWM)
124Bin son: Phm Nguyn Huy Cng
Lu gii thut cho bi thchnh v ADC
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t cu hnh cho Timer 2
t cu hnh ADCCho php ADC hot
ng
t cu hnh cho
CCP ( ch PWM)
t cu hnh cho PORT C
Cho php cc ngt
Chng trnh chnh
Xem trangtip theo
125Bin son: Phm Nguyn Huy Cng
Lu gii thut cho bi thc hnhv ADC (tt)
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Xut 4 bit thp ca ktqu ADC ra LED
Bt u chuyn i AD
a kt qu ADC
vo thanh ghiCCPR1L
Chuyn i xong?
TMR2IF=1
Vng lp chnh NO
YES
NO
YES
Tip theo trngtrc
126Bin son: Phm Nguyn Huy Cng
Cc bc cn thc hin
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ng dn cha chng trnh ca bi thchnh: C:\RTC\201_ASP\Lab6-ADC Cu hnh module ADC lu kt qu nh dng
ly l bn tri
Cu hnh xung clock cho ADC l FOSC/32
Cho php module ADC hot ng
Cho php ADC hot ng v ch cho n khichuyn i AD hon tt trong vng lp chnhca chng trnh
127Bin son: Phm Nguyn Huy Cng
Cc kin thc cn nm
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Bi thc hnh khng s dng chngtrnh ngt cho hot ng chuyn i ADC,v phng php hi vng c la chn.
Ghi kt qu chuyn i AD ln thanh ghiCCPR1L s lm thay i duty cycle caxung PWM xut ra buzzer
Cn nm r cc thanh ghi iu khinmodule ADC: ADCON1 v ADCON0
128Bin son: Phm Nguyn Huy Cng
Li gii cho bi thchnh v ADC
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;*************************************************************************; Cu hnh ADC: knh 0, ly l bn tri, Tad = 8 * Tosc, bt ADC;*************************************************************************
clrf ADCON0 ; ### chn knh 0 cho ng vo ADbsf ADCON0,ADCS1 ; ### thit lp Tad = Fosc/4bsf ADCON0,ADON ; ### bt ADCbsf STATUS,RP0 ; ### chuyn qua BANK1movlw 0x0E ; ### ly l bn tri, cu hnh AN0 l analogmovwf ADCON1
;
; Cho php ngt Timer 2, ngt ngoi vi v ngt ton cc;bsf PIE1,TMR2IEbsf INTCON,GIEbsf INTCON,PEIEbcf STATUS,RP0 ; tr v BANK0
;;*************************************************************************
; thm 3 dng lnh bt u thc hin chuyn i AD; v ch cho n khi chuyn i hon tt;*************************************************************************
bsf ADCON0,GO ; ### bt u thc hin chuyn i ADbtfsc ADCON0,GO ; ### chuyn i hon tt?goto $-1 ; ### cha, ch cho ti khi chuyn i hon tt
129Bin son: Phm Nguyn Huy Cng
Cu hi cho bi thchnh v ADC
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hnh v ADC
Cu hi:Thay v phi ch ngt Timer 2 xy ra (bngcch kim tra c ngt TMR2IF trong chngtrnh chnh, ta c th kch hot module AD bng
chng trnh ngt c khng?
Tr li:
c
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AUSART
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Tng Quan AUSART
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Giao tip ngoi vi qua chun ni tipCn c gi l Giao din truyn thng ni tip Chc nng chnh:
ng b hay bt ng b Nhn hoc truyn:
o Nhn v truyn bt ng b song cngo Ch v t ng b bn song cng S dng thng thng:
Giao tip qua RS-232 vi cng ni tip ca PCo Cn driver cho b chuyn dch mc RS-232
Tnh nng ni bt (EUSART) lin kt giao din vi h thng
bus ca mng lin kt cuc b (LIN)
g Q
132Bin son: Phm Nguyn Huy Cng
Thanh ghi AUSART
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Thanh ghi tc baud- SPBRG (8 bit for AUSART)
- SPBRG and SPBRGH (16 bit for EUSART)
iu khin v truyn trng thi- TXSTA
iu khin v nhn trng thi- RCSTA
Thanh ghi truyn d liu- TXREG
Thanh ghi nhn d liu- RCREG
g
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134Bin son: Phm Nguyn Huy Cng
Thanh Ghi RCSTA
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SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
Bitt Trng
SPEN
Khi ng port Ni Tip
1=khi ng port ni tip (Thit lp cu hnh chn RX/DT V TX/CK ca cc chn Port ni tip);0=Khng khi ng Port NiTip
RX9 1=khi ng nhn 9 bit d liu,0=8 bit d liu
SREN Phng Thc ng B (Ch),1= k hi ng tn hiu RX,0=khng khi ng RX
CRENTip tc khi ng nhn d liu,1=Khi ng,0=khng khi ng
ADDEN Khi ng tng bit a ch
1=khi ng(khi ng ngt v load b im RX khi RSRcset),0=khng khi ng v s dng bit chn l th 9
FERR 1=Kim tra li s kin(bit STOP khng c xo)
OERR 1=Li s kin trn (FIFO vn cn y khi d liu khc c load)
RX9D Nhn bit d liu th 9
S Khi Pht D Liu
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BUSS D LIU
TXIETXREG
CHO PHP NGT
CHN
TX/DT
SPEN
B M V IUKHIN
TXEN
B TO DAONG
TX9DTX9
Set bit TRMT
Dch chuyn b ghi dch
Xo bit TMRT
TSR c d liu trong
Khi ng Port nitip
MSBLSB
Bit d liu th 9
TRMT
136Bin son: Phm Nguyn Huy Cng
S Khi Nhn D LiuKhi ng port nitip
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CHNRX/DT
SPEN
B m viu khin
Nhn d liu
B to daong
RX9
FIFO
RCREG
RX9DRCIF
RCIE
Set c RCIF
Xo c RCIF
Cho Php NgtBuss D Liu
STOP STRAT
Thanh ghi dch nhn d liu(RSR)
137Bin son: Phm Nguyn Huy Cng
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CHUN CNG NI TIP NGB (MSSP)
138Bin son: Phm Nguyn Huy Cng
Tng quan v MSSP
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Module MSSP c th hot ng mt trong 2
ch SPI( Giao tip ngoi vi ni tip)
3 Chn c s dng Ng ra d liu ni tip ( SDO)
Ng vo d liu ni tip(SDI) Clock ni tip(SCK)
I2C Ch Master hon ton
Ch slave 2 chn c dng Clock ni tip ( SCK) D liu ni tip ( SDA)
139Bin son: Phm Nguyn Huy Cng
Cc iu kin cho I2C
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Cc iu kin: START(S)
STOP(S)
ACKNOWLEDGE(A)
RESTART(R)
NEGATIVE hoc NOT-ACKNOWLEDGE(N)
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141Bin son: Phm Nguyn Huy Cng
Cc thanh ghi iu khin MSSP( ch I2C)
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Thanh ghi 1: Thanh ghi trng thi MSSP (SSPSTAT)
Cc bit iu khin Cc bit c
BIT CHC NNG
SMP Bit iu khin tc qut
CKE Khng s dng trong ch I2C
D/ Byte cui ca Tx/Rx l d liu hoc a ch
P Pht hin iu kin dng
S Pht hin iu kin bt u
R/ Slave: c/ghi hoc Master = ang truynUA a ch cn c cp nht
BF Thanh ghi SSPBUF y
Cc thanh ghi i u khi n MSSP( ch I2C)
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Thanh ghi 2: thanh ghi iu khin MSSP 1( SSPCON)
Cc bit iu khin
BIT Chc nng
WCOL Kim tra xung t khi ghi
SSPOV Ghi ln SSPBUF trc khi gi tr x l trc
SSPEN Kch hot module MSSP
CKP Kch hot clock
SSPM3
cc bit chn ch SSPM2SSPM1
SSPM0
Slide 142
Cc bit kim tra( c)
Bin son: Phm Nguyn Huy Cng
Cc thanh ghi i u khi n MSSP( ch I2C)
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Thanh ghi 3: thanh ghi iu khin MSSP 2( SSPCON 2)
Bit Chc nng
GCEN To ra ngt khi c gi( ch slave)
ACKSTAT 0= thng bo nhn c t slave( ch truyn)
ACKDT 0= ACK 1= NACK( ch nhn)
ACKEN Initiate ACK/ NACK condition ( transmit ACKDT bit)
RCEN Kch hot ch nhnPEN Khi ng iu kin STOP
RSEN Khi ng iu kin RESTART
SEN Khi ng iu kin START
Cc bit iu khin Cc bit kim tra( c)
Slide 144Bin son: Phm Nguyn Huy Cng
Cc thanh ghi iu khin MSSP( ch I2C)
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( )SSPM3 SSPM2 SSPM1 SSPM0 Ch
0 0 0 0 SPI Ch ch , clock = FOSC/40 0 0 1 SPI Ch ch , clock = FOSC/16
0 0 1 0 SPI Ch ch , clock = FOSC/64
0 0 1 1 SPI Ch ch , clock = TRM2 output/2
0 1 0 0 SPI Ch ph , clock= chn SCK, chn iu khin SS c kch hot
0 1 0 1 SPI Ch ph , clock= chn SCK, chn iu khin SS b ngt, SS c
th s dung nh I/O pin0 1 1 0 I2C Ch ph , 7 bit a ch
0 1 1 1 I2C Ch ph , 10 bit a ch
1 0 0 0 I2C ch ch, clock= FOSC / ( 4* (SSPADD+1))
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 I2C firmware c iu khin bi ch ch ( Slave Idle)
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 I2C Ch ph, 7 bit a ch vi bit Start v Stop c ngt
1 1 1 1 I2C Ch ph, 7 bit a ch vi bit Start v Stop c ngt
Slide 143Bin son: Phm Nguyn Huy Cng
B M Tx/Rx (SSPBUF)
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Thanh ghi m cha d liu Tx v RxSSPBUF giao tip vi thanh ghi dch (SSPSR) chuyn d liu vo hocra
Khi b m y th bit bo y (BF) trong thanh ghi SSPSTAT s ctch cc.
Bt c ghi g ln thanh ghi SSPBUF trong khi Tx/Rx d liu u b t
chi, v bit pht hin xung t ghi (WCOL) ca thanh ghi SSPCON stch cc
( )
146Bin son: Phm Nguyn Huy Cng
Thanh ghi a ch I2C(SSPADD)
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(SSPADD)
Ch slave :Cha a ch slave ca PIC
So snh vi gi tr a ch nhn c
Ch master :Dng tnh ton tc xung clock ( tc BAUD ) ca h thng I
2C
Tc Baud
Ch : Fosc l tn s dao ng thch anh, khng phi l chu k lnh TCY
147Bin son : Phm Nguyn Huy Cng
CC NGT MSSP
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C ngt MSSP (SSPIF) c tch cc trongthanh ghi PIR1 vi cc s kin sau : iu kin START
iu kin STOP
TX/RX hon thnh Xc nhn pht iu kin RESTART
148Bin son : Phm Nguyn Huy Cng
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Th nghim giao tip I2C
149Bin son : Phm Nguyn Huy Cng
Mc tiu ca bi lab cm bin
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nhit vi I2C
Cu hnh mt vi thanh ghi iu khin MSSP thitlp truyn thng I2C vi cm bin nhit trn
mch PICDEM 2. c nhit (4 bit thp) s c hin th trn ccLED.
150Bin son : Phm Nguyn Huy Cng
Tng quan v I 2C Lab
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g q
Bi th nghim ny cu hnh MSSP thnh mt I2CMaster
Cm bin nhit TC74, c bng MSSP module
Nhit c c gi ra PORTB hin th ln 4 LED.
151Bin son: Phm Nguyn Huy Cng
Tng quan v I 2C LabThut ton
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Lp vng Gi a ch cm bin nhit
c nh it
Hin th nhit ( cc bit thpP
Ra LED PORB
iu kin khi ng ban u cho I2
C
Cu hnh I/0
Cu hnh MSSP
152Bin son : Phm Nguyn Huy Cng
Chi tit v bi lab I 2C
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Chng trnh ca bi lab lu C:\RTC\201_ASP\Lab7-I2C
Hon thnh cc phn sau: Kha chc nng iu chnh tc qut
ta s dng tn s I2C chun (100KHz)
Cu hnh MSSP hot ng ch I2C masterv cho php chn d liu(SDA) v chn clock (SCL)tch cc
Khi ng truyn d liu v kim tra khi hon thnh.
153Bin son: Phm Nguyn Huy Cng
Bn cn bit
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iu khin t l xoay c tm thy thanh ghiSSPSTAT
Cc thnh ghi cn bit hon thnh bi th nghim:
SSPSTAT
SSPCON SSPCON2
154Bin son : Phm Nguyn Huy Cng
Li gii Lab I2C
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;------------------------------------------------------------------------------------------------------;Thit lp t l, tc Baud cho hot ng 100MHzBANKSEL SSPSTAT ;### tr ti BANK choSSPSTATBsf SSPSTAT ;### thit lp tc qut chun;--------------------------------------------------------------------------------------------------;Cu hnh I2C Master vi ngun xung clock Fosc/4
BANKSEL SSPCON ;Bsf SSPCON,SSPM3 ;### thit lp ch I2C Master vi
; ngun xung clock Fosc/4Bsf SSPCON,SSPEN ;### Cho php chn SDA v SCL tchcc
; hot ng ch I2C;------------------------------------------------------------------------------------------------------
BANKSEL SSPCON2 ; iu kin STARTban uBsf SSPCON2,SEN ;### cho tch cc bit SENBsfsc SSPCON2,SEN ;### ch xong?Goto $-1 : khng : kim ta li
155Bin son : Phm Nguyn Huy Cng
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TH NGHIM V NGT
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TH NGHIM V NGT
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Bi ny bao gm 2 hay nhiu ngt ng thi
Xc nh ngun ngt
Quyt inh ngt no c phc v trc
157Bin son: Phm Nguyn Huy Cng
Tng quan Labthut ton
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Cu hnh CCP l ng ra b so
snhNh Lab6
Cho tch cc Timer 1 v PORTC
Nh Lab6
Cu hnh PORTB: cho phpngt ngoi S3 Nh
Lab1
NOP
158Bin son: Phm Nguyn Huy Cng
Tng quan LabTrnh phc v ngt
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Gi chng trnh to trChng rung phm
o gi tr binGi push_flag
Xa c IF
Tr v chngtrnh chnh
Xa IF
t -1 vo WREG
Thit lpPush_flag?
t 0 vo WREG
Cng WREG viCCPR1L
Tr v chngtrnh chnh
INT_ISRCCP_ISR
159Bin son: Phm Nguyn Huy Cng
Tng quan Lab
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C ngtCCP?
Lu trng thi
n trnh phc vngt CCP
C ngtngoi?
Phc v ngt ngoiTr v chng
trnh chnh
NO
NOYES
YES
IU KHIN NGT
160Bin son: Phm Nguyn Huy Cng
Chi tit Lab
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Lab lu ti:
C:\RTC\201_ASP\Lap8-MXINT 2 trnh phc v ngt:
INT_ISR
CCP_ISR Hon thnh chng trnh theo cc phnsau Khi sy ra ngt, xc nh v truyn tn hiu iu
khin ti trnh phc v ngt tng ng. Thit lp thanh ghi chc nng c bit ( SFR)
tch cc INT v CCP.
161Bin son: Phm Nguyn Huy Cng
Bn cn bit
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INTCON, v thanh ghi chc nng c bitPIR trong lab ny.
162Bin son: Phm Nguyn Huy Cng
Bi gii Lab
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Int_service_RoutineCall save_regs ;lu W, STATUS, PCLATHBtfsc INTCON,INTF ;### kim tra yu cu ngt ngoiGoto INTE_ISR ;Btfsc PIR1,CCP1IF ; ### kim tra yu cu ngt CCPFinish_int
Call restore_regs ;Phc hi W, STATUS, PCLATHretfie
163Bin son: Phm Nguyn Huy Cng
Bi gii lab
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Bsf PIE1,CCP1IE ;### Cho php ngt CCP1Bsf INTCON,INTE ;### Cho php ngt ngoiBsf INTCON,GIE ;### Cho php ngt ton ccBsf INTCON,PEIE ;### Cho php ngt ngoi viBcf STATUS,RP0 ; tr v BANK 0
164Bin son: Phm Nguyn Huy Cng
Cu hi
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Cu hi ti sao cn ch s n nh khi S3 c
nhn
Tr li
Khi chng trnh chng rung c g trongchng trnh ngt, v GIE b xa, ngt CCP1lt trng thi, khng cho php loa hot
ng. Loa khng ku
165Bin son: Phm Nguyn Huy Cng
Cu hi
C
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Cu hi
Lm th no khong lng ny c th c cchli v loa tip tc hot ng?
Tr li
Bt xung S3 trong chng trnh chnh v gi
chng trnh chng rung trong khi GIE tch cc S dng timer to tr
Cho php cc ngt tch cc tr li trong INT_ISR
166Bin son: Phm Nguyn Huy Cng
Lp ngoi vi
H t t hi b h i i
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Hm nay ta tm hiu cc b phn ngoi vi
ca h PIC c va PORT I/O Cu trc v x l ngt Timer(timer0, timer1, timer2) Module CCP (Ng ra so snh, bt xung ng vo,
PWM)
Cc b so snh v chuyn i AD in p tham chiu
AUSART Port ni tip S dng module MSSP cho I2C
167Bin son: Phm Nguyn Huy Cng
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201ASP Wrap-up
168Bin son: Phm Nguyn Huy Cng
Li cui
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Phn tho lun ny trnh by theo chunca Microchip:
Tng quan v ngoi vi
M t thanh ghi v cccu hnh
Nng cao hoc ccchc nng c bit
S dng phn ny :-Pht trin lu thut ton hoc
m gi ( Trnh m ri)Mch nc:-Ch thch cc on m trong sutchng trnh-Chn cc tn gi nh xc nhcc thnh ghi
169Bin son: Phm Nguyn Huy Cng
Ngun
T i hi
http://www.microchip.com/http://www.microchip.com/7/31/2019 Chuong 4 Ngoai Vi Va Lap Trinh Asm
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Truy cp www.microchip.com : H tr k thut 24/7
Cc lu trong thit k ng dng
Semina
Cc chng trnh v d Datasheet
V Nhiu hn na !!
170Bin son: Phm Nguyn Huy Cng
http://www.microchip.com/http://www.microchip.com/7/31/2019 Chuong 4 Ngoai Vi Va Lap Trinh Asm
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Thank You!!