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8/10/2019 Chapter4 - Combinational Circuit Building Blocks
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Week Group 1 Group 2 Remarks
Week 1 No Class Dr. Sofian Assignment 1
Week 2 Mr. Mahazani Dr. Sofian
Week 3 Dr. Sofian Dr. Sofian Assignment 2Week 4 Dr. Sofian Dr. Sofian
Week 5 Dr. Sofian Dr. Sofian Assignment 3
Week 6 Dr. Sofian Dr. Sofian
Semester Break
Week 7 Dr. Sofian Dr. Sofian Mid-Term Test
Week 8 Mr. Mahazani Mr. Mahazani
Week 9 Mr. Mahazani Mr. Mahazani
Week 10 Mr. Mahazani Mr. Mahazani
Week 11 Mr. Mahazani Mr. Mahazani
Week 12 Mr. Mahazani Mr. Mahazani
Week 13 Mr. Mahazani Mr. Mahazani
Week 14 Mr. Mahazani Mr. Mahazani
Revision Week
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Final Exam
Saturday (10 Jan 2015)
Venue - not yet decided
11:30 1:30 PM
4 Questions
Answers all
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Reference books
Main texbook:
Fundamentals of Digital Logic with Verilog Design, 3rd
Edition, Brown and Vranesic, McGraw Hill, 2013.
Other textbooks:
Digital design: with an introduction to the Verilog
HDL, 5thEdition, Mano and Cilleti, Pearson, 2012.
Digital design and computer architecture, 2nd
Edition,David Harris and Sarah Harris, Morgan Kaufman, 2013
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Time Table (Group 1)
Mon 2:00 4:00 PM DK8
Tue 12:00 1:00 PM DK8
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Short revision
Truth table
Logic gates
Boolean algebra Synthesis (SOP & POS)
Karnaugh map
Number representation
Adder
Multiplier
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Chapter 4
Combinational-CircuitBuilding Blocks
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Combinational Circuits
Combinational circuits are stateless
Output is dependent only on its inputs
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Multiplexer
Combinational circuit that selects binary
information from one of many input lines
and directs it to one output line
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Figure 4.1. A 2-to-1 multiplexer.
(a) Graphical symbol
f
s
w0
w1
0
1
(b) Truth table
0
1
f
fs
w0
w1
(c) Sum-of-products circuit
s
w0
w1
(d) Circuit with transmission gates
w0
w1 f
s
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Figure 4.2. A 4-to-1 multiplexer.
f
s1
w0w1
00
01
(b) Truth table
w0w1
s0
w2
w3
10
11
0
0
1
1
1
0
1
fs1
0
s0
w2
w3
f
(c) Circuit
s1
w0
w1
s0
w2
w3
(a) Graphic symbol
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Figure 4.3. Using 2-to-1 multiplexers to build a 4-to-1 multiplexer.
0
w0
w1
0
1
w2w3
0
1
f0
1
s1
s
Larger multiplexer can also be constructed from
smaller multiplexers
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Figure 4.4. A 16-to-1 multiplexer using 4-to-1 multiplexer.
w8
w11
s1
w0
s0
w3
w4
w7
w12
w15
s3
s2
f
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Figure 4.5. A practical application of multiplexers.
x1 0
1
x2 0
1
s
y1
y2
x1
x2
y1
y2
(a) A 2x2 crossbar switch
(b) Implementation using multiplexers
s
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Figure 4.6. Synthesis of a logic function using multiplexers.
(a) Implementation using a 4-to-1 multiplexer
f
w1
0
1
0
1
w2
1
0
0
0
1
1
1
0
1
fw1
0
w2
1
0
(b) Modified truth table
0
1
0
0
11
1
01
fw1
0
w2
10
f
w2
w1
0
1
fw1
w2
w2
(c) Circuit
1
2
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Figure 4.7. Implementation of the three-input majority function
using a 4-to-1 multiplexer.
w3
w3
f
w1
0
w2
1
(a) Modified truth table
(b) Circuit
00
0
1
1
1
0
1
fw1
0
w2
1
0 0
0 1
1 0
1 1
0
0
0
10 0
0 1
1 0
1 1
0
1
1
1
w1 w2w3 f
0
0
0
01
1
1
1
w3
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Figure 4.8. Three-input XOR implemented with
2-to-1 multiplexers.
(a) Truth table
0 00 1
1 0
1 1
01
1
0
0 0
0 1
1 01 1
1
0
01
w1w2w3 f
00
0
0
1
1
11
w2 w3
w2 w3
f
w3
w1
(b) Circuit
w2
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Figure 4.9. Three-input XOR function implemented with
a 4-to-1 multiplexer.
f
w1
w2
(a) Truth table (b) Circuit
0 0
0 1
1 0
1 1
0
1
1
0
0 00 1
1 0
1 1
10
0
1
w1w
2w
3f
0
0
0
0
11
1
1
w3
w3
w3
w3
w3
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Standard MSI Multiplexers
Standard MSI Multiplexers
74151A (8-to-1)
74150 (16-to-1)
74153 (2-bit 4-to-1)
74157 (4-bit 2-to-1)
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Standard MSI Multiplexers 74151A
74151A
8-to-1 multiplexer
Output equation
Strobe (~G) acts as enablesignal
2ndoutput W is just
complement of Y
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Standard MSI Multiplexers 74150
74150
16-to-1 multiplexer
Output equation
One strobe signal (~G)
Only one output (W)
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Standard MSI Multiplexers 74153
74153
2-bit 4-to-1 multiplexer
(contain two 4-to-1
multiplexers)
Have 1 enable signal.
Module behavior:
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Standard MSI Multiplexers 74153
Alternative Symbol
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Standard MSI Multiplexers 74157
74157
4-bit 2-to-1 multiplexer
Have only 1 control signal
(S) Have 1 enable signal (~G)
Multiple 74157 can be used
to create other multiplexer
configurations of different: Path widths, and
Number of inputs.
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Standard MSI Multiplexers 74157
Extending path widths
Two 74157s are used to
create 8-bit two-input
multiplexer.
Both modules are
controlled with the same
select signal (S).
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Standard MSI Multiplexers 74157
Extending number of
inputs.
Two 74157s are used to
create 4-bit four-inputmultiplexer.
S1 selects only 1 module
(and turns off the other)
S0 selects of one of the two4-bit input of the enabled
module.
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28
Decoders
n-to-2n decoder is a multiple-output
combinational logic, with:
n input lines, and
2n output lines.
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Figure 4.14. Binary decoder.
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Figure 4.15. A 3-to-8 decoder using two 2-to-4 decoders.
w2
w0 y0y1y2y3
w0
En
y0w1 y1
y2y3
w0
En
y0w1 y1
y2y3
y4y5y6y7
w1
En
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Figure 4.16. A 4-to-16 decoder built using a decoder tree.
w0
En
y0w1 y1
y2y3
y8y9y10y11
w2
w0 y0y1y2y3
w0
En
y0w1 y1
y2y3
w0
En
y0w1 y1
y2y3
y4y5y6y7
w1
w0
En
y0w1 y1
y2y3
y12y13y14y15
w0
En
y0w1 y1
y2y3
w3
En
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Figure 4.17. A 4-to-1 multiplexer built using a decoder.
w1
w0
w0
En
y0w1 y1
y2
y3
w2
w3
f
s0s1
1
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Demultiplexers Connects a single input line to one of noutput lines
(2s>=n). (sis number of bits in the selection code).
Functional
Diagram
Selection code is used
to generate a mintermof svariables.
That minterm thenconnects the input datato the proper outputterminal.
n-to-2n decoder can beused as a 1-to-ndemultiplexer
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Demultiplexers 1-to-4 data demultiplexer
with an enable signal (E)(that controls the operationof the circuit) is shown on
the left.
1-to-4 Demultiplexer
(with Enable)
The operation of the devicecan be described as:
Yi= ( miD )E(Dis the input signal to bedistributed to the noutputlines)
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Encoders
An encoder performs the opposite function
of a decoder
Encoders is a combinational logic thatassigns a unique output code for each input
signal (opposite of a decoder).
If an encoder has ninputs, the number ofoutputssmust satisfy the expressions:
2s>= n
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Figure 4.18. A 2n-to-nbinary encoder.
2n
inputs
w0
w2n 1
y0
yn 1
noutputs
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Figure 4.19. A 4-to-2 binary encoder.
0
0
1
1
1
0
1
w3 y1
0
y0
(b) Circuit
w1
w0
0
0
1
0
w2
0
1
0
0
w1
1
0
0
0
w0
0
0
0
1
y0
w2
w3 y1
(a) Truth table
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Figure 4.20. Truth table for a 4-to-2 priority encoder.
d
0
0
1
0
1
0
w0 y1
d
y0
1 1
0
1
1
1
1
z
1
x
x
0
x
w1
0
1
x
0
x
w2
0
0
1
0
x
w3
0
0
0
0
1
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Figure 4.21. A hex-to-7-segment display code converter.
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Figure 4.22. A four-bit comparator circuit.
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Figure 4.23. A 2-to-1 multiplexer specified using the conditional operator.
modulemux2to1 (w0, w1, s, f);inputw0, w1, s;
outputf;
assignf = s ? w1 : w0;
endmodule
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Figure 4.24. An alternative specification of a 2-to-1 multiplexer
using the conditional operator.
modulemux2to1 (w0, w1, s, f);
inputw0, w1, s;
outputregf;
always@(w0, w1, s)
f = s ? w1 : w0;
endmodule
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Figure 4.25. A 4-to-1 multiplexer specified using the conditional operator.
modulemux4to1 (w0, w1, w2, w3, S, f);inputw0, w1, w2, w3;
input[1:0] S;
outputf;
assignf = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);
endmodule
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Figure 4.26. Code for a 2-to-1 multiplexer using the if-elsestatement.
modulemux2to1 (w0, w1, s, f);
inputw0, w1, s;
outputregf;
always@(w0, w1, s)
if(s==0)
f = w0;else
f = w1;
endmodule
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Figure 4.27. Code for a 4-to-1 multiplexer using the if-elsestatement.
modulemux4to1 (w0, w1, w2, w3, S, f);
inputw0, w1, w2, w3;
input[1:0] S;
outputregf;
always@(*)
if(S == 2'b00)
f = w0;
elseif(S == 2'b01)f = w1;
elseif(S == 2'b10)
f = w2;
elseif(S == 2'b11)
f = w3;
endmodule
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Figure 4.28. Alternative specification of a 4-to-1 multiplexer.
modulemux4to1 (W, S, f);
input[0:3] W;
input[1:0] S;
outputregf;
always@(W, S)
if(S == 0)
f = W[0];
else if(S == 1)f = W[1];
else if(S == 2)
f = W[2];
else if(S == 3)
f = W[3];
endmodule
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Figure 4.29. Hierarchical code for a 16-to-1 multiplexer.
modulemux16to1 (W, S, f);
input[0:15] W;
input[3:0] S;
outputf;
wire[0:3] M;
mux4to1 Mux1 (W[0:3], S[1:0], M[0]);
mux4to1 Mux2 (W[4:7], S[1:0], M[1]);mux4to1 Mux3 (W[8:11], S[1:0], M[2]);
mux4to1 Mux4 (W[12:15], S[1:0], M[3]);
mux4to1 Mux5 (M[0:3], S[3:2], f);
endmodule
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Figure 4.30. A 4-to-1 multiplexer defined using the casestatement.
modulemux4to1 (W, S, f);
input[0:3] W;
input[1:0] S;
outputregf;
always@(W, S)
case(S)
0: f = W[0];1: f = W[1];
2: f = W[2];
3: f = W[3];
endcase
endmodule
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Figure 4.31. Verilog code for a 2-to-4 binary decoder.
moduledec2to4 (W, En, Y);
input[1:0] W;
inputEn;
outputreg[0:3] Y;
always@(W, En)
case({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
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Figure 4.32. Alternative code for a 2-to4 binary decoder.
moduledec2to4 (W, En, Y);
input[1:0] W;
inputEn;
outputreg[0:3] Y;
always@(W, En)
begin
if(En == 0)
Y = 4'b0000;
else
case(W)
0: Y = 4'b1000;
1: Y = 4'b0100;
2: Y = 4'b0010;
3: Y = 4'b0001;
endcase
end
endmodule
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Figure 4.33. Verilog code for a 4-to-16 decoder.
moduledec4to16 (W, En, Y);
input[3:0] W;
inputEn;output[0:15] Y;
wire[0:3] M;
dec2to4 Dec1 (W[3:2], M[0:3], En);dec2to4 Dec2 (W[1:0], Y[0:3], M[0]);
dec2to4 Dec3 (W[1:0], Y[4:7], M[1]);
dec2to4 Dec4 (W[1:0], Y[8:11], M[2]);
dec2to4 Dec5 (W[1:0], Y[12:15], M[3]);
endmodule
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Figure 4.34. Code for a hex-to-7-segment decoder.
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Table 4.1. The functionality of the 74381 ALU.
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Figure 4.35. Code that represents the functionality of the 74381 ALU chip.
// 74381 ALU
modulealu(s, A, B, F);
input[2:0] S;
input[3:0] A, B;
outputreg [3:0] F;
always@(S, A, B)
case(S)
0: F = 4'b0000;
1: F = B - A;
2: F = A - B;3: F = A + B;
4: F = A ^ B;
5: F = A | B;
6: F = A & B;
7: F = 4'b1111;
endcase
endmodule
modulepriority (W, Y, z);
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Figure 4.36. Verilog code for a priority encoder.
odu e p o ty (W, , );
input[3:0] W;
outputreg[1:0] Y;
outputregz;
always@(W)begin
z = 1;
casex (W)
4'b1xxx: Y = 3;
4'b01xx: Y = 2;
4'b001x: Y = 1;4'b0001: Y = 0;
default: begin
z = 0;
Y = 2'bx;
end
endcase
end
endmodule
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Figure 4.37. A 2-to-4 binary decoder specified using the forloop.
moduledec2to4 (W, En, Y);
input[1:0] W;
inputEn;
outputreg[0:3] Y;integerk;
always@(W, En)
for(k = 0; k
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Figure 4.38. A priority encoder specified using the forloop.
modulepriority (W, Y, z);
input[3:0] W;
outputreg[1:0] Y;
outputregz;
integerk;
always@(W)
begin
Y = 2'bx;
z = 0;
for(k = 0; k < 4; k = k+1)
if (W[k])
begin
Y = k;
z = 1;
end
end
endmodule
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Figure 4.39. Truth tables for bitwise operators.
& 0 1 x j 0 1 x
0 0 0 0 0 0 1 x
1 0 1 x 1 1 1 1
x 0 x x x x 1 x
^ 0 1 x ~ ^ 0 1 x
0 0 1 x 0 1 0 x
1 1 0 x 1 0 1 xx x x x x x x x
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Figure 4.40. Verilog code for a four-bit comparator.
modulecompare (A, B, AeqB, AgtB, AltB);
input[3:0] A, B;
outputregAeqB, AgtB, AltB;
always@(A, B)begin
AeqB = 0;
AgtB = 0;
AltB = 0;
if(A == B)
AeqB = 1;else if(A > B)
AgtB = 1;
else
AltB = 1;
end
endmodule
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Table 4.3. Precedence of Verilog operators.
moduleaddern (carryin, X, Y, S, carryout);
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Figure 4.41. Using the generateloop to define an n-bit ripple-carry adder.
( y , , , , y );
parametern=32;
inputcarryin;
input[n-1:0] X, Y;
output[n-1:0] S;
outputcarryout;wire[n:0] C;
genvark;
assignC[0] = carryin;
assigncarryout = C[n];
generate
for(k = 0; k < n; k = k+1)begin: fulladd_stage
wirez1, z2, z3; //wires within full-adder
xor(S[k], X[k], Y[k], C[k]);
and(z1, X[k], Y[k]);
and(z2, X[k], C[k]);
and(z3, Y[k], C[k]);or(C[k+1], z1, z2, z3);
end
endgenerate
endmodule
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Figure 4.42. Use of a task in Verilog code.
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Figure 4.43. The code from Figure 4.42 using a function.
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Figure 4.44. Circuit for Example 4.24.
w3
w2
w1 w2
w1
w0
1 En
y0
y1
y2
y3
y5
y4
y6
y7
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Figure 4.46. Circuit for Example 4.26.
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Figure 4.47. Binary to Gray code conversion.
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Figure 4.48. Circuits for Example 4.28.
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Figure 4.49. Circuits for Example 4.29.
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Figure 4.50. A shifter circuit.
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Figure 4.51. A barrel shifter circuit.
module mux4to1 (W, S, f);
input [0:3] W;
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Figure 4.52. Verilog code for Example 4.32.
input [0:3] W;
input [1:0] S;
output f;
wire [0:3] Y;
dec2to4 decoder (S, 1, Y);
assign f = |(W & Y);
endmodule
moduledec2to4 (W, En, Y);
input[1:0] W;inputEn;
outputreg[0:3] Y;
always@(W, En)
case({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
moduleshifter (W, Shift, Y , k);
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Figure 4.53. Verilog code for the circuit in Figure 4.50.
s e (W, S , , );
input[3:0] W;
inputShift;
outputreg[3:0] Y;
outputregk;
always@(W, Shift)
begin
if (Shift)
begin
Y[3] = 0;
Y[2:0] = W[3:1];k = W[0];
end
else
begin
Y = W;
k = 0;end
end
endmodule
d l hift (W Shift Y k)
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Figure 4.54. Alternative Verilog code for the circuit in Figure 4.50.
moduleshifter (W, Shift, Y , k);
input[3:0] W;
inputShift;
outputreg[3:0] Y;
outputregk;
always@(W, Shift)
begin
if (Shift)
begin
Y = W >> 1;k = W[0];
end
else
begin
Y = W;
k = 0;
end
end
endmodule
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Figure 4.55. Verilog code for the barrel shifter.
modulebarrel (W, S, Y);
input[3:0] W;
input[1:0] S;
output[3:0] Y;
wire[3:0] T;
assign{T, Y} = {W, W} >> S;
endmodule
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Figure 4.56. Verilog code for Example 4.35.
moduleparity (X, Y);
input[7:0] X;
output[7:0] Y;
assign Y = {^X[6:0], X[6:0]};
endmodule
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Figure P4.1. A multiplexer-based circuit.
i
3
i4i5
i8
f
i2
i6
i1
i7
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Figure P4.2. Code for Problem 4.18.
module problem4_18 (W, En, y0, y1, y2, y3) ;
input[1:0] W;
inputEn;
output reg y0, y1, y2, y3;
always @ (W, En)
begin
y0 = 0;
y1 = 0;
y2 = 0;y3 = 0;
if (En)
if (W = = 0) y 0 = 1;
else if (W = = 1) y1 = 1;
else if (W = = 2) y2 = 1;
else y3 = 1;end
endmodule
module dec2to4(W En Y);
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module dec2to4(W, En, Y);
input[1:0] W;
inputEn;
output reg[0:3] Y;
integer k;
always @(W, En)
for (k = 0; k