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Examples of operating system Windows 95/98/2000, Windows NT Unix, Linux, VAX/VMS IBM MVS Novell Netware and Windows NT:
Client/Server model
Objective
how Virtual Memory works; the limitation and inaccuracy of
data the internal structure between
DRAM and Video RAM; and the function and location of Cache
memory.
Overlay
Divide the program into several manageable smaller overlays to be stored on the disk
Load the first overlay into the memory and run for a while.
When it finishes, it reads the next overlay into the memory to perform program execution.
Idea of virtual memory
Allow programmers to write programs without paying attention to the size of the program
Programs could be as large as necessary
run even though the whole program would not fit into the main memory.
Hardware and software
Break program (code + data) into pages (page means fixed length data block.)
Keep all code/data pages on disk Brings pages from disk into
memory only as needed by the programme only.
To implement virtual memory, we must be able to: break code/data into pages recognize when a given page is
not present in memory be able to bring the missing page
into various places in main memory
Difference Between Virtual Address and Physical Address Compiled addresses are called
virtual addresses for this reason. Physical address refers to the
address in the main memory.
Mapping
Mapping is about the virtual addresses to physical addresses.
It is composed of two parts, page # and offset
Example in a 16 bit virtual address has: 4 bit page # (can be changed for
different physical frame) 12 bit offset
Addressing
For example 12310h, The page number is 0011, the first
four digits, The offset is 12310 - 12288 = 22.
Virtual to Real addresses to map one virtual address to
several different locations in physical memory.
For example 12310
The page number is 0011 in binary, which is 3 in decimal
The offset is 0000 0001 0110 in binary, which is 22 in decimal
If PAGE 3 was stored in page frame 0, the page is 0 offset = 22
Windows NT
All early PC using 8086 and 80286 used a segmented model.
A segmented addressing system divides physical memory (RAM) into units of continguious address, called segment.
the page size for Windows NT is chosen as 4K bytes
Memory error Detection /Correction deals with basic error detection
and protection to ensure the data in the memory is accurate
invisible to software; and set/checked by hardware only
Hamming Codes Suppose there is an m-bit word, how
many extra bits are required to detect and correct the single bit error.
2^n >= 2m(n + 1) Since n = m + r 2^(m+r) >= 2^m (m+r+1) 2^r >= m + r + 1 it is more efficient to apply this error
checking for large word size but not for small word size.
DRAM and SRAM
DRAM uses capacities to hold the data and needs refreshment to store the data as a capacitor
Video memory
Video DRAM is a conventional DRAM with an additional 256 bit shift register on board.
This shift register is connected to help download a complete row of memory cells.
The shift register has its own output which can be controlled with separate input lines to the video DRAM.
Cache Memory
Cache is a French word which means “to hide”.
Cache memory refers to the memory that is invisible.
This helps to speed up the operation.
characteristics for cache memory It is usually built within a CPU/board chip
to facilitate the frequently used commands. Most frequently used code/data in memory
is also kept in cache but invisible to software.
When program accesses this code/data, it comes from high speed cache rather than from slower main memory.
Cache memory is small, high speed memory usually on-chip or on same board as CPU.
Cache Design
size how much will fit on a CPU/board? at what point does increased size
result in small improvements in hit rate? Issues
Cache Performance
Mean access time = [cache memory access time] + (1-h)*[main memory access time]
h refers to the hit rate Note that as h -> 0 the cache
memory is a little worse than main memory alone.
Example What is the effective memory speed
of a cache-main memory system with the following characteristics?
main memory access time is 100 nsec
cache access time is 20 nsec the hit rate is 95%
Using the formula, the effective memory speed is 20 + (1-0.95)x100 = 25 nsec