Chapter 7

Design and Optimization of Cross-Coupled OTA

7 .1 lntroduction

Scaling of analog modules is not obeying rules of digital circuits. Therefore

migration from one technology to another needs <;omprehensivc redesigns. We have us~d

our design and optimization flow, proposed in chapter 3 of this thesis, to scale the OTA­

h::i~ed FPAA from 2um to 0.35um CMOS technology. This design and optimi7.alion

procedure is presented in detail in this chapter. Accordingly OT A nnd its inlernul

modules were~ optimized 10 get the bcsl performance specifications for the CAOs in

0.35um CMOS technology.

7.2 Design of OTA

for 0.35um CMOS technology, the equations for various parameters such as gain,

power dissipation, output impedance, etc. are derived along with the saturation conditions

of each transistor. According to design specification the aspect ratios of all MOS

transistors nre obtained. With these dimensions circuit is simulated and the results are

analyzed. The process is repeated till satisfactory result, i.e. not fulfill ing the desin::d

specifications, the circuit is re-design. The process parameters required for hand­

calculutions is downloaded from MOSIS web site. The required Lambda, channel length

modulation parameter, is calculated using simulation.

74

Channel Length Modulation parameter (Lambda)

The drain current remains constant once Vos > V os-Y.r. But actually as drQin

voltng<.: increa:scs the channel length is reduced resulting in increased current, i.e. the

length of the invertoo channel gradually decreac;;es as the potential difference between the

gate & drain increases. This phenomenon is called Channel Length Modulation Effect.

The saturntion rctsion model is given by,

(7.1)

where, A. is the channel length modulation parameter. A. is also given by,

(7.2)

The schematic used for calculating Lambda is shown in Fig. 7.1. The circuit,

shown in fig. 7.1, is simulated in 0.35um mixed-mode: CMOS te~hnology. for NMOS,

W = 2um; L = 0.4um, & for PMOS, W = 2um; L = 0.4um, and Gate to Source voltage is

varied from 0.6V to 2.8V.

.__ _ _J ...

(a) (b) Figure 7.1 Schematic used for calculating Lambda (a) for PMOS; (b) for NMOS.

From DC & AC analysis lo vs. Vos & ro vs. Vos plots are Obtained for different

values of Vos· From these two plots r0 vs. lo plot is obtained and then using this graph the

75

lambda for NMOS is o 3y-1 ft . 1

CMOS technology.

. , ur PMOS IS o.2v· is obtained for 0 35 um . d · rn1xe - mode

7.2.1 Simplified Programmable OTA Circuit

The com I t · · d' Pe e c1rcu1t iagram of the OT A is shown iu Fig. 7.2 l 14). l'he circuit

contains following blocks

I) Cross coupled OT A

2) floating voltage source

3) Current mirror array

4) Current source

S) Common mode feedback circuit

6) ProW'ammable Current Array

111 un.11;;r lo oblai.11 a wide range of application frequencies in OTA-C filter design,

it is necessary that the transconductance of the OT A should be adjustable in a wide range.

The change in transconductance can be achieved by tuning the floating bias voltage by an

analog voltage. The only requirement is that it should provide required voltage shifling

with very low impedance.

7.2.1.1 Cross-coupled Architecture

The simplified schematic diagram of the OT A based with two cross-coupled

differential MOS pairs is shown in Fig 7.3. Two cross-coupled differential pairs with

MOS devices Ml-M4 are operating in saturation. Both pairs arc biased by a de current

lss in comhination with an adjustable floating voltage source V~ with low output

resistance. Vb is connected between the common-source nodes C and D.

76

Vin+

Figure 7.2 Simplified schematic diagram of the CMOS programmable OTA

Thus, this topology of the transconduclors circuit does not introduce additional

internal nodes, resulting in improved high-frequency performance. In the range of

operation 210 is ru>sumed constant and tuning is achieved by adj usling Yh.

Figure 7.3 Cross-coupled architecture

77

The process parameters for 0.3Sum CMOS technology given in Table 7. I, are

used for simulation throught this thesis.

Table 7.1 Process parameters for 0.3Sum CMOS technology

-Parameter Value

Yoo 3.3V Vss OV YTn 0.45V

VTn 0.65V µnCox 158uANi µpCox 66.89uANi

11) Design of Cross-Coupled OTA

The circuit is redesigned in 0.35um lc;;i;hnolugy from 2um technology. The

reference design (2um) is taken from reference paper [ 14 J. The design is converted into

OJSµm technology by the following manner.

(7.3)

By using CMOS process paramcler values for 2 um and .35um technology,

(µ Pc •• ) oJSµm = 66.89*10 -b = 3

.546 ( µ C ) I S 8 . 3 3 • 1 0 _,

r ox 2i.am

Now using equation (7.3) relation (7.4) can be derived.

- 3 546 Jfl ..... - . ( ~ )

' ""'°

(7.4)

78

The aim was to keep the transconductuncc of cross-1.:oupled OT A unchanged

while redesigning the circuit in 0.35um technology. This was because of the requirement

to get the same filter specifications but with reduced power. Therefore

( ~ ) (~) (~J = ,,. = _ 3 - "' 0.46 ... 0.5

L 3.546 3.546 1> u,..

(7.5)

Considering In as current flowing through transistors MI, M2, M3 and M4 and

using equation (7.1) (neglecting the A. term)

ID = 0.5 * (µp COX ~ )o.35µm * ( vg~t )1 (7.6)

where (µpCo.)OJS~m = 66.89 uAJV2 an<l v8 .. = - 0.8V. Therefore lo= 10.SµA

and 1ss = 42~iA. Accordingly value of design variables W ,L, lss, Vcm (common mode

voltage) are given in Table 7.2

Table 7.2 Value of design variables for designed cross-coupled OTA

Variable Value Wl = W2- W3= W4 0.6um Ll-1.2=L3~L4 l.2um

Iss 42uA Vern l.6v

W5=W6 !Oum L5=L6 3um

Simulation Rcsulb

The Cross-Coupled architecture in Fig 7.3 was simulated using Cadence's

Custom TC Design Tools in 0.35um CMOS technology with process specifications given

in Tahle 7.1. The Vb varies from 29mV to 460mV with Iss = 42uA. Fig.7.4 shows the

transconductance of the simulated cross-coupled architecture for the frequency range

79

from I OOITz to 1 GHz, V h is taken as a parameter. The simulation result shows that this

cross-coupled architecture has the bandwidth ofZOMHz.

AC Rosyon,.

• : \'b • "460m"; •: \'b . "+12.lm"; , ; \'b•" J64.2m" ; ... lo~"315.3m"; • : \'b •"26B.11n" ; 8.0u a : \'b •"220.6m"; • : \"b ... "172.7m", • . \'b •"124 .8m"; • : \'b • "76.89m"; • · \'b •''29m":

7.0u --- - - - - - -----6.0u r---~---------.-----.~

5.0u ;---------------------

~ ... ,,u ;------------------~--

.J.0u !:-------~--------~

?0u lo----~---------.-----~~

1.0u r------------- -----0.~

1K 101<---· ·~ lM 10M 100M froq ( llr )

Figure 7.4 Transconductance vs. frequency of designed OT A

The transconductance varies from 0.45uS to 7.7uS when vb changes from 29mY

to 460mV. As shown in Fig 7.5, the cross-coupled architecture works linearly for the

range ofVid -0.2V to +0.2V for the change in Vb from 29mV to 461mV. The Table 7.3

shows OTA has good linearity. Average power comiumption resulted from simulation

was D9uW.

Table 7.3 THD simulation results of cross-coupled OTA

Vb (mV) TIID (db) ·-22 -71.92

230 -68.9 460 -67. 19

80

AC Response

9.0u

8 0u \'• • ''461m '*

7.0u \''\'- •"413m11

\'• • "365m" 6.Gu

'\',•"J17m" 5.0u

<( "• •"269m"

~ -t .0u \', ="22 Im"

3.0u ''• •"173m"

2.0u ,., •" 125m"

"• -"77m"

1.0u \\ -"29m"

00 -J00m -200m - 100m 0.00 100m 200111 J00m

vidholf

Figure 7.5 Transconductance vs. Vid (half) of designed OT A

In order to maximize linearity and minimize power consumption of the design

CADENCE oplimizer was used. Table 7.3 gives the THD (Total Harmonic Distortion)

simulation resull of cross-couple OTA which shows lhe better linearity.

b) Second Order E ffects of C r oss-Coupled OT A

Second-order effects, such as mobility reduction, body effect an<l channel length

modulation, cnusc deviations from the iueul square-Jaw behavior of MOS devices. As a

result, the transfer function will no longer be strictly linear (14).

Using the standard square-law model for MOS devices, relations (7.7) and (7.8)

are given for currents T, rmd Ii shown in Fis. 7.3.

(7.7)

(7.8)

81

Where K = 0.5µC.., W/ L . h d f 1:> I e transcon uc1ancc parameter o transistor MI -M4

having the same W/L ratios, VTHP is the threshold voltage, Vb is the voltage of the

floating DC source and Yx, Yv are the gate-source voltages of transistors Ml and M2

respectively. With relations (7.7) and (7.8) the difference between currents 11 and 12 can

be expressed as relation (7.9).

(7.9)

h Vid=V..x-Vv · th d'ffi · i · I w en: is e 1 erenua mput vo tage.

As a first-order approximation, mobility reduction in MOS transistors may be

modeled as equation (7.10) 19J.

(7.10)

where µ0 is the zero-field mobility of carriers. 0 = l/(ToxECR) is the coefficient of

the effect of the electric field on the mobility, Tox is the gate oxide thickness tmd EcR is

the critical field. The dependence on the bulk-source voltage resulting in body effect is

an other potential cause of nonlinear behavior in the voltage-to-current (V- I) conversion

of lhe transconductor circuit.

The derivations (7.7) & (7.S) were performed under the assumption that both pairs

Ml , M2, and M3, M4 sit in their own wells so that body effect is avoided. ff this is not

the case, transistor Ml- M4 nonnally have their bulk co1mections tied to supply volt.age.

As a result, the bulk-source voltages Vasi , 2 and Ves3, 4 are not equal to zero and the

threshold voltage, VTp, can be expressed as equation (7.11 ).

g2

(7. 11 )

where V,., is the threshold voltage for Yus = 0, y the bulk threshold parameter,

and <I> the strong-inversion surface potential. If a p-well CMOS process is used and MOS

dcvic\::s are pul Into p-well connected to lhc respective sources, no body effect occurs and

Assuming different transconductance parameters K 1.2 and K3.4 for the pairs MI,

M2 and M3, M4, respectively, including relations (7. 10) and (7.11) in (7.7) and (7.8) and

using a Maclaurin series expansion, (7.9) can be approximated by (7. 12), where Vq as a

function ofYad is approximated by (7.13) [9).

(7.12)

It follows from relation (7 .12) an npproximatc cancellation of third-order non-

linearity can be achieved via properly scaling W IL ratios of both cross-coupled pairs M 1,

M2 i1.m.1 M3, M4 according to equation (7.14).

83

K12 [B(V, + Vn,2)- 1]4 K:.4 = (B(Vq +vb+ vT3,4 )-11•

(7.14)

where K 1, 2 and K3. 4 are transconductance parameters of transistors Ml , M2 and

M3, M4, respectively. Note however, that for a given Vb the scaling indicated by (7.14)

works well only for constant Vq, i.e., if the dependence of (7.13) on V,d is negligibly

small. Using relation (7. 14) third-order nonlinear tcnns in the equation (7.12) is canceled,

resulting in the linearized transconductance at VbCmid) shown by relotion (7. 15) (9].

The relation (7 .15) was used for MATLAB programming to compare "Gm"

values once considering second order effects und once neglecting second order effects.

f or first order approximation, relations (7.7) nnd (7.8) lead to rela1iu11 (7.16). rn (7.16)

considering Vx:r = Yx - Yr"' and VYT= Vv - Vmp

84

where V x 2 = V v 2 = V ~G (Gate-source bias voltage of MI an cl M2)

.. I I - l 2 = v id ( -2 K I v T + 2 K 3 v T + 2 K 3 vb) (7.17)

Thus fina l general expression for Gm is given by relation (7.18) and the relations

(7. 19) and (7.20) gives the relation for Gm at Vb(maxl and Vb(min» respectively.

G111 =2(K3Vb + K3VT - K1Vr )

G m,mux =2(K3Vb.max +K3Vr - K1VT)

Gm.min = 2(K3 vb,rnin + K3 VT - K, VT)

(7 .18)

(7.19)

(7.20)

By considering second order effects and solving the equations using MATLAB

the values of the design variables were obtained and those values were used for

simulation. The simulation results showed that cross-coupled architecture nullifies the

second order effects.

For 0.35 CMOS process technology second order effects are ne::gligible, due to

small value of e if widths of transistors Ml -M2, M3-M4 arc changed or equal, results are

not affected. Also it is observed that the effect of mobility reduction is less in case of /

PMOS transistors. By proper sizing of channel lengths chnnncl-lcnglh modulation as a

source of nonlinear distortion is negligible [9.59),

c) CADENCl: Optimization Toolbox

Opdmlzation JS the proce3s v f 11utomutica1Jy modifying dec:ign voriQblc~ ;iv that

optimized sp~ifications are achieved l57]. The tool that performs optimization is called

optimizer. Otlen the optimizer can take a design that is close to meeting performance

85

spec1 fi ca1ions ond generntc new component values that bring the design into the

acceptahle performance. A circuit, as originally designed, often foils to me~t all desired

specilications. Ry using CADENCE optimizat1on toolbox f59], goals such as THD and

uver.tge I" were minimized. Variahlcs. w hich urc considered for this d1;:sign, arc lss, W

and L. Design was optimized for middle values of V h (230m V). TI ID values und average

power dissipation before optimization and uftcr optimization a.re shown in Table 7.4.

Table 7.4 THD values bcforu optimization and after optimization

vb THO (db) nmcdb) Power(uW) Power(uW) W(nm) L (um) (mV) Ocfore AJlcr Defore Afttr After Al\cr

optimlzatioo 01>1imizatlon optimizntlou op111111mtfon opumi1.ation onrimizntion 22 -71 -73.03 118.6 46.2 529.6 1.45 -230 -68 -77.02 13 8.6 26.4 503.3 3.622 460 -67.19 -76.15 138.6 30.6 577.8 3.015

Table 7.4 shows how THD and power values are reduced using Cadence

Optimization Toolbox. CADENCE optimizer automatically changt:s design variables in

order to obtain the desired goal.

7.2.1.2 Floating Voltage Source (FVS)

In order to obtain a wide range of application frequencies in OT /\-C filler design,

it is necessary for the transconductance of the OT/\ to be adjustable in a wide range and it

<.:an lx: achieved using floating voltage source. To preserve the high lin~rity of the

transconductunce, voltage source Vb requires very low output impedance. TI1us it is very

important to have a floating volto.ge source with low output impedance.

86

A} 4-M03 Floating Voltiage Source

A suitable low-vohuge CMOS voltage source is shown in Fig. 7.6 [60]. The high

gain negative feedback loop containing transistors M 1 through M4 stabilizes the output

voltage over a wide range of the current Iioad = Id3 + ld4• The output resistance of circuit

can be derived as t:<.juation (7 .2 1 ).

Ro = (Ysm3 + Ysm2) + X1111 gml ro4 gmJ ro3

(7.21)

Where, gtlln and r00 is transconductance and small signal output resistance of n 1h

MOS device respectively.

\'DD

Uond _t, .. , \'0111

l\14

Figure 7.6 Schematic diagram of 4-MOS floating voltage source

For the FVS shown in Fig.7.6 the voltage:: Vb can be defined as relation (7.22).

The reference current of 4-MOS FVS is given by equation (7.23)

l bius = l ctrl + l m2

Where the current l ctrl and 1012 are given by equation (7.24) and (7.25)

(7.22)

(7.23)

87

lart =~µpCox(~l (v,,1 -\vTHp\)2

lm, =tµpCox( ~l (v,si -IVrnplf The minimum source-gate voltages to keep the transistor in active region are

for M3.

v -IV I= ~(J:.) .3 ~ ll w 1-'p ~

v -IV I= Ii. .. - I"rt (~) ,.2 n1p A W f'p 2

Where the~" & PP are defined as P. -tf'.Cox and ll, =iµpCox

The load current 11oad is given by

f lood = + µnCox ( ~: ). (v •• - VTHn r Where the v gl is given by vgl ) ~/r/- - VTH11

(7.24)

(7.25)

(7.26)

(7.27)

(7.28)

The circuit was simulated using process parameters of 2um CMOS technology

and aspect ratios as (W/L) M1=2110, (W/L) Mi=30/2, (W/L) M3=30/2, (W/L) M4= 2/24.

The simulation result shows that Ibias = 15 uA and Rout = 34 K Ohms. i.e. 4-MOS floating

voltage source (Architecture-I) (Fig.7.6) provides very high output resistance at low bias

current.

The cross-coupled OTA works properly for control voltage range 1.9V to 3.1 Y

(54]. According to (7.22) & (7.29), the output resistance of FVS (Fig.7.6) depends on the

load current. From simulation results, the range of programmable current source is 42µA

to 60µA. For this range of load current. FVS shown in Fis. 7.6 providc.;s t11e very high

output resistance.

88

B) CMOS Floating Voltage Source (2um)

To reduce the output impedance of the floating voltage another topology is used

from main reference paper l14]. Fig. 7.7 shows the CMOS FVS architecture

(Architecture IT) which consists of differential pair, current mirrors and standard cascode

current mirrors, along with transistor Mvb6 acting as MOS diode. Such type of floating

voltage source has been used in the cross-coupled OT A.

vdd

Wvb18

~no

Figure 7. 7 Schematic diagram of CMOS FVS (2um tech.)

The voltage difference at the output terminals of FVS mainly depends on the gate-

source voltage of tnmsistors as shown in rel:ition (7.29) and The output rcs:s tnnce mninly

89

clcpcnu:s vu the vc1luc uf uutpul rc:si:sli:1fll;C ur tnm:si:slur MvbJ emu MvM i:1:S well i:1:S un luup

gain and is given by relation (7.30) [14].

T-:; =~13 +~2-~1 -V.ll?6

(Rob6 Pros)

(7.29)

(7.30)

Aspect ratios (W /L) of the transistors used in this FVS are obtained by

calculations. The FVS (Fig. 7. 7) was simulated using process parameters of 2um CMOS

technology. Fig. 7.8 illustrates the simulated output voltage of the floating voltage source

versus input control voltage. Simulation results show that, this Floating Voltage Source

provides u voltage shift 55mV to 550mV for control Voltage varying between l.QV to

3.1 V while the output resistance is l 35ohms. This architecture exhibits low oulput

impedance with low power dissipation.

600m

500m

+00rn

)o ~camm

Z00tn

I ~~

D.~O Loi a ........... ~ ......... ~.,-;. •• ~ ........... ~+.-2.,...J ........... ~....__,.,H),......_~~"t:c . ...,_:~~~'*~~~~J .. 1 ., •ot;,

Figure 7.8 Voltage shifts of CMOS FVS (for Fig.7.7)

90

C) Propo:sed CMOS Floating Voltage Source

The proposed (improved) architecture is shown in Fig.7.9. This CMOS FVS

consists of differential pair, current mirrors and standard cascode current mirrors, along

with transistor Mvb6 acting as MOS diode. To achieve the large range of bias voltage in

0.35um CMOS technology, low-swing cascode current mirror circuit is used as shown in

Fig. 7.9. This low-swing cascode current mirror increases the voltage headroom for

Mvb I & Mvb2, this helps to increase the range of bias voltage for the floating voltage

source in 0.35um technology. T he voltage difference at the output terminals of FVS

mainly depends on the gate-source voltage of' transistors see equation (7.30).

Mvb3

vin

\/Out

11

vdd

Mvb4

na

Mvb16

Mvb13 gnd

Mvb15 Mvb18

Figure 7.9 Schematic diagram of improved CMOS FVS (in 0.35um tech)

91

AC analysis shows that the output resistance at the outpul lcnninals mainly

dcpcnd:s on the value of output resistance of transistor MvbS nnd Mvb6 as well as on loop

gain.

(Rob6 Pros) Rour = 1 + T

Where Tis Loop guin of tloating voltage source given by

T=Avxf

Where Av is forward gain and f is feedback gain given by

Where. ~ = Output resistance of cascade current source

Therefore the relation may be rewrillen as (7.35)

(7.3 1)

(7.32)

(7.33)

(7.34)

(7.3~)

The relation (7.35) shows that the transistors Mvbl. Mvb2, Mvb5, Mvb6 and

Mvb13 are the ma.in deqign clements vf nooting voltase :iOUJCC. The only condition

applied to the floating voltage source is that Vgs2 > Vgsl. Aspect ratio1; (W/L) of the

transistors used in this improved FVS are obtained by manually is given in Table 7.5.

Simulation Results

The schematic Fig.7.9 is simulated in Cadence Analog Design Environment in

OT'ium CMOS technology with procc:ss spc~i fi1.:111ions given in Lhe Table 7.1. Aspect

ratios (WfL) of the transistors used in this i:vs arc obtained by calculations and Vo() a

3.3V, Vss - OV & Vbins = IV. The simulation results (Fig. 7. 10) show thal the FVS

92

provides a voltage shift 29mV to 460mV for control voltage varying between lV to 2.3V

while the output resistance is 55.58 ohms.

Table 7.5 Aspect ratio of MOS tramistors of manually designed FVS

Transistor W /L

Transistor W/L

(um) (um)

Mvbl 3/ 1 MvblO Ill Mvb2 3/ 1 Mvbl I 3/1 Mvb3 1/ 1 Mvb12 311 Mvb4 1/ 1 Mvbl3 Ill Mvb5 250/ 1 Mvb14 1.311 Mvb6 0.811 MvblS 2/1 Mvb7 3/ 1 Mvbl6 Ill

Mvb8 311 Mvb17 3/ 1

Mvb9 1/1 Mvbl8 1/1

rt J.i~''I ••II ..,,

ec-•m

~00m

JC'Jf}t11

-.. 200m

1~m

CO.P>ft I .__ '----' .. - · .J> _....._ • U IC. I 24

.. _ .... ...... . . . . -··· .... ~ ·- · . .... .. · "-·- ·. 1 .~, Ve 1. 7s :>.1>•

_._ .. · 2.J.o«I

Figure 7.10 Floating voltage vs. control voltage (Ve) (for Fig. 7.9)

Optimi1,ation ofFVS using MATLAB optimization toolbox

As the optimizer takes a design that is close to meeting performance

specifications and generate new component values that brings the design into the

93

ncccptablc performance range. Hence the aspect ratios obtained from manual design are

used ac; an initial guess for optimization of various objectives such as power, area, etc. in

MATLAB optimization toolbox.

Since power is our main concern here objective is used as power in terms of

average current consumption of the floating voltage source and minimized it using

MATLAB optimization toolbox. Herc, to minimize the power in terms of average current

consumption. the various con~traints arc considered such us limits on device sizes, bias

conditions and output impedance as follows.

a. Limits on Device Sizes

Lithography limitations and layout rules impo:se minimum (and possibly

maximum) sizes on the transistor

(7.36)

Where, i = l,. . ., 6, 13

These constraints can be expressed as posynomial constraints such a:s Wmi,./W1 s l. Since

W 1 is vtlfiable (hence, monomial), the sizes of certain devices can also fix, i.e., impose

equality constraints.

b. Bias Conditions

The bias conditions are that each transistor Mvbl ... Mvb6, Mvbl3 should remain

in saturation for all possible values of the input common-mode voltage and the output

voltage. The important point here is that the constraints are each posynomial inequalities

on the design variables and, hence. can be handled by l!eometric programming.

94

ForNMOS:

For PMOS:

• Transistor Mvbl:

• Transistor Mvb2:

~.~. • Transistor Mvb3:

Where, V,1m _,, 0

Where, V11in < 0

~) (V,,_ ~ V.,,,,,.,,., -lv,i.p\ L s

(7.37)

(7.38)

ince V gd.3 = 0, transistor Mvb3 1s alway~ remain in saturation no

additional constraint is necessary.

• Transistor Mvb4:

I ( W) ( - V,.P + V mi - Y;.,.,.., + V ••• -J1,Co,.. -2 L 3

(7.39)

• Transistor Mvb5:

(7.40)

• Transistor Mvb6;

Since V~0.6 - 0. transistor Mvb6 is always in saturation and no additional

constraint is necessary.

95

• Transistor Mvb13:

As source of Mvbl3 is connected to VDD so it will always remain in

sat\lration no additional constraint is necessary.

As the saturation condition of Mvbl satisfies the saturation condition of

Mvb4 and tht: saturation condition of Mvb5 satisfies the saturation condition of

Mvb3. Hence only saturation conditions or Mvb 1 & MvbS are considered in

constraints.

c. Output impedance

The output resistance at the output terminals mainly depends on the value of

output resistance of transistor Mvb5 and Mvb6 as given in relation (7.35)

Simulation results (MATLAB optimized FVS)

The floating voltage source in Fig. 7.9 was designed and simulated using

Cadence' s Custom IC Design Tools in 0.35wn CMOS technology with process

specifications given in the Table 7. 1. The power supply is Voo=3.3Y, Vss=OY & Vbias =

1 V. Aspect ratios (W /L) of the transistors used in this floating voltage source arc given

in Table 7.6.

Fig. 7. 10 shows the simulation ri:sults of MATLAB optimizt:d FVS. This FVS

provides a voltage shift 27.6mV to 460.9mV for control voltugc varying between IV to

2.3V while the output resistance is l 58.7ohms with the averag~ current consumption

39uA and Area 546.15 um2.

96

Table 7.6 Aspect ratio of MOS transistors of MATLAB optimized FVS

Transistor W/L

Transistor W/L

(um) (µm) Mvbl 1911 MvblO 1/1 Mvb2 19/1 Mvbll 3/ 1 Mvb3 1/1 Mvb12 3/1 Mvb4 1/1 Mvb13 1/ 1 MvbS 300/ 1 Mvbl4 1.3/ l Mvb6 0.811 Mvb15 2/1 Mvb7 3/1 Mvb16 1/1 Mvb8 3/1 Mvbl7 3/1 Mvb9 111 Mvb18 111

Optimization of Floating Voltage Source using CADENCE optimizer

As the MATLAB optimization toolbox does not consider the second order effects

and for fine-tuning of circuit, the CADENCE optimizer is used. For design using

CADENCE optimizer the initial values for a set of design variable::; are u::;ed from

MATLAB optimization toolbox.

;t, ft,,'l'•l'M t•:: Re~~""

169\! -»~·i f'O~fl' :

t~U

i

! -&'~v

~

18~.~ < ' !J'!>1

! · ~\J 182.t

g l -":8•J .__._.. ~

11 ..... t Vb ~ ~~ :i; ' i 1~H ! -~

·- ~;;,) .. '> -· m~

l~\;!11

1.88 .. I

;~ .. zio

J .s> .... i.r,..1 I 89 'SI.> H;i ... :~

Vetri Vetri

Figure 7.11 Simulation results of MATLAB optimized floating voltage source

97

To use cadence optimizer, goals nnd initial valuc:5 fur u set of design variables,

should be specified. The optimizer first determines how the values of the goal expression

vary as a function of changes in the design variables. Then the optimizer changes the

design variables in a maIUler expected to move the values of the expression in the

direction of goals. After the change, the optimizer simulates the circuit to check the

outco1m:. Lf stopping criteria are not met, the optimizer iterates through the optimization

process.

Although MATLAB optimization toolbox minimized the average current

consumption but the output impedance is incn;a:;cd. Hence in Cadence's Optimizer goals

are set to output impedance and power in terms of average current consumption and the

design variables considered are WI. W2. W3. W4. W5. T,.,.. And Ios-

Figure 7.U Schematic of FYS (with irte11l cnrrP.nt ~onrL'e)

vddl

M1J

- CJnd

98

Fig. 7.13 shows the output of the Cadence's optimizer result window for the

circuit shown in Fig. 7. 12. The left side of the shows how the value of goals, i.e. average

power consumption and output impedance of the floating voltage source is changing with

iterations. And the right side of the shows the change the value of the design variable to

achieve the desired goals.

Simulation Results

The proposed FVS (Fig.7.9) was simulated using Cadence's Custom IC Design

Tools in 0.35um CMOS technology with proct:ss paramt:tt:rs givt:n in tht: Table 7.1. Tht:

power supply is Yoo=3.3V, Vss=OV & Vbias = IV. Aspect ratios (W/L) of the transistors

used in lhis Floating Voltage Source are given in Table 7.7

Table 7.7 Aspect ratio of MOS transistors of CADENCE optimized FVS

W/L Transistor

W/L Transistor

(µm ) (µm)

Mvbl 20/1 MvblO 1/ 1 Mvb2 20/1 Mvbll 311 Mvb3 0.8/1 Mvb12 3/1 Mvb4 1/1 Mvb13 l / l

Mvb5 245/1 Mvb14 1.311 Mvb6 0.8/1 Mvb15 211 Mvb7 311 Mvbl6 1/1 Mvb8 3/1 Mvb17 3/1 Mvb9 1/ 1 Mvb18 1/ 1

Fig. 7.14 shows the simulation results of floating voltage source (Fig. 7.9). This

Floating Voltage Source provides a voltage shift 27.33mV to 460.6mV for control

99

Voltage varying between IV to 2.3V whi le the output res istance IS 1'.H ohms with the

average current consumption 39uA and Area 466 um2

!JO

tttt'lltlon

~ I

>()u WJ

:~:------! ~~ ....

:~ ~: ~~~~~~~-----~~·----1 Wt ::r ~

'""~----...... ~"-----'---- ... __ _ '''" ID~

;~:1;,.-.... ==~~,;_ __ ..,_, ___ ...,~--- ~ lttl"'Af101l

Figure 7.13 CADENCE analog circuit optimizer's waveform window for FVS

,,.. p ... , '"' ..

,.~ '81 _ U('lo..J , Powtr

,., ft

,_,g 8

1.) 1 •

g 13r,e '!'.' '-411, . I! • "' ,,,,..

1\q,,

: "' ln Z' t'"' . 711

1211 e - .: tll

tZ" ltf • !'II

12:;e tel> ,_, _ __ ..,, -~,.~~--tN------t. !• ...

1 00 I'" .. 1 ....... ---..-J

· ·""' 2:" \lctat \ c trl

Figure 7.14 Simulation results of CADENCE optimized FVS

JOO

A Table 7 .8 shows the summery of results of optimized d~sign of proposed FVS.

Tobie 7 .Q S ummary ot n::1ult of uptiml~"' \leslgn of designed FV:S

Specification s Manual Design Design using MATLAB Final Optimization (GP-based O ptimization) (Cadence Outimlzcr)

vb 28mV to 46lmV 27.6mV lo 460.9mV 2&mV to 461.lmV

Control voltage l V to 2.3Y IV LO 2.3V lV to 2JV - -/\"erngc output 55 ohm 158.7ohm 130.5 otun imoedance

Area 423.1 Sum2 546.1 5um2 2 381.15um

Average current 46uA 39uA consumption 39uA

7.2. l.3 Programmable Current Source

Fig. 7.15 shows programmable current source [61). A Prognurunable current

source (PCS) can be realized by using two transistors in parallel driven by two different

biasing voltages, in which one biasing volta~e is fixed and other is vuriablc biasing

voltage. If variable biasing voltage becomes zero, then the other fixed biasing voltage

will take care that the current through cross-quad coupled OTA will never be zero.

This programmable current source was :iimulated using 2um CMOS technology in

Cadence's Analog Design Environment. with the aspect ratios of transistors,

(WIL)M11=110/3; (W/L)M12-200/3; (WIL)Mi3=3/12; (W/L)Mi4=3/30; Ybiasl = 2.5V;

VDD ... SV, and V ctrl varies from l.9V to 3. 1 V. The manually calculated and simulation

results are giv1.:n in Table 7.9. The simulation results gives that the output current vnries

(through transistor M12) from 42.6 uA to 60. l l uA for the change in control voltage from

IV to 2.3V.

IOI

r i!'At.••·· -

Table 7.9 Drain current of transistors of PCS (2um)

Vetri 1.9V 2.2V 2.SV 2.8V 3.IV Calculated (uA) 24.3 26.4 29.13 32.2 35.9

Mil Simulated (uA) 18.34 19.89 21.71 23.83 26.26 Calculated (uA) 44.18 48 52.96 58.5 65.27

Mi2 Simulated {uA) 42.6 46.04 50 54.7 60.11

Calculated (uA) 20.8 20.8 20.8 20.8 20.8 Mi3 Simulated (uA) 15.69 15.69 15.69 15.69 15.69 - Calculated <uA) 3.5 5.6 8.33 11.4 15.1 Mi4 Simulated (uA) 2.657 4.173 6.002 8.134 10.56 .____

The programmable current source (Fig.7.15) was scaled manually in 0.35um

technology and simulated.

V<ld

Mi2

Mi3 Mi"1

Figure 7.15 Schematic diagram of programmable current source

The programmable current source designt:u in 0.35um tc:chnology with the

following equations:

The current through Mi2 is given by,

(7.41)

102

and. T03 & 104 is given by,

(7.42)

(7.43)

Simulation Results-

Tht! programmable currenc source shown in Fig 7 .15 wns simuluted using

Cadence's Custom lC D~sign Tools in 0.35um CMOS leclumlogy with process

specifications given in the Table 7.l. Aspect ratios (W/L) of the transistors used in this

Programmable Current Source are: (W/L)Mi1"'lO/ I , (W/L)Mi2""20/I, (W/L)MiJ=0.6/S,

(W/L)Mi4"'0.6/l.2. Simulation results (Table 7.JO) gives that tl1c output current varies

from 19.0 I uA to 58.2uA for the change control voltage from 1 V to 2.3V.

Table 7.10 Simulation result of PCS (0.3Sum)

Vetri lV 1.28V 1.S8V 1.86V 2.3V

Mil 8.179 uA 10.72 uA 14.25 uA 18.72 uA 26.86 uA

Mi2 19.01 uA 24.49 uA 32.01 uA 41.38 uA !\8.2 uA

Mi3 6.26 uA 6.26 uA 6.26 uA 6.26 UA 6.26 uA

Ml4 1.91 uA 4.44 uA 7.98 uA 12.45 uA 20.61 uA

7.2.1.4 Simulation of OTA with .Oegigncd FVS and PCS

The circuit of OTA is shown in fig.7. 16. in which the optimized fVS ,PCS block

are used with cross-couple OT A .

103

Vin+

MS

Vdd

Y 011 Prog. Current Source 1------1~----

+ Floating Voltage Source

Vbias Ye

M6 ~·

.J,Gnd

Figure 7.16 Cross-coupled OT A with FVS and PCS

Simulation Results

The Cross-Coupled architecture (with FVS and PCS) in Fig 7.16 was simulated

using Cadenct:'s Custom IC Design Tools in 0.35um CMOS technology with process

specifications given in Table 7.1. The Vetri varies from IV to 2.3V with lss = l 9uA.

Fig. 7.1 7 shows the transconductance of the simulated cross-cuuplcd architecture

(Fig.7.16) for the frequency range from IOOHz to lGHz, Ycirl is taken as a parameter. The

simulation result shows that this cross-coupled architecture has the bandwidth of 20MHz

and transconductance varies from 4.5uS to 7. 7uS. when Vetri changes from IV to 2.3V.

104

-<

tl.0u

7.0u

S.0u

5.0u

4-.0u

:S.0u

2.0u

I 0u

0.0

·~--~~-----,-r-.-,,-~, ·~-- ----.._ r------------------'---.

..... .. ·'"!:)•J

• .,., .. • 1 .. v

\s•'V

100 ""ii< ___ ... 'i0K--' ·-· - '100K, • ·- · -;·;;r-fN.1q ( Hz }

100M

Figure 7.17 Transconductance vs. frequency (optimized OTA (Fig.7.16))

. .\C R~~pcm . .,."'

9.0u

8.ll•J V::r • 'i..3V

7.0v V ;:r• • 2. 1 Ei$V

v~" -2011v 6.Du

Vo., = 1 Se7V 5. l!u V ::r = 1 7ZlV

.(

V::r • 1.578V >I.Ou

J,(lu Vo " 1.42.lV

V=r = 1.289V 2.Bu

Vc:r = 1 144V Ulv

V ':f = 1V

e.a -:l90m -20Dm - 100r11 D..00 100.,. 200rn

'•idholf

Figure 7.18 Transconductance vs. Vid (halt) (optimized OTA (Fig.7.16))

10

Sll~1n

105

The ratio maximum to . ninimum transconductance is 17. The result also shows

the better THD values that resu.t in good linearity, the average current consumption is

94uA. Fig 7.18 shows the graph of transconductance vs Vid(half), the optimize cross-

coupled OTA works linearly for the range of Vid -02V to +0.2V for the change in Vetri

from 1 V to 2.3 V. Table 7. 11 gives the summary of OTA with FVS and PCS blocks

shown in Fig.7.16 simulated usillg 0.35 um tehnology.

Table 7.11 Summary of result of OTA (Fig.7.16) simulated in 0.35 um

IS

~e

Minimum Transcon Maximum Transcon

Ratio of max/min Trans

THD Average current Con

Bandwidth

~ange

:luctance :luctance

~onductance

)0Khz ;umption

Result of OT A

3.3V IV to 2.3V

0.45uS 7.7uS

17 times

-65dB 94uA

20MHz

7.2.1.5 Programmable Cur (°ent Mirror Array

A current mirror of programmable gain can be realized using the well-known high

compliance current mirror struc1 ure with 31 identical output stages [ 14]. The output

current lout is a sum of the curre1 tts flowing through individual output stages. As can be

seen from Fig. 7 .19, the output ~ tages are connected in 5 groups of 1, 2, 4, 8, and 16

stages that can be simultaneously switched ON or OFF by appropriate switch Si where i

= {l,2,4,8,16}. Using stages, the output current lout can be set to the value from the

equation (7.44).

106

l out \.fin = Tin to l out Max = nl;n (7.44)

With resolution of Al uu• "" 11" only live ourput groups (5 bits) were implemented

due to the huge area of the MOS devices of the most significant bits. 1n prnctice, every

switch Si must be accompanied by another switch Si, which can short-circuit the gate of

the transistor Mia to ground. This is necessary for discharging the parasitic capacitance

Cgs of the lntnsistor Min and stopping the current Ii flowing. The cnsco<led current mirror

structure is used to achieve high output resistance.

F igure 7.J9(a) Programmable curt'cnl mirror

Tnpu' O nrpul

C'ou ll ol Bit"

Figure 7.19 (b) Programmable current mirro1· (CMOS)

107

The Programmable Current Mirror is designed for 0.35 um CMOS technology

and simulated w::ins Cadence' s Custom IC D\::sign Tool. The results are shown in Table

7 . 12. The Output current varies from 03.11 uA to 82.58 uA in 32 steps for input current

7.5uA.

Table 7.12 Simulation results or programmable current mirror

Control Bits O utnut C urrent' (uA) 00001 03.11 000 10 05.92 00100 11 .68 01000 23.58 10000 48.29 11111 92.58

I at Input cutTcm ~ 1.S uA

7.2.1 .6 Common Mode Feedback (CMFB)

'lbe common mode feedback circuit (CMfB) block i:. responsible for regulating

the average output voltage to a fixed de voltage of 2.5 V. The CMFR circuit (transistors

Mcm11>1-Mcmlh10) drives the output current source (transistors Mo1-M04). This current

sourct: consists of two cascaded tronsistors to obtain high output resistance. By reducing

the current flowing through the output stage increases OT As output resistance. But care

must be taken that such reduction will decrease the linear transconductance range.

The problem with fully bnlanced circuit is that no feedback loop exist for

common mode (CM) voltage; CM output, therefore, is undefined and the transistor in the

output stage may drift out of their linear range .To avoid this problem, an additional

feedback loop cnlled Common mode feedbnck (CMFD) should be employed ll41. Thus

CMFB stabilizes common-mode voltages for fully differential OTA by means of

adjusting the common-mode output currents.

108

The lwu uiffcremlJ:il output volfogos arc nvcrui;cd (Yem) and compared with the

common-mode reference voltage (Vrcm), and the differential voltage is converted to lhe

common-mode output current to adjust the common-mode voltage (Yem). Common

mode feedback circuit rejects a difference mo<lc signal on its input and amplifies the

common mode signal. ·n1is is exactly o pposite of w h ut a single diITerential amplilier

docs. Common mode ft:edback circuit (CMFR) block is responsible for regulating the

average output voltage to a fixed voltage of 1.65V (for 3.3V) supply. The CMfl3 circuit

amplifies the difference between the averages of the outputs, an<l common modt: volrnge.

Through the use of feedback, tluough the OT A. the averages of the outputs and common

mode signal are made equal. The CMFB circuit is designed and its gain and phase

margins are determined to check the stability f20,62-63). CMFB circuit is shown in

Fig.7.20 with its gain und phuse mnrgin simulation results shown in Fig.7.2 1.

u ~ . u~ !

icmfb M4 l 1111

'

[i~ 6S ; f ~- ' ; ~·~·

M7 MS "" • .

- · . !Jld ~ !Jld

------------ ---

1 •

Figure 7.20 Common mode feedback circuit

lo2

•

109

19')

i-··~ - · - 180

- Jet

1-1n

'{J Od.B - ....

Phase Curve

.. ........ ..... ' . .... .

: . Magnitude curve ...... ,.,.,,, ....... _ .. .. .......

···--...... -........... . 1--~~~~~~~

. ... . .... . .

.. .... .................. .. .. _. .. ,. .... 1<. ..... ......... ..

..

'lfl.f> l ilt( · ""iee<

• .. • • • . • ...... ··--~·:'-"'""t!!' 6M 10\A ~.. ..,

Freq HZ. IM

Figure 7.21 Magnitude and phase plot of CMFB circuit

T:ible 7.13 shows the result of CMFD circuit for different values of W of output stage

transistors.

Table 7.13 Results of CMFB circuit

W1 =411m Wl - I6um Wl='64Um Specifications

W2•3um w 2- 12um W2'"-48um

UGR 3.JMll.G 6MH.1. 7.2MHz

Gain Margin 26dB 32d0 34d0

Phase Margin 70° 76" 71S"

DC power 3Sut\ 78uA 132uA - Consumption

7.2.1.7 Programmable Capacitor Array (J>CA)

The proposed structure of the programmable capacitor array is shown in Fig. 7.22.

It consists of five capacitors CO to C4 and switches Seo to Sc4. The branch of capacitor

CO and switch Seo represents the least significant bit (LSB). Each branch is built of an

uppropriatt: number of urn branches (connected in parallel).

110

Switches are realized using MOSFETs of width high enough to achieve the

current phase of a capacitor in the range of 90°± I 0 for frequencies up to 10 MHz. Tilt:

equivalent capacitance of the capacitor array can be expressed as relation (7.45).

4

CrQ = L: bn2" (Cm1 -CoF~)+CPAR (7 .45)

""°

- 1

Figure 7.22 Programmnble tapacitor array

In relation (7.44) b,, £ {O, 1} and is equal to I when switch is ON and equal to O

when switch is OFF, and are the capacitances of the LSB capacitor when switches nn: in

ON and OFF modes, respectively, while is the parasitic capacitance of connections when

all the switches are off. Table 7.14 summarizes the parameters of the programmable

capacitor array.

Table 7.14 Parameters of programmable capacitor 1uray

Parameter Value

No. of bits 5

Minimum Capacitance 0.45p f

Maximum Capacitance 6.75p F

Resolution 0.45p F

Occupied Area 46.7u M x ?Su M

111

7.2.2 Simulation Results of Complete OTA

fhe complete programmable OTA is shown in Fig.7.23. The all supporting blocks

designed were included and then simulated using Cadence's Custom IC Design Tools in

TSMC 0.35um CMOS technology. Fig. 7.24 and Fig.7.25 present the simulo.tcd

lrun:;conductance of the OT A for the minimum and mnximum scnings of lhc control

voltage V ctrl and the current gain A. Table 7 .15 summarizes the achieved values of

transconductance. Table 7 .16 and Table 7 .17 give the summary of the transconductance

and bandwidth. The simulation results show lhat this cross-coupled architecture has the

bandwidth of l 00 MHz and the overall transconductance varies from 90.3 1 nS to 52.09uS

when Yc1r1 changes from lV to 2.3V. Overall transconductance range is 576.78 times with

the nveroge eurrent consumption of 94uA.

P a uw nu\uu\\.le C'mYent l\'fln•o1·

Binmy Input Vohage

Conunou lVlo(\e t·eedbark C.'ll·rnit._,........ .... · ••

+-----1---9 Oul-

Pt-oar~•tUt•nLJv Cun f'U t ?vlin OJ

OwGry lnpui Vollago

Out+

Figure 7.23 Complete circuit diagram of the programmable OTA

112

10 ~

!·-·-·-·-···· '-·-· ··-···--·-·~·-·-·-·-· ······-·'- ···-·······-······· .. ····--·-· .... ' ··

10-1 ---- ___ :~-'~'~~:."~--- ·- - ····· -~7~~·~··. -----. 10- - ·-·· ........ .,..-.... . .......... ·-·... ·-· .... j. • •• .. .... ...... . ··-· · · ....... . ... .... • .. .

. bits ..... ·~ I Vctr1~1v from: ~0001 i to: 1111 l ::1 ······- -· ····-- -··· -.... --···· -·· ·······- -· -······-· -·. -. -.... ·· .

. ,_ ......

10- 1•G-0~~~~,-K~~~~~,0-~~~~~-,0-0-K~~~-,-M~~~~~10=t~~~~~~,00~M;--­<"ro:qu~ncy lriz l

Figure 7.24 Simulated transconductance of programmable OT A V.\· frequency

10-4 ··:

1e-

. .... • .... -····· ··--·~::;;::::; ·············· ... -· [-~~,:,:;~,······ . - .... ·-·

-------------------------·------ ---········*·····----------·--------------··--------------------------------------------------···"•' .................. ... ----------·············----------· --------·--········· ·-----------------·----·----·-----··--....... ________ .,_., __ ...

Vclrl=lV bits from:00001 t.o: 1 1111

1e-- ------·-----.. --···--------------t-------·---------· , ______________ _ ......... . ···-------- ·-·---· __________ .,. ______________ ......

10 ...........L. ·--. ~,..----- ' _ __ ..._._~~ .............................. ~ ......... ~~-u...~~ ....... ...., - :l.1!111lm -150m -100m -50.0m 0 .00 50.0m 100m 100m 200m

Vid !VJ

Figure 7.25 Simulated transconductance of programmable OT A Vs Vid (half)

113

Ta hie 7 .15 S imulation r·csuhs of the OTA (Fig. 7.23)

Parameter Value

Maximum Transconductance 52.09u S

Minimum Transconductance 90.3 lnS

Resolution 5 bits

Utn,max/Gm,min through programmable 32.55 times

current mirror.

Control Range of

the transconductance through control 17.72 times

voltage V c1rl.

Overall Transconductance Range 576. 78 times

Table 7.16 Transconduclance Vs Vetri & PCM

Condition Vetri & PCM Transconductance (ut 20 Mhz.)

I VCtrl: I PCM: 00001 Gm = 90.31 n S

2 VCtrl: 2.3 PCM: 0000 I Gm = l.6u S

3 VCtrl: I PCM: 11111 Gm = 2.938u S

4 VCtrl: 2.3 PCM: 1111 1 Gm = 52.09u S

Table 7.17 Transconductance Vs Viti (half)

G m \ Vid -0.2V 0 0.2V

Voltal!e Max Gm 30.2u S 52.06u S 30.2u S

Min Gm 96n S 90.31n S 96n S

Table 7 .18 gives the comparision of complete OT A simulated in 2um technology

l21 I and designed OTA in 3um technology. Results shows that designed OTA is showing

114

better performance wilh respect to specificationi: like power , frequency, linearity

compnired with reference OTA.

Table 7.18 Comparison of complete OT A simulated in 2 um and 0.35 um technology

Specifications 2um CMOS tech. 0.35um CMOS tech.

Supply Voltage 5Y 3.3Y

Control Voltage range 1.9V to 3.IV JV to 2.3V

Minimum 0.09uS 90.3 lnS Transconductance

Maximum 6.JuS 52.09u S

Transconductance Jlntio or max/n-.'11

700 times 576.78 times Transconductance (Vetri and PCM)

THO @0.2 VPP• tOOKhz -37.SOdB -6Sd8

Average current lSOuA 94uA

Con sumption

BundwidCh 20M llz 20MH.t -

Implementation of OT A-Resistors

There is generally little need for resistors in the area of gm-C filters with the

notable exception of source and load resistors in doubly tenninated LC ladders. It need at

least two resistors in a lossless ladder. For sensitivity design, source and load resistor

should be incorporated into the design strategy [ 45).

To realize a resistor, the differential transconductance was taken to connect two

inputs to two different voltages and feed th~ output back to the input as :.hown in fig.

7.26. Always paying attention that feedback is negative, we obtain the two equations

(7.46) and (7.47).

Ii = Io = I = gm* (Vl-V2) (7.46)

11 5

Thus, the resister is R =(VI - V2)fl = II gm (7.47)

We should be certain to maintain the negative feedback when forming the gm-

bnscd resistor. I f the feedback connection bcwmes positive, we simuJate a negative

resistor. Vi I Ii =- - R = - l I gm, in a difTerential form. Such a resistor is used, for

instance, lo compensate the transconductor losses or to illuminolc inductor lo:;,,es when

very smnll but reaJ spiral- wound inductors are used on ICs for filters at the high

ttequem:ies.

I

v~ I

Figure 7.26 Active implementation of a r~ci is tor u s ing "gm" rnod ulu w ith o n"

terminal connected to the ground

The implementation of a floating resistance is more complicated since two

different reference voltages must be created. Therefore, a common practice is to

transform the input voltage source to ai1 input current source (64]. The transformation is

shown in Fig. 7.27. It can be seen that the floating source resistance has been transformed

into n grounded resistance that can be implemented with the structure from Fig. 7.26. The

input current Im• is determined by forcing the equivalence of the two circuits. The

functionality of the sources is equal if the current and the voltage drop on the input

impedance of the LC network are the same after the transformation [64]. Then it holds

true.

V • ZLc 1 • Rsl 1c '" R.~ t Zu • '" . Rs + Z 1.<

(7.48)

116

>l

b l

Figure 7.27 a) Transformation of the input voltage source to an input current and b) The OTA-C implementation

Relation (7.47) results that the equivalent input current source must be scaled with

the reciprocal of the source resistance RS and will be equal to Vin/RS. The

transformation yields the OTA-C su·ucture from the Fig. 7.27 (b), where the fi rst

transconductance amplifier implements the :scaled current source.

An advantage of the llgm resistors is lhat the r1;sistors nre clcc1ronic11lly variable

because they depend on a bias current (or voltage). A traditional integrated resistor,

implemented say, as a diffused or a deposited layer, does not offer this possibility. It is

most helpful in gm-C filter design to have the "resistors" technologically mulch and track

the active devices. Table 7.18 shows the result of OTA-based resistor. The OTA-based

resistor (ideal register) offers a resistance of 19.2 K Ohm to 11.07 M Ohms.

Table 7.19 Simulation result of OTA as a resistor

Vetri PCM Ideal Resistor Grounded Floating Control Voltage Programmable I/gm (Ohms) Resistor (Oluns) Resistor

<Yul ts) l.11rrPnt Source (Olu11:,) Binary

l 00001 11.07M 13.48M 9.39M 2.3 00001 625K 629.92K 615.8~

I 11 111 341SK 500.73K 257.77K 2.3 11111 19.2K 20.l lK 18.82K

117