1

Chapter 5

FIELD-EFFECT TRANSISTORS(FETs)

Chapter 5 FETs 1

FETs is also a three terminal devices. For the FET an electric field is established by thecharges present that will control the conduction path of the output circuit without the needfor direct contact between the controlling and controlled quantities.

DifferencesBJTs FETs

(i) Current-controlled devices (i) Voltage-controlled devices

Current I is a direct function Current I is a function of the voltageCurrent IC is a direct functionof the level of IB.

Current ID is a function of the voltageVGS applied to the input circuit.

Chapter 5 FETs 2

(ii) Bipolar device (npn and pnp) (ii) Unipolar device (n-channel and p-channel)Conduction level is a function ofTwo carriers, electrons and holes.

Conduction level is a function ofone type of carrier, either electrons (n-channel) or holes (p-channel).

2

Types of FETs :

(i) Junction FETs (JFET) and (ii) Metal-Oxide-Semiconductor FETs (MOSFET)

MOSFET can be divided to two types: (i) Depletion type and (ii) Enhancement type(ii) Enhancement type.

The MOSFET transistor has become one of the most important devices used in the designand construction of integrated circuits for digital computers. Its thermal stability and other general characteristics make it extremely popular in computer circuit design.

Chapter 5 FETs 3

CONSTRUCTION and CHARACTERISTICS of JFETs

Ex: n-channel JFETs

The major part of the structure is the n-typematerial that forms the channel betweenthe embedded layers of p-type material.

The top of the n-type channel is connectedthrough an ohmic contact to a terminalreferred to as the drain (D), while the lowerend of the same material is connected throughan ohmic contact to a terminal referred to asthe source (S).

The two p-type materials are connectedtogether and to the gate (G) terminal.

Chapter 5 FETs 4

Therefore, the drain and source are connectedto the ends of the n-type channel and thegate to the two layers of p-type material.

Under no-bias condition, there are two p-n junctions. The result is a depletion region ateach junction. A depletion region is that region void of free carriers and therefore unableto support conduction through the region.

3

Analogy

The source of water pressure can be likened to the applied voltage from drain to sourcethat will establish a flow of water (electrons) from the spigot (source). The “gate”,through an applied signal (potential) controls the flow of water (charge) to the “drain”

Chapter 5 FETs 5

through an applied signal (potential), controls the flow of water (charge) to the drain .The drain and source terminals are at opposite ends of the n-channel because theterminology is defined for electron flow.

VGS = 0V, VDS Some Positive Value

In this figure, a positive voltage VDS has beenapplied across the channel and the gate hasbeen connected directly to the source toestablish the condition VGS=0V.

The result is a gate and source terminal atthe same potential and a depletion region inthe low end of each p-material similar to thedistribution of the no-bias condition.

The instant the voltage VDD (=VDS) is appliedthe electrons will be drawn to the drainterminal, establishing the conventional currentID. The path of charge flow clearly reveals that The drain and source currents are equivalent

Chapter 5 FETs 6

The drain and source currents are equivalent(ID=IS).The flow of charge is limited solely by theresistance of the n-channel between drain andsource.

4

It is noted here that the depletion region is wider near the top of both p-type materials. Assuminga uniform resistance in the n-channel, the resistanceof the channel can be broken down to the divisionsshown in the figure. The current ID will establishthe voltage levels through the channel as indicatedthe voltage levels through the channel as indicatedon the same figure.For example, the upper region of the p-typematerial will be reverse-biased by about 1.5V, withthe lower region only reverse-biased by 0.5V.

Recall from the discussion of the diode operationthat the greater the applied reverse bias, the widerthe depletion region.

Chapter 5 FETs 7

The fact that the p-n junction is reverse biased for the length of the channel results in agate current of zero amperes. The fact that IG=0A is an important characteristics ofthe JFET.

As the voltage VDS is increased from 0 to a few volts, the current will increase asdetermined by Ohm’s law. The relative straightness of the plot reveals that for the regionof low values of VDS, the resistance is essentially constant.As VDS increases and approaches a level referred to as VP, the depletion region will widen,causing a noticeable reduction in the channel width. The reduced path of conduction causesthe resistance to increase and the curve in the graph to occur. The more horizontal the curve, the higherthe resistance If VDS is increased to a level wherethe resistance. If VDS is increased to a level whereit appears that the two depletion regions would “touch”as shown in the figure, the condition is referred to as“Pinch Off” will result.

Chapter 5 FETs 8

VP:Pinch-off voltage

5

In the saturation region, the level of ID remains essentially the same. Therefore, onceVDS > VP the JFET has the characteristics of a source current.As shown in the previous figure (output characteristics), the current is fixed at ID=IDSSbut the voltage VDS (for levels > VP) is determined by the applied load.

The notation of IDSS is derived from the fact that it is the Drain-to-Source current witha Short-circuit connection from gate to source.

IDSS is the maximum drain current for a JFET and is defined by the conditions

Chapter 5 FETs 9

DSS s t e a u d a cu e t o a J a d s de ed by t e co d t o sVGS = 0V and VDS > VP.

VGS < 0 V

VGS is the voltage from gate to source and is the controlling voltage of the JFET.

For the n-channel device the controlling voltage VGS is made more and more negativeFrom its VGS = 0V level. In other words, the gate terminal will be set at lower and lowerpotential levels as compared to the source.

In the figure, a negative voltage of –1V hasbeen applied between the gate and sourceterminals for a low level of VDS.The effect of the applied negative-bias VGSis to establish depletion regions similar tothose obtained with VGS =0V but at lowerlevels of VDS.The result of applying a negative bias to thegate is to reach the saturation level at a lowerlevel of VDS.The resulting saturation level for I has been

Chapter 5 FETs 10

The resulting saturation level for ID has beenreduced and in fact will continue to decreaseas VGS is made more and more negative.

6

The pinch-off voltage continues to drop in a parabolic manner as VGS becomes moreand more negative.Eventually, VGS when VGS = -VP will be sufficiently negative to establish a saturationlevel that is essentially 0 mA, for all practical purposes the dvice has been “turned off”.

Chapter 5 FETs 11

The level of VGS that results in ID = 0 mA is defined by VGS = VP with VP being anegative voltage for n-channel devices and a positive voltage for p-channel JFETs.

Voltage-Controlled Resistor

The region to the left of the pinch-off locus is referred to as ohmic or voltage-controlledresistance region. In this region, the JFET can actually be employed as a variableresistor whose resistance is controlled by the applied gate-to-source voltage.

Note that the slope of each curve and therefore the resistance of the device betweendrain and source for VDS < VP is a function of the applied voltage VGS.d a a d sou ce o DS P s a u ct o o t e app ed o tage GSAs VGS becomes more and more negative, the slope of each curve becomes moreand more horizontal, corresponding with an increasing resistance level.

The following equation will provide a good approximation to the resistance level interms of the applied voltage VGS.

Chapter 5 FETs 12

Where ro is the resistance with VGS = 0V and rd the resistance at a particular level ofVGS.For an n-channel JFET with ro equal to 10 kOhm (VGS =0V, VP=-6V), the above equationWill result in 40 kOhm at VGS = -3V.

7

p-Channel DevicesThe p-channel JFET is constructed in exactly the same manner as the n-channel device.The defined current directions are reversed as are the actual polarities for the voltage VGSand VDS.

Chapter 5 FETs 13

For the p-channel device, the channel will be constricted by increasing positive voltagesfrom gate to source and the double-subscript notation for VDS will result in negativevoltages for VDS on the above output characteristics which has an IDSS of 6 mA and apinch-off voltage of VGS = +6V. The minus signs for VDS simply indicate that the source isat a higher potential than the drain.

Symbols

n-channel JFET p-channel JFET

The arrow is pointing in for n-channel device to represent the direction in which IG would flow if the p-n junction were forward-biased.

The only difference in the symbol isthe direction of the arrow.

Chapter 5 FETs 14

8

SUMMARY(i) The maximum current is defined as IDSS and occurs when VGS = 0V and VDS>=|VP|.(ii) For gate-to-source voltages VGS less than (more negative than) the pinch-off level,

the drain current is 0A (ID=0A).(iii) For all levels of VGS between 0V and the pinch-off level, the current ID will range

between IDSS and 0A, respectively.(iv) For p-channel JFETs a similar list mentioned above can be developed.

Chapter 5 FETs 15

TRANSFER CHARACTERISTICSFor the BJTs, the output current IC and input controlling current IB were related bybeta.

A linear relationship exists between IC and IB. Double the level of IB and IC will increase by a factor of two also.

The above linear relationship does not exist between the output and input quantitiesof a JFET. The relationship between ID and VGS is defined by Shockley’s equation.

The squared term of the equationwill result in a nonlinear relationshipbetween ID and VGS, producing acurve that grows exponentially withdecreasing magnitudes of VGS.

Chapter 5 FETs 16

DC analysis can be performed using a graphical approach and mathematical approach.Graphical approach is more direct and easier to apply. However, it require a plot ofabove equation to represent the device and a plot of the network equation relating thesame variables. The solution is defined by the point of intersection of the two curves.

9

The transfer characteristics defined by Shockley’s equation are unaffected by thenetwork in which the devices is employed.

Chapter 5 FETs 17

Obtaining transfer curve: When VGS = 0 V, ID = IDSSWhen VGS = VP, ID = 0 mA

The transfer characteristics are a plot of an output current versus an input-controllingQuantity. Therefore, there is a direct “transfer” from input to output variables.

If the relationship were linear, the plot of ID versus VGS would result in a straight linebetween IDSS and VP. However, a parabolic curve will result because the verticalspacing between steps of VGS on the drain characteristics decreases noticeably as VGSbecomes more and more negative.

Compare the spacing between VGS = 0 V and VGS = -1 V to that between VGS = -3 V and pinch-off. The change in VGS is the same but the resulting change in ID is quite differentdifferent.

A quick, efficient method of plotting ID versus VGS given only the levels of IDSS and VPand Shockley’s equation.

Applying Shockley’s Equation

Examining a few specificLevels.

Chapter 5 FETs 18

Levels.

(i) VGS = 0 V

10

(ii) VGS = VP

(iii) Selected curve; ex. VGS = -1 V

Chapter 5 FETs 19

Note the care taken with the negative signs for VGS and VP in the calculations above.The loss of one sign would result in a totally erroneous result.It should be obvious from the above that the level of ID can be found for any level ofVGS.

Using basic algebra, we can obtain an equation for the resulting level of VGS for agiven level of ID.

We can test the above equation using the previous output characteristics.

Chapter 5 FETs 20

11

Shorthand MethodSince the transfer curve must be plotted so frequently, it would be quite advantageousto have a shorthand method for plotting the curve in the quickest, most efficient mannerwhile maintaining an acceptable degree of accuracy.

(i) If we specify VGS to be one-half the pinch-off value VP, the resulting level of ID willbe the following, as determined by Shockley’s equation:

Chapter 5 FETs 21

The result specifies that the drain current will always be one-fourth of thesaturation level IDSS as long as the gate-to-source voltage is one-half thepinch-off value.

(ii) If we choose ID=IDSS/2, we find that

As conclusion, the transfer curve can be sketched to a satisfactory level of accuracy simplyusing the four plot points.

Chapter 5 FETs 22

12

Example (1): Sketch the transfer curve defined by IDSS = 12 mA and VP = - 6V.

Solution:

Four points;

(i)

(ii)

(iii)

(iv)

Chapter 5 FETs 23

Example (2): Sketch the transfer curve for a p-channel defined by IDSS = 4 mA and VP = 3V.

Solution:

Chapter 5 FETs 24

13

IMPORTANT RELATIONSHIP

Chapter 5 FETs 25

For the BJT configuration, IB is normally the first parameter to be determined.For the JFET, it is normally VGS.

DEPLETION-TYPE MOSFET

Basic ConstructionA slab of p-type material is formedfrom a silicon base and is referred toas the substrate. It is the foundationupon which the device will beconstructed.

In some cases the substrate is internallyconnected to the source terminal.However, many discrete devices providean additional terminal labeled SS,resulting in a four-terminal device.

The source and drain terminals are connected through metallic contacts ton-doped regions linked by an n-channel.The gate is also connected to a metal

Chapter 5 FETs 26

The gate is also connected to a metalcontact surface but remains insulatedfrom the n-channel by a very thinsilicon dioxide (SiO2) layer.

SiO2 is a insulator: (i) Therefore, there is no direct electrical connection between the gateTerminal and the channel of a MOSFET.

14

SiO2 is a insulator: (ii) Therefore, it construct very high input impedance of the device.Then it support the fact that the gate current (IG) is essentially zeroamperes for dc-biased configuration.

Metal-Oxide-Semiconductor FET or another name Insulated-Gate FET (IGFET)Metal Oxide Semiconductor FET or another name Insulated Gate FET (IGFET)

Metal: for the drain, source and gate connections to the proper surface- in particularthe gate terminal and the control to be offered by the surface area of the contact.

Oxide: Silicon dioxide insulating layer.

Semiconductor: the basic structure on which the n- and p-type regions are diffused.

Chapter 5 FETs 27

Basic Operation and Characteristics

The gate-to-source voltage VGS is set to zero volts by the directconnection from one terminal to theother and a voltage VDS is appliedacross the drain-to-source terminals.

The results is an attraction for thepositive potential at the drain by thefree electrons of the n-channel and a current similar to that establishedthrough the channel of the JFET.In fact, the resulting current withVGS = 0V continues to be labeledIDSS.

Chapter 5 FETs 28

15

Chapter 5 FETs 29

Let set VGS to a negative voltage such as –1 V. The negative potential at the gate willtend to pressure electrons toward the p-type substrate (like charges repel) and attractholes from the p-type substrate (opposite charge attract).

Depending on the magnitude of thenegative bias established by VGS, alevel of recombination between

l t d h l ill th t illelectrons and holes will occur that willreduce the number of free electronsin the n-channel available for conduction.

The more negative the bias, the higherrate of recombination. The resultinglevel of drain current is therefore reducedwith increasing negative bias for VGS.

Chapter 5 FETs 30

16

For positive values of VGS, the positive gate will draw additional electrons (free carriers)from the p-type substrate and establish new carriers through the collisions resultingbetween accelerating particles.As the gate-to-source voltage, VGS continues to increase in the positive direction revealsthat the drain current will increase at a rapid rate for the reasons listed above.pThe vertical spacing between the VGS = 0V and VGS = +1V curves is a clear indicationof how much the current has increased for the 1 V change in VGS.Due to the rapid rise, the user must be aware of the maximum drain current rating sinceit could be exceeded with a positive gate voltage.

As revealed above, the application of a positive gate-to-source voltage has “enhanced”the level of free carriers in the channel compared to that encountered with VGS =0V.For this reason, the region of positive gate voltages on the drain or transfer characteristicsis often referred to as the “enhancement region”, with the region between cut-off and the

t ti l l f I f d t th “d l ti i ”

Chapter 5 FETs 31

saturation level of IDSS referred to as the “depletion region”.

Example (3): Sketch the transfer characteristics for an n-channel depletion type MOSFETwith IDSS = 10 mA and VP = -4 V.Solution:

Before plotting the positive region of VGS, keep inMind that ID increases very rapidly with increasing positive values of VGS. In other words, be conservativeWith the choice of values to be substituted intoShockley’s equation. In this case, we will try +1V asFollows:

Chapter 5 FETs 32

Follows:

17

p-Channel Depletion Type MOSFET

The construction of a p-channel depletion type MOSFET is exactly the reverse of that n-channel depletion type MOSFET. There is now an n-type substrate and a p-typechannel. The terminals remain as identified but all thevoltage polarities and the current directions are reversed.VDS will have negative values and ID will have positive values since the defined direction is now reversed. The reversal in VGS will result in a mirror image for the transfer characteristics.

Chapter 5 FETs 33

SymbolsThe symbols chosen try to reflect the actual construction of the device.The lack of a direct connection (due to the gate insulation) between the gate and channelis represented by a space between the gate and the other terminals of the symbol.The vertical line representing the channel is connected between the drain and source andis “supported” by the substrate. Two symbols are provided for each type of channel toreflect the fact that in some cases the substrate is externally available while in othersit is not. For most of the analysis, the substrate and source will be connected and lowerit is not. For most of the analysis, the substrate and source will be connected and lower symbols will be employed.

or or

Chapter 5 FETs 34

or

18

ENHANCEMENT TYPE MOSFETAlthough there are some similarities inconstruction and mode of operationbetween depletion-type and enhancementtype MOSFET are quite different fromanything obtained thus far. The transfercurve is not defined by Shockley’s equationand the drain current is now cut off untiland the drain current is now cut off untilthe gate-to-source voltage VGS reachesa specific magnitude.

Basic Construction of n-channelEnhancement type MOSFETA slab of p-type material is formed froma silicon base and is again referred to assubstrate.

Chapter 5 FETs 35

Note here the absence of a channel between the two n-doped regions. This isthe primary difference between the construction of depletion type andenhancement type MOSFETs.

Basic Operation and Characteristics

(i) VGS = 0 V and a voltage appliedbetween the drain and source of thedevice, VDS will result in a current ofeffectively zero amperes.With VDS some positive voltage, VGS =0Vand terminal SS directly connected to thesource, there are in fact two reverse-biased p-n junctions between the n-dopedregions and the p-substrate to opposeany significant flow between the drain andsource.

(ii) Both VDS and VGS have been set atsome positive voltage greater than 0V,establishing the drain and gate at a positivepotential with respect to the source. The

Chapter 5 FETs 36

p ppositive potential at the gate will pressurethe holes in the p-substrate along the edgeof the SiO2 layer to leave the area and enter deeper regions of the p-substrate.The result is a depletion region near theSiO2 insulating layer void of holes.

19

However, the electrons in the p-substrate (the minority carriers of the material) will beattracted to the positive gate and accumulate in the region near the surface of the SiO2layer. The SiO2 layer and its insulating qualities will prevent the negative carriers frombeing absorbed at the gate terminal.As VGS increases in magnitude, the concentration of electrons near the SiO2 surfaceincreases until eventually the induced n-type region can support a measurable flowbetween drain and source.The level of VGS that results in the significant increase in drain current is called thethreshold voltage ,VT. On specification sheets it is referred to as VGS(Th).

Since the channel is nonexistent with VGS = 0V and “enhanced” by the application of apositive gate-to-source voltage, this type of MOSFET is called an enhancement-typeMOSFET.Both depletion and enhancement type MOSFETs have enhancement-type regions butthe label was applied to the latter since it is its only mode operation.

As V is increased beyond the threshold level the density of free carriers in the

Chapter 5 FETs 37

As VGS is increased beyond the threshold level, the density of free carriers in theinduced channel will increase, resulting in an increased level of drain current. However,if we hold VGS constant and increase the level of VDS, the drain current will eventuallyreach a saturation level as occurred for the JFET and depletion type MOSFET. Theleveling off of ID is due to a pinching-off process depicted by the narrower channelat the drain end of the induced channel.

KVL to the terminal voltages of the MOSFET,we find that

If VGS is held fixed at some value such as8 V and VDS is increased from 2 to 5 V, thevoltage VDG will drop from –6 to –3 V andthe gate will become less and less positivewith respect to the drain.This reduction in gate-to-drain voltage VDGwill in turn reduce the attractive forces forfree carriers (electrons) in this region of theinduced channel, causing a reduction in the

ff ti h l idth E t ll th

Chapter 5 FETs 38

effective channel width. Eventually, thechannel will be reduced to the point ofpinched-off and a saturation condition will beestablished. Any further increase in VDS at the fixed value of VGS will not affect the saturation level of ID until breakdownconditions are encountered.

20

The drain characteristics shown below reveal that at VGS = 8V, saturation occurred at alevel of VDS = 6V. In fact, the saturation level for VDS is related to the level of appliedVGS by Obviously, for a fixed value of VT, then the higher

the level of VGS, the more the saturation levelfor VDS as shown by the locus of saturation levels.

As the levels of VGS increasedfrom VT to 8V, the resultingsaturation level for ID alsoincreased from a level of 0 to10 mA.It is quite noticeable that thespacing between the levels ofVGS increased as the magnitudeof VGS increased, resulting in

i t i d i t

Chapter 5 FETs 39

ever-increments in drain current.

For values of VGS less than the threshold level, the drain current of an enhancementtype MOSFET is 0 mA.

For levels of VGS > VT, the drain current is related to the applied gate-to-sourcevoltage by the following nonlinear relationship:

It is the squared term that results in the nonlinear relationship between ID and VGS.The term k is a constant that is a function of the construction of the device.The value of k can be determined from the following equation where ID(on) andVGS(on) are the values of each at a particular point on the characteristics of the device.

Chapter 5 FETs 40

Ex: substituting ID(on) = 10mA when VGS(on) = 8V yields

21

Substituting VGS = 4V, we find that

A general equation for ID for the characteristics shown in the previous slide results in:

At VGS = VT, the squared term is 0 and ID = 0mA.

Chapter 5 FETs 41

Example (4): How to plot the trnasfer characteristics given the levels of k and VT asincluded below for a particular MOSFET:

First, a horizontal line is drawn at ID = 0 mA from VGS = 0V to VGS = 4V.Next, a level of VGS greater than VT such as 5 V is chosen.

Finally, additional levels of VGS are chosen and the resulting levels of ID obtained.

Chapter 5 FETs 42

22

p-Channel Enhancement-Type MOSFETs

The construction of a p-channel enhancement-typeMOSFETs is exactly the reverse of n-channel type.That is , there is now an n-type substrate and p-doped regions under the drain and source connections.All the voltage polarities and the current directions arereversed. The increasing levels of current resultingreversed. The increasing levels of current resultingfrom increasing negative values of VGS.

Chapter 5 FETs 43

Symbols

The symbols try to reflect the actual construction of the device. The dashed line betweendrain and source was chosen to reflect the fact that a channel does not exist betweenthe two under no-bias conditions.It is, in fact, the only difference between the symbols for the depletion-type and enhancement-type MOSFETs.

Chapter 5 FETs 44

23

Example (4): Given; VGS(on) = 10V will giveID (on) = 3 mA. VGS(Th) = 3V. Plot the transfercharacteristics.

For

Chapter 5 FETs 45

For VGS = 8, 10, 12, and 14 V, ID will be 1.525, 3 (as defined), 4.94 and 7.38 mA,respectively.

SUMMARY

Chapter 5 FETs 46

24

Chapter 5 FETs 47