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CHAPTER 4

TRANSCEIVER DESIGN AND LAYOUT ISSUES

4.1 PERFORMANCE SUMMARY

Power management is a great challenge in wireless sensor nodes

where considerable amount of energy is consumed in the transceiver circuits.

For this design the normalized energies at 1.2V are considered based on

simulations and these are extrapolated over a range of Vdd using fundamental

analytical models. The transceivers designed in this work are implemented in

the 120nm CMOS technology. A summary of the performance of the ASK,

FSK and PSK Transceivers in transmit as well as in the receive modes are

tabulated in Table 4.1.The performance of the proposed transceivers is

compared with the existing results available in the literature.

From the table, it is seen that the ASK transceiver consumes

0.41mW in transmit mode and 2.18mW in receive mode. In the receiver chain

much of the power is consumed by the mixer. So there is greater power

consumption during the reception of the signals. FSK and PSK transceivers

consume 0.53mW and 5.21mW in transmit mode and 2.41mW, 2.18mW in

receive mode respectively.

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Hence it is clear that the proposed ASK architecture gives good

linearity and low power consumption for the low power and low data rate

WSN applications.

4.2 LAYOUT ISSUES OF TRANSCEIVER

4.2.1 Introduction

A layout is the equivalent of an engineering blueprint of the circuit.

The layout is critical to an analog circuit design, especially for RF circuits in

the GHz range. Careful floor plan and layout considerations are important. A

poor layout generates unexpected parasitic and leads to performance

degradation or circuit failures. This section describes the layout techniques of

basic elements, circuits used in the design and layout considerations for the

Transceiver circuits.

As CMOS circuits evolve to low voltage, high speed and high

complexity systems, it is well recognized that the layout could heavily

influence and limit the performance of the circuit. Crosstalk, parasitic

capacitances and substrate coupling are a few examples of such issues that

arise from the layout design. Tradeoffs are usually necessary under these

circumstances. For example, increasing the width of an interconnection metal

can reduce its parasitic resistance, but will inevitably raise its crosstalk with other

signal paths.

The layout of RF integrated circuits plays an important role in the

proper circuit functioning of a chip. The parasitic capacitances of wire for

routing of signals degrade the performance of ICs and need to be minimized

by proper layout. If the chip area is not a concern, the ground buses can be

made as wide as possible since they do not contribute to parasitic

capacitances. The width of the signal paths need to be carefully chosen for

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tradeoffs between parasitic shunt capacitance and parasitic series resistance.

In this chapter, the 120nm CMOS technology is used to present the Layout

design.

4.2.2 Layout Design Flow

After optimizing the schematic to meet the design requirements,

each circuit block is implemented to layout using Microwind. There are two

guidelines to implement the layout: one is to optimize the layout to reduce

parasitic (R, L and C) components, and the other is to improve device

matching (transistors, capacitors, resistors and inductors). When the layout of

the blocks is completed, they need to be arranged together. This is called floor

planning. Some guidelines to floor planning are: optimizing area efficiency,

isolating noisy devices and reducing parasitic effects. Extraction from the

layout finds expected and unexpected parasitic effects. Post-layout simulation

indicates that the parasitic effects have significant effects to the circuit

performance. If so, one may need to redo the floor plan and even the

individual block layout. After a successful post layout simulation, the design

can be streamed out for fabrication.

The parasitic effects such as coupling capacitance and losses related

to the integration substrate degrade the performance. These unwanted effects

are particularly important for silicon substrates. The on-chip CMOS inductor

design is very important in the RF IC design because the Q value of the

inductor dominates the losses in the LC tank thus it directly affects the

performance. One of the key factors that determine the performance of the RF

integrated circuits (RF IC's) is the availability of good quality integrated

inductors (Burghartz et al 1998).

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4.2.3 Layout of the CMOS Inductor

Figure 4.1 shows the layout of the on chip CMOS spiral inductor.

The top most layer of metals (metal-6) is used to layout the inductor because

this is the thickest metal layer with the smallest sheet resistance.

Figure 4.1 Layout of the spiral inductor

In addition, this layer is located far away from the lossy silicon

substrate, which reduces the substrate loss and provides better noise isolation.

A wide metal width helps to reduce the series resistance of the metal inductor.

However at high frequencies, the current only flows through the surface of the

metal due to skin effect. The skin depth of a conductor ‘ ’

using Equation (4.1) as,

0

1f

(4.1)

where, ‘f’ is the frequency of the signal

0’ is the permeability in free space and

Increasing the metal width correspondingly increases the silicon

area dramatically. With the increase of inductor size, the parasitic capacitance

from inductor to the substrate increases proportionally and thus lowers the

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self-resonant frequency of the inductor. To improve the magnetic coupling

between segments of an inductor, the spacing between metal segments is

often kept as minimum.

4.2.4 Layout of the Capacitor

Two different capacitors have been utilized in the design, one is the

metal-to-metal capacitor and the other is metal-insulator-metal (MIM)

capacitor shown in Figure 4.2. MIM capacitor uses an extra metal layer CTM,

which is much closer to the next metal layer and thus provides much more

capacitance per unit area than the usual metal-to-metal capacitors.

Figure 4.2 Layout of the Capacitor

4.2.5 Layout of the Resistor

All the resistors in the design are unsilicide polysilicon ones. These

resistors have relatively large resistances, low temperature coefficient and

relatively low parasitic capacitances. Figure 4.3 shows a layout of the

degeneration resistor using poly silicon.

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Figure 4.3 Layout of the Resistor

4.2.6 Layout of the MOS Transistors

The layout of the NMOS and PMOS transistors illustrated in

Figure 4.4 has a great influence on the overall performance of the design

including symmetry, noise, parasitic capacitance and gate resistance issues

especially for low noise circuit design.

Figure 4.4 Layout of NMOS and PMOS Transistor

The transistor with a large width is usually divided into a number of

small width transistors placed in parallel to reduce parasitic capacitance as

well as gate resistance. To isolate the noise, a guard ring with many substrate

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contacts is also employed. Symmetry needs to be carefully planned if

differential topology is used in the design.

4.2.7 Layout of the ASK, FSK and PSK Transmitters

For this design, the normalized energies at 1.2V are considered for

simulation using the simulation model. As the transmitter consists of a

modulator and a power amplifier, the layout is drawn for both the circuits.

The surface area of the ASK transmitter is about 41.7µm2 and for the FSK, it

is 58.3µm2. The PSK transmitter occupies an area of 265.3µm2. This is more

when compared to the other two transmitters. The Layout of the transmitters

is presented in Figures 4.5 to 4.7. For wireless sensor nodes, in order to

accommodate a large amount of circuitry in a small chip the dimension of the

devices should be made smaller.

Figure 4.5 Layout of ASK Transmitter

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Figure 4.6 Layout of FSK Transmitter

Figure 4.7 Layout of PSK Transmitter

4.2.8 Layout of the Low IF Receiver

The low IF receiver is comprised of an inductive feedback

differential mode CG LNA, a Gilbert mixer, Frequency synthesizer, Q-

enhanced fully differential BPF and a Detector. Hence the Layout of receiver

includes all the wireless components mentioned above. In order to construct

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the Layout, the front end of the receiver is first considered. Since the

proposed receiver front end consists of an inductive feedback Common Gate

LNA, layout of the LNA is considered in the next section followed by the

other components.

4.2.8.1 Layout of the Inductive Feedback CG LNA

An important aspect in the design of low noise amplifier is the

availability of high Q inductors as it plays an important role in the

determination of the noise figure of LNA. The layout of single ended and

fully differential low noise amplifiers has been carried out in 120nm CMOS process. The following points are considered while doing the layout of the LNA.

1. The thick metal layer metal- 4 has been used for realization of

on-chip inductors and routing of input and output signals due

to its low resistivity and maximum distance from the substrate

which results in low parasitic capacitance.

2. Guard rings have been placed around the inductors and

sensitive circuitry to provide effective isolation and to reduce

noise coupling. Large guard rings have been placed around

inductors for isolation.

3. The use of multiple ground pads and bond wires is strongly

recommended as ground of IC and PCB ground will not be at

the same potential due to inductance of bond wires. The effect

can be minimized by using multiple bond wires and pads

connected in parallel.

4. A fully symmetrical layout has been carried out for the fully differential LNA.

Even though there are five LNAs proposed in the research work,

inductive feedback CG LNA is suitable for the design of the low power

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transceiver since it consumes a reduced power of 0.346 . The Layout of the

proposed single ended Common Gate LNA as well as the differential mode

LNAs are shown in Figures 4.8 and 4.9.

Figure 4.8 Layout of the single ended inductive feedback Common Gate LNA

Figure 4.9 Layout of the inductive feedback differential mode Common

Gate LNA

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The width of the single ended LNA is around 335.5µm and the height is

314.3µm. It occupies an area of 0.1mm2. The width of the differential mode

LNA is 436.1µm and the height is 401.5µm. It occupies an area of around

0.2 mm2.

4.2.8.2 Layout of the proposed modified Q-Enhanced fully Differential

BPF

Figure 4.10 shows the Layout of the modified Q enhanced fully

differential Band pass filter using 120nm CMOS technology. The height of

the Layout is only 415 9

occupies an area of 32808.7µm2.

Figure 4.10 Layout of the modified Q enhanced fully differential BPF

Using the Layout of the wireless components, the Layout of the

Low IF receiver is constructed. It is incorporated in the Layout of the

transceiver.

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4.2.9 Layout of ASK, FSK and PSK Transceiver

In this section, Layout of the transceivers such as ASK, FSK and

PSK transceivers is drawn.

Figure 4.11 Layout of the ASK Transceiver

Figure 4.11 shows the Layout of the proposed low power and low

data rate ASK Transceiver. The width of the Layout is 763.41µm and the

height is 662.79µm. Its surface area is around 0.5mm2. Layouts of FSK and

PSK Transceivers are depicted in Figures 4.12 and 4.13 respectively. They

occupy an area of 0.52mm2 and 0.55mm2 using 120nm CMOS technology.

Figure 4.12 Layout of FSK Transceiver

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Figure 4.13 Layout of PSK Transceiver

From the Layouts shown in the above Figures, it is seen that the

low power ASK Transceiver occupies less area when compared to the FSK

and PSK layouts reported in the research work. The difference in layout area

reflects the area occupied by the modulator and demodulator circuits of the

proposed Transceivers.