Chapter 4

Processor Technology and Architecture

Chapter goals Describe CPU instruction and execution cycles Explain how primitive CPU instructions are combined

to form complex processing operations Describe the key CPU design features, including

instruction format, word size, and clock rate Describe the function of general-purpose and special-

purpose registers Compare and contrast CISC and RISC CPUs Describe the principles and limitations of

semiconductor-based microprocessors

Model of Central Processing Unit

How the CPU works CPU is a complex electronic device

that carries out instructions Called the “brains” of a computer Is a combination of parts that

through a carefully coordinated process execute code

CPU partsControl Unit – moves data and instructions

between main memory and registers

Arithmetic and Logic Unit – performs all computation and comparison operations

Registers – fixed size high speed storage locations that hold inputs and outputs for the ALU

How does CPU execute code? CPU can only execute machine code Machine code is a predetermined set

(defined by hardware manufacturer) of instructions CPU can execute

Machine code is in binary format (0s and 1s)

Process of executing code is called the “Fetch Execute Cycle”

The Fetch Execute Cycle Program counter (pc) points to the next

instruction to be execute Instruction is loaded into instruction

register and program counter is incremented

Instruction is de-coded or separated into OPCODE and addresses

Instruction is executed and results are stored if required

CPU Fetch Execute Cycle

CPU Instructions Instruction is a single command a

CPU is capable of carrying out Instruction is formatted as a bit

string, i.e. a sequence of 0s and 1s Opcode – unique binary number

representing operation to be performed Operand(s) – reference or pointer to

data needed for operation

Instruction format

Opcodes and operands Opcodes – unique binary number

representing an operation to be carried out

Operand(s) – reference(s) to location of data needed for operation Register # Memory address Secondary storage or I/O device

How is instruction executed? Instruction directs CPU to route data

through a built-in set of circuitry (i.e. a series of logic gates) designed to carry out the desired function

Circuitry takes input signals and depending on sequence and number of logic gates produces the desired output signal

Output signal is stored in a register Then may be stored in memory, secondary

storage, or used by a subsequent instruction

Instructions Some instructions are just handled

by the control unit Moving or copying data Halting or restarting the CPU

Other instructions require coordination with the ALU Computation Logic (comparisons)

Instruction set The collection of all possible

instructions CPU can execute is called the “instruction set”

Predetermined by hardware manufacturer

Vary greatly from machine to machine (even with the same manufacturer)

Instruction set cont. Since instruction sets vary so

much, we will describe what is generally in most machines

Specific “machine code” we will learn will be for the machine simulator presentation

General instruction categories Data movement (really a copy

command, original bit pattern is unchanged) Load – copies data from memory into

a register Store – copies data from a register

into memory

Data Transformation

Logical shift

Using logical shift Computers often use Boolean

(true false) values to control processes

These values (called flags) can be stored in a single bit

Therefore, a 32 bit register can contain 32 individual flags to identify 32 separate conditions

Program status word (PSW) See p. 133 in text PSW used by CPU to store status

information for currently executing instruction Store the result of a comparison

(equal or not equal, T or F) Indicate overflow and underflow

conditions

How a PSW is used http://www.heyrick.co.uk

/assembler/psr.html This is an example of how the PSW

is used for a processor manufactured by ARM, a processor manufacturer in Australia

http://www.arm.com/

Arithmetic shift

Sequence control Default sequence (order) of program

instructions is one after another Can override through BRANCH or JUMP

unconditional – new address of next instruction is loaded into PC (JUMP)

conditional – new address of instruction is loaded depending on result of some comparison (BRC & BRP in simple machine)

HALT – ends execution

Sequence control cont. Allows loops (iteration)

for (int 1=0; i <10; i++) cout << “\nHello”;

Allows decision statements if (speed >= 65) cout << “Speeding ticket”;else cout << “Legal speed”;

Variations in instruction format Formats can vary as to opcode size meaning of opcode values Number of operands Data types used as operands Length and coding format of each

operand

Reduced Instruction Set Computing Analysis of actual software found

that certain instructions made up the vast majority of machine code

Many instructions used very infrequently

CPU design that limited instruction set found to be much faster

RISC vs. CISC Pentium (RISC) vs. 486 (CISC) CISC bloated instruction set slowed

down execution time CISC CPU larger and slower than

necessary

Clock rate System clock is a timing device

that generates timing pulses or signals that are transmitted devices throughout the computer

Frequency or rate (clock rate) is measured in hertz (Hz) and megahertz (MHz)

Clock rate cont. CPU uses timing of clock to trigger

its actions (i.e. fetch, execute, store)

Clock is also used by other devices like secondary storage

CPU must often wait for slower devices (secondary storage, RAM) Wait state – cycle where CPU is idle

waiting for other devices

Measuring CPU speed Clock rate – measured in mHtz MIPS – millions of instructions per

second (assumed to be instructions involving integer operations)

MFLOPS – millions of floating point operations per second

CPU instructions can vary greatly as to length of time for execution

CPU registers General purpose

Collection of registers that can be used to store intermediate input and output of ALU operations

Example34 + 31 + 44first 34 is added to 31 and placed in a register, then 44 is added to the register

Special purpose registers Several registers in CPU are set

aside for specific purposes: Instruction register – holds the

currently executing instruction Program counter (PC) – points to the

next instruction to be executed Program status word (PSW) – set of

flags (bits) indicating certain conditions

Word size Unit of data that contains a fixed

number of bits Determines the amount of data

CPU can process at one time Corresponds to size of general

purpose registers

Optimal word size Should be same size as system bus

If bus is smaller every load and store operation requires multiple transfers

Word size should correspond to size of data used in the machine Int float data types are 4 bytes (32

bits) Double is 8 bytes (64 bits)

Current word sizes Most desktop machines are 32 bit word

size Doubling word size to 64 increases CPU

components by 2.5 to 3 times Larger word increases CPU fabrication cost Since the rest of the machine operates at

32 bit (system bus and secondary storage) this larger word size is not yet an advantage

The physical CPU

Gate design for addition

Chapter summary The CPU continuously alternates between the

instruction, or fetch cycle and execution cycle

Primitive CPU instructions can be classified into three types: Data movement Data transformation Sequence control

Summary cont. An instruction formation is a template

describing the op code position and the length and the position, type and length of each operand

The CPU clock rate is the number of instruction and execution cycles potentially available in a fixed time interval

Summary cont. CPU registers are of two types:

General purpose Special purpose

Word size is the number of bits that a CPU can process simultaneously

CPUs are electrical devices implemented as silicon-based microprocessors