Chapter 21 Bias in Transistor Amplifiers - Welcome to MATCecampus.matc.edu/.../electronics/662_112_lectures/ch21biasSp09m.pdf · Chapter 21 Bias in Transistor Amplifiers* by Robert

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© 2008 Strangeway, Lokken, Petersen, and Gassert page 1

Chapter 21 Bias in Transistor Amplifiers*

by Robert Strangeway, Richard Lokken, Owe Petersen, and John Gassert

21.1 The Need for Bias in Transistor Amplifiers ....................................................................2

21.2 Bipolar Junction Transistor (BJT) Amplifiers................................................................3

21.2.1 BJT Linear Semiconductor Principles Review ........................................................3

21.2.2 Common Emitter Amplifiers: Bias Analysis ..........................................................5

21.3 Field Effect Transistor (FET) Amplifiers ......................................................................12

21.3.1 FET Linear Semiconductor Principles Review......................................................12

21.3.2 Common Source Amplifiers: Bias Analysis .........................................................15

21.4 Class Notes ........................................................................................................................19

21.5 Homework Problems .......................................................................................................33

Note: The order of coverage of sections 21.2 and 21.3, and the corresponding sub-sections of

class notes within section 21.4, may be swapped—they are independent sections.

Outcomes: As a result of studying this chapter and working the homework problems, the

student should be able to:

Explain general transistor amplifier biasing concepts and analysis approaches.

Develop and utilize the bias equations for common emitter/source transistor amplifiers.

* This chapter may be copied and distributed during the 2008-9 academic year to students in the

Electrical/Electronics Technology and Engineering Technology programs at College of Lake County, Fox Valley

Technical College, Gateway Technical College, Madison Area Technical College, Milwaukee Area Technical

College, Milwaukee School of Engineering, Northeast Wisconsin Technical College, Waukesha County Technical

College, and Western Technical College, all in the states of Wisconsin or Illinois. Any other reproduction or

distribution is prohibited without the express written consent of one of the first or second named authors.

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21.1 THE NEED FOR BIAS IN TRANSISTOR AMPLIFIERS

Have you ever increased or decreased the volume on a CD player or radio? If a resistor

network is present, voltage division can be used to decrease the volume. How is an increase in

volume accomplished? A circuit that increases the power of the AC signal is often required. A

transformer could be used to increase the peak-to-peak voltage or current amplitude of a signal.

However, a transformer does not add power, it only transforms voltage and current levels. We

need a circuit that can increase the power of the signal. This circuit could be used to increase the

voltage magnitude, the current magnitude, or both. Such an electronic circuit is named an

amplifier, and the process of increasing the magnitude of a signal is called amplification. The

generic schematic symbol of an amplifier is shown in Figure 21.1. The triangle represents the

amplifier circuit. Notice that an amplifier has two connections, an input and an output, as do

transformers and filters. The input is on the left side of the triangle (the vertical line) and the

output is on the right side (the horizontal point of the triangle). The peak phasors of the input

and output are indicated, with the understanding that the input and output are AC sinusoidal

steady-state signals in the circuit analysis.

+

_

+

_iV

oV

Figure 21.1 Schematic symbol for an amplifier

Where does the energy come from to amplify the input signal? It comes from the DC

voltage and current applied to the electronic circuit. DC energy is converted into AC energy in

an amplifier. The DC voltage and current are called DC bias when used in this context. Hence,

most electronic amplifiers require DC bias in order to amplify. In fact, the amplifier can be

viewed as a component that has a DC bias input and amplifies an AC input signal, as illustrated

in Figure 21.2. Often, the DC bias is assumed and not shown with the schematic symbol of an

amplifier.

AC inputAC output

DC input

Figure 21.2 Overall viewpoint of amplification

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What devices can be used in amplifier circuits? The bipolar junction transistor (BJT) and

field effect transistor (FET) are two of the most common discrete electronic devices utilized in

amplifiers. Both transistors will be utilized in this chapter and subsequent chapters because they

are probably the two most important active devices that are utilized in amplifiers. The key

aspect in these chapters, however, is not the particular device, but how the device is analyzed

within amplifier circuits and, even more importantly, the underlying reasoning.

One of the functions of an amplifier circuit is to establish appropriate DC voltages and

currents at the active device terminals, that is, to establish DC bias. Bias sets the DC operating

point of the transistor in a region of its operating characteristics that is suitable for amplification

(to be discussed in more detail in each of the following two sections). This function is another

reason why DC bias is necessary in amplifier circuits.

There are many different basic amplifier circuits and even more particular variations of

the basic circuits. The purpose here is not to investigate every amplifier circuit configuration—

there are far too many to cover in one or two courses. Instead, the purpose is to examine some

important configurations so that you understand amplifier circuits, you can predict amplifier

circuit performance, and you have a conceptual foundation to build upon when you need to

investigate amplifiers in whatever specialty areas that you may encounter.

21.2 BIPOLAR JUNCTION TRANSISTOR (BJT) AMPLIFIERS

The bias of amplifier circuits that utilize the bipolar junction transistor (BJT) is covered

in this section. The linear semiconductor principles of the BJT are reviewed in section 21.2.1.

The developments of the dc bias equations are covered in section 21.2.2.

21.2.1 BJT Linear Semiconductor Principles Review

The npn transistor is used to review the linear semiconductor principles of a bipolar

junction transistor. The corresponding description for the pnp transistor is left as a homework

exercise. The term ―linear‖ indicates that the transistor is biased such that a change of the base

current results in a proportional change in the collector current. The transistor is not being used

as a switch, where the bias states results in either saturation or cutoff. (If the discussion in this

paragraph is not clear to you, please review your previous semiconductor class materials.)

The following semiconductor discussion uses a npn transistor in the common emitter

(CE) configuration, as shown in Figure 21.3. It shows the block diagram of a npn transistor and

the corresponding bias supplies. The base-emitter junction is forward biased and the base-

collector junction is reverse biased. Thus, the depletion region of the base-emitter junction is

relatively narrow and the depletion region of the base-collector junction is relatively wider. How

do we know that the base-collector region is reverse-biased? Apply KVL through the emitter-

base-collector and collector voltage supply path. The base-emitter voltage, VBE is approximately

0.7 V for a npn silicon transistor. The collector supply is at least a few volts; hence, the base-

collector junction is reverse biased.

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C

E

BIB

IC

IE

n

p

n

B

C

E

Depletion

Regions

VCC

VBB

Figure 21.3 npn BJT diagram

In the following discussion, a current is a conventional current unless specifically labeled

an ―electron current.‖ The base region is relatively thin. The thinness of the base region has a

profound effect on the circuit operation. If the base-emitter voltage is increased (more forward

biased), the base current increases, and more current flows in the base-emitter circuit.

Correspondingly, the base-emitter junction depletion width (potential barrier) is decreased.

However, there are two DC bias voltage supplies. The base-emitter voltage supply provides the

base-emitter current and the forward bias to that junction. The collector voltage supply provides

a larger current that enters the collector region at the collector contact. The negative side of the

collector voltage supply strongly attracts most of these charges from the collector region straight

through the thin base region and into the emitter region, where the current path is completed

back through the collector voltage supply. This action occurs despite the reverse bias on the

collector-base junction because of the thinness of the base region.

The degree to which the base is forward biased directly influences the current level from

the collector supply that can transverse across the base into the emitter region. A larger forward

bias voltage produces a smaller depletion region of the base-emitter junction. Thus, more current

from the positive side of the collector supply flows into the collector, across the base into the

emitter region, and back to the negative side of the collector supply. The argument is vice-versa

for less base-emitter forward bias. Hence, the base current, which is proportional to the forward

bias voltage, effectively controls the collector current, and current amplification results. This

amplification is expressed as a current ratio with the Greek letter symbol beta (β):

CDC

B

I

I (21.1)

where the DC subscript indicates that this is the current ratio of DC currents. It is usually quite

large, in the range of 100 to 300, so significant amplification occurs. Base currents are often on

the order of 10’s of μA and the collector current is often on the order of mA for small-signal BJT

amplifiers.

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Is the emitter current equal to the collector current? Almost. Apply KCL to the BJT.

The emitter current consists of the collector current plus the base current. The base current is

usually much smaller than the collector current by a factor on the order of 100 to 300, as stated

previously; hence, the emitter and collector currents are effectively equal in most CE BJT

amplifiers. β will be used extensively in DC bias and AC gain calculations in the next section.

21.2.2 Common Emitter Amplifiers: Bias Analysis

Bias Analysis

The discussion in the previous section has established that the base-emitter junction must

be forward biased and the base-collector junction must be reverse biased. How are these DC

bias conditions established? One could use two separate DC voltage supplies, but this is

expensive. Alternatively, resistors could be used in various configurations to supply the bias

conditions from one DC voltage supply. Different bias configurations have different properties,

such as stability vs. temperature changes, which are covered in detail in design references. Here,

we consider DC bias analysis: given a BJT amplifier circuit, predict the bias conditions, usually

the base current, the collector current, and the collector-emitter voltage. Then one can insure that

the Q-point is in the active region of the BJT characteristic curves. For example, examine the

CE characteristic curves for the 2N3904 transistor illustrated in Figure 21.4. Recall that the

cutoff region is where both the base and collector currents are effectively zero. Both junctions

are reversed-biased and the BJT is off. The saturation region is at low collector-emitter voltage

values such that the depletion region of the base-collector region is forward biased and,

consequently, the collector current is relatively high. The BJT is fully on. These two regions are

appropriate for operation of the BJT as a switch, but not for linear amplification. The bias needs

to establish a Q-point somewhere in the ―middle‖ of the characteristic curves, where the collector

current is directly proportional to the base current. This occurs when the base-emitter junction is

forward biased and the base-collector junction is reverse biased (the active region). For example,

the Q-point of approximately IB = 40 μA, IC = 7 mA, and VCE = 5 V would be located in the

active region for this transistor. What are the acceptable ranges of collector current and

collector–emitter voltage for the active region? Don’t forget maximum power dissipation too.

max

max

max

sat

sat

CE C C

CE CE CE

CE C C

I I I

V V V

V I P

(21.2)

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BJT I C versus V CE

0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.02

0.0 2.0 4.0 6.0 8.0 10.0

V CE (Volts)

I C (

A)

IB=100uA

IB=80uA

IB=60uA

IB=40uA

IB=20uA

IB = 0uA

Figure 21.4 Plot of the IC versus VCE at various values of IB for a 2N3904 transistor

(The characteristic curve values were calculated with PSpice®.)

Example 21.2.1 Locate a data sheet for the 2N3904 transistor. Determine the acceptable

ranges of collector current, collector–emitter voltage, and maximum

collector power dissipation.

The 2N3904 data sheet is located on the web (for example, at

http://www.rohm.com/products/databook/tr/pdf/umt3904.pdf ). The

following ranges are identified from the data sheet:

max

50 nA 200 mA

0.3 V 40 V

625 mW

C

CE

C

I

V

P

General DC bias analysis strategy for BJT amplifiers:

Before considering an example, how should one approach a bias analysis of a BJT

amplifier? Apply KVL and/or KCL appropriately, relate the base and collector currents using β,

and solve for the desired bias quantities. Generally, KVL is applied to the base circuit in order to

solve for the base current, and then applied to the collector circuit in order to solve for the

collector-emitter voltage. You should be able to apply this general strategy to a variety of bias

configurations without the need to memorize formulas or consult a reference table.

http://www.rohm.com/products/databook/tr/pdf/umt3904.pdf

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Example 21.2.2 For the emitter-stabilized bias circuit shown in Figure 21.5,

a) develop the bias equations and solve for IB, IC, IE, and VCE.

b) determine these bias levels given VCC = 12 V, β = 100, VBE = 0.7 V,

RB = 200 kΩ, RE = 300 Ω, and RC = 900 Ω.

VCC

Cgen

RB

RC

CL

RE C

E

AC

input

signal

AC

output

signal

E

BC

IC

IE

IB

Figure 21.5 CE amplifier with voltage divider bias

Given: The CE amplifier circuit in Figure 21.5

VCC = 12 V β = 100 VBE = 0.7 V

RB = 200 kΩ RE = 300 Ω RC = 900 Ω

Desired: a) development of the bias equations to solve for IB, IC, IE, and VCE

b) the actual values of IB, IC, IE, and VCE for the circuit in Figure 21.5

Strategy: All capacitors appear as open circuits at DC. Apply KVL around paths

and KCL at nodes that include the variables of interest (IB, IC, IE, and VCE)

and solve for those variables.

b) Insert component values to determine IB, IC, IE, and VCE.

Solution: a) Apply KVL to the base side of the amplifier circuit:

0CC B B BE E EV I R V I R (21.3)

Arbitrarily, let’s try to solve for IB first (one needs to start somewhere).

Apply KCL to the transistor to relate IE to IB:

0B C EI I I (21.4)

C BI I (21.5)

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1E B B BI I I I (21.6)

1 0CC B B BE B EV I R V I R (21.7)

1 1CC BE B B B E B B EV V I R I R I R R (21.8)

1

CC BEB

B E

V VI

R R

(21.9)

Note that three of the desired quantities, IB, IC, IE, have been determined

because IB is determined purely in terms of known circuit quantities and

IC and IE are determined from known circuit quantities and IB in Equations

(21.5) and (21.6).

A second application of KVL, to the collector side of the amplifier circuit,

is required to determine VCE:

0CC C C CE E EV I R V I R (21.10)

1CE CC C C E E CC B C B EV V I R I R V I R I R (21.11)

1CE CC C E BV V R R I (21.12)

As with IC and IE, VCE has been determined in terms of known circuit

quantities and IB, which has previously been determined in terms of

known circuit quantities. Hence, the four bias equations applicable to this

CE amplifier configuration are

1

CC BEB

B E

V VI

R R

(21.13)

C BI I (21.14)

1E BI I (21.15)


b) Insert the circuit values and calculate IB, IC, IE, and VCE:

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12 0.749.1 A

1 200k 101 300

CC BEB

B E

V VI

R R

100 49.1 4.91mAC BI I

1 101 49.1 4.96 mAE BI I

1 12 100 900 101 300 49.1 6.09 VCE CC C E BV V R R I

Notice that approximately half of the supply voltage is used to establish

the Q-point value of VCE.

Example 21.2.3 For the voltage divider bias BJT amplifier shown in Figure 21.6,


b) determine these bias levels given VCC = 5 V, β = 100, VBE = 0.7 V, R1 =

60 kΩ, R2 = 30 kΩ, RE = 100 Ω, and RC = 600 Ω.

VCC

Cgen

R1

RC

CL

RE

R2

CE

AC

input

signal

AC

output

signal

BC

EIB

IC

IE

IR1

IR2

Figure 21.6 CE amplifier with voltage divider bias and an emitter resistor

Given: The CE amplifier circuit in Figure 21.6

VCC = 5 V β = 100 VBE = 0.7 V

R1 = 60 kΩ R2 = 30 kΩ RE = 100 Ω RC = 600 Ω

Desired: a) development of the bias equations to solve for IB, IC, IE, and VCE


_____________________________________________________________________________________________________________________


Strategy: a) Determine the Thévenin equivalent circuit of the supply voltage, R1 and

R2 as seen from the base. Apply KVL around paths and KCL at nodes

that include the variables of interest (IB, IC, IE, and VCE) and solve for

those variables.


Solution: a) Determine the DC Thévenin equivalent circuit as seen by the base at

terminals a – b in Figure 21.7.

VCC

Cgen

R1

RC

CL

RE

R2

CE

VCC

a

b

Thev.

R1

VCC

R2

Thev.

a

b

Figure 21.7 Determination of the DC Thévenin equivalent circuit for the base bias

1 2 2

Th Th

1 2 1 2

andCCR R V R

R VR R R R

(21.17)

The Thévenin equivalent circuit replaces the supply voltage, R1 and R2 on

the base side of the circuit, as shown in Figure 21.8.

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VCC

RC

RE

RTh

VTh

IB

IC

IE

Figure 21.8 Base side of the amplifier circuit with the Thévenin equivalent circuit inserted

Apply KVL to the base side of the amplifier circuit:

Th Th 0B BE E EV I R V I R (21.18)

Solve for IB first as in the previous example:

1E BI I (21.19)

Th Th 1 0B BE B EV I R V I R (21.20)

Th Th Th1 1BE B B E B EV V I R I R I R R (21.21)

Th

Th 1

BEB

E

V VI

R R

(21.22)

C BI I (21.23)

A second application of KVL, to the collector side of the amplifier circuit,

is required to determine VCE (identical to the previous example):




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Hence, the four bias equations applicable to this CE amplifier

configuration are

Th

Th 1

BEB

E

V VI

R R

(21.27)

C BI I (21.28)

1E BI I (21.29)


b) Insert the circuit values and calculate RTh, VTh, IB, IC, IE, and VCE:

1 2

Th

1 2

30k 60k20 k

30k 60k

R RR

R R

2

Th

1 2

5 30k1.6667 V

30k 60k

CCV RV

R R

5Th

Th

1.6667 0.73.2116 10 32.1 A

1 20k 101 100

BEB

E

V VI

R R

100 32.116 3.21mAC BI I

1 101 3.2116 3.24 mAE BI I

1 5 100 600 101 100 3.2116 2.75 VCE CC C E BV V R R I

Notice that approximately half of the supply voltage is used to establish

the Q-point value of VCE.

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21.3 FIELD EFFECT TRANSISTOR (FET) AMPLIFIERS

21.3.1 FET Linear Semiconductor Principles Review

21.3.2 Common Source Amplifiers: Bias Analysis

The bias of amplifier circuits that utilize the field effect transistor (FET) is covered in this

section. The linear semiconductor principles of FETs are briefly reviewed in section 21.3.1.

The developments of the DC self-bias equations are covered in section 21.3.2.


The n-channel junction field effect transistor is used to review the linear semiconductor

principles of FETs. The corresponding description for the p-channel FET is left as a homework

exercise. The term ―linear‖ indicates that the transistor is biased such that a small change of the

gate-source voltage results in a proportional change in the drain current. The transistor is not

being used as a switch, where the bias state results in either saturation or cutoff. (If the

discussion in this paragraph is not clear to you, please review your previous semiconductor class

materials.)

The following semiconductor discussion uses an n-channel field effect transistor in the

common source (CS) configuration, as shown in Figure 21.9. The FET consists of a channel of

n-doped semiconductor material. The terminal at one end is called the source and the terminal at

the other end is called the drain. If a voltage source were connected across these terminals, a

current would flow. The amount of current would depend on the applied voltage and the

resistance of the semiconductor material. A third terminal, the gate, is connected to the FET

either by p-doped semiconductor material (the junction FET, shortened to JFET), shown in

Figure 21.9, or by a terminal that is separated from the channel by a thin insulation layer (the

metal-oxide-semiconductor FET, shortened to MOSFET). The analysis approaches are quite

similar, often identical. Again, the purpose here is to establish the methods of and reasons

behind the analysis approaches, not a multitude of individual cases. One can easily perform the

analysis with device and circuit variations once the fundamental approaches are learned.

D

S

G

ID

IS

n

pG

D

S

Depletion

Region

VDS

VGS

Figure 21.9 n-channel FET diagram

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The bias establishes a reverse-bias of the junction between the gate and the channel. The

depletion region extends into the channel and limits the current flow because less of the channel

is available for conducting current. Note that VGS establishes a reverse bias between the gate and

the source. However, the combination of VGS and VDS creates an even larger reverse bias

between the gate and the drain. If the gate-source voltage were zero volts (a short), increasing

VDS increases current in the channel by Ohm’s law. However, increasing VDS also increases the

depletion region and decreases the current in the channel. The condition where these two

effects balance is called pinchoff, and results in the current leveling off in the characteristic

curves (see the top curve in Figure 21.10). The value of VDS at this point is called the pinchoff

voltage, VP, and the current remains relatively constant despite further increases in VDS.

Amplification is possible by establishing a non-zero gate-to-source reverse-bias voltage.

This voltage further increases the reverse bias between the gate and the channel, and the current

levels off at a lower level relative to a zero gate-to-source voltage (see Figure 21.10). In fact, if

VGS is increased to the value of VDS that causes pinchoff, the channel current is essentially zero

(explained below). With VGS somewhere between zero and pinchoff, a superposed AC voltage

will alternately increase and decrease the drain current, which can result in a larger signal at the

output, that is, amplification.

0.00E+00

2.00E-03

4.00E-03

6.00E-03

8.00E-03

1.00E-02

1.20E-02

1.40E-02

1.60E-02

1.80E-02

2.00E-02

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00

I D(A

)

VDS (Volts)

FET ID versus VDS

Vgs = 0

Vgs = - 0.25 V

Vgs = - 0.50 V

Vgs = - 0.75 V

Vgs = - 1.00 V

Vgs = - 1.25 V

Figure 21.10 Plot of ID versus VDS at various values of Vgs for a 2N4394 JFET transistor

(The characteristic curve values were calculated using PSpice®.)

The pinchoff voltage, VP, requires more explanation. It has already been established that

VP is the value of VDS where the channel current levels off when VGS = 0. But both VDS and VGS

contribute to the reverse bias between the gate and the channel when both voltages are non-zero.

As VGS increases (becomes more negative for an n-channel FET, or more positive for a p-channel

_____________________________________________________________________________________________________________________


FET), the pinchoff condition is reached at a lower level of VDS. The channel current must level

off at a lower point due to the lower level of VDS and Ohm’s law. When VGS equals VP, the

channel current would once again level off. However, it would ideally level off at zero VDS,

which would mean zero channel current. Hence, when VGS reaches the pinchoff voltage, the

channel is cut off (zero current). [This explanation is a significantly simplified version of the

semiconductor theory behind the pinchoff and cutoff effects.]

The relationship between the gate-source voltage, VGS , and the drain current, ID , is not an

exact direct proportion due to the manner in which the depletion region in the channel increases

as VGS is increased (the gate-channel junction reverse bias increases). The relationship is

obtained from semiconductor physics and is known as Shockley’s equation:

2

1 GSD DSS

P

VI I

V

(21.151)

where IDSS is the drain current above pinchoff when VGS = 0, and VP is the pinchoff voltage.

Again, the pinchoff voltage is basically the drain-source voltage (VDS) where the drain current

levels off as VDS increases on the plot of the drain current vs. drain-source voltage characteristic

curves. The pinchoff voltage is also known as the gate-to-source cutoff voltage, VGS(cutoff) or VGS(off), because the pinchoff voltage is also the gate-to-source voltage at which the drain current

will be zero. For example, the pinchoff voltage is approximately -1.3 V for the 2N4394 JFET, as

seen on the drain current vs. drain-source voltage characteristic curves plot shown in Figure

21.10. Note that the pinchoff voltage is used in two respects: one in terms of drain-source

voltage where ID levels off and one in terms of gate-source cutoff voltage.


Bias Analysis

The discussion in the previous section has established that the gate-channel junction must

be reverse-biased. How are these DC bias conditions established? One could use two separate

DC voltage supplies, but this is expensive. Alternatively, resistors could be used in various

configurations to supply fixed bias conditions from one DC voltage supply. However, the large

variation in the specifications of typical batches of FETs makes the fixed bias approach

unsuitable. The fixed bias approach results in large variations of the Q-point due to the variation

in the specifications of FETs; thus, it is generally unsuitable for FET bias circuits.

A bias configuration exists that ―adjusts itself‖ as the specifications of FETs varies. It is

called the self-bias configuration, and it is illustrated in Figure 21.11. How does this

configuration operate to compensate for the variation in FET specifications? Note that the

voltage across RS is directly proportional to the drain current. The gate current is zero due to the

reverse bias of the gate-channel junction. Hence, by KVL:

_____________________________________________________________________________________________________________________


0S

S

GS R

GS R

GS D S

V V

V V

V I R

(21.152)

Thus, as the IDSS specification increases from FET-to-FET, the gate-source voltage will also

increase, which pulls the Q-point down in terms of drain current (you might wish to sketch this

action on a load line that is plotted on a set of drain current vs. drain-source voltage characteristic

curves). Hence, ID and VDS remain relatively constant, especially as compared to a fixed-biased

configuration. In the following discussion, the self-bias circuit that is illustrated in Figure 21.11

is analyzed. A voltage divider self-bias configuration is left as homework exercises.

RG

RD

Cgen

CL

VDD

GD

S

VGS

RS C

SiVoV R

L

oZiZ

Rgen

genV

Figure 21.11 Self-bias FET circuit

Before considering an example, how should one approach a bias analysis? There are

generally two approaches, the load-line and the Shockley’s equation approaches, but the load-

line approach is really the graphical implementation of Shockley’s equation. We will use

Shockley’s equation. Solve Shockley’s equation for ID:

2

1 GSD DSS

P

VI I

V

(21.153)

GS D SV I R (21.154)

_____________________________________________________________________________________________________________________


2 2

1 1D S D SD DSS DSS

P P

I R I RI I I

V V

(21.155)

2

1 2 D S D SD DSS

P P

I R I RI I

V V

(21.156)

2 2 2 2 2 2 22 2D P DSS P D S P D S P DSS D S P DSS D S DSSI V I V I R V I R V I I R V I I R I (21.157)

2 2 2 22 0D S DSS D S P DSS D P P DSSI R I I R V I I V V I (21.158)

2 2 2 22 0D S DSS D S P DSS P P DSSI R I I R V I V V I (21.159)

Use the quadratic equation to solve for ID:

2 2 22S DSS S P DSS P P DSSA R I B R V I V C V I (21.160)

2 4

2D

B B ACI

A

(21.161)

Recall that the quadratic equation produces two solutions due to the ―±‖ in the result. Solutions

to reject are:

a complex number solution

ID greater than IDSS (explain why)

|VGS| = ID RS greater than VP (explain why)

transconductance gm greater than gmo (these quantities are covered in the AC discussion)

However, it can appear that both solutions are viable. The graphical solution should be plotted to

determine the proper solution in these cases.

The remainder of the bias solution is straightforward: VGS = -ID RS. Then apply KVL to

the drain circuit to determine VDS.

Another method that you may have heard of to determine the Q-point in FET amplifiers

is a graphical approach that utilizes the transfer characteristic curve. The transfer characteristic

is a plot of ID vs. VGS. It is often given in FET specification sheets. In this technique, a load line

is drawn that represents VGS = -ID RS. The Q-point is where the load line intersects with the

transfer characteristic curve. This technique is basically the graphical solution to Shockley’s

equation, and was useful when calculators and computers were primitive. The calculations are

accomplished easily with modern calculators or computer software per Equations (21.160) and

(21.161), and this technique will be utilized in this chapter. The next example illustrates the

technique.

_____________________________________________________________________________________________________________________


Example 21.3.1 For the self bias FET circuit shown in Figure 21.11 and component values

given below, determine the bias levels. [Note: the transconductance

solution will be utilized in a later chapter.]

gm2 2.538 103

gm1 8.598 103

gmo 3.6 103

gm2 gmo 1VGS2

VP

gm1 gmo 1VGS1

VP

gmo 2IDSS

VP

transconductance:

VGS2 1.476VGS2 ID2 RS

VDS2 9.053VDS2 VDD ID2 RD ID2 RS

ID2 4.472 103

ID2B B

24 A C

2 A



cri terion: reject a solution i f:

1) I-D is greater than I-DSS

2) V-GS is greater than V-P

3) g-m is greater than g-mo

ID1 0.051ID1B B

24 A C

2 A

C VP2

IDSSB 2 IDSS RS VP VP2

A RS2

IDSS

RD 1000VDD 15RS 330VP 5IDSS 0.009

Note that the first solution results in a drain current greater than IDSS. Thus, the second

solution is the valid self bias solution for this example.

____________________________________________________________________________

You should also check that the Q-point is in the active region of the characteristic curves and/or

in the specified operational bias range per the specification sheet of the particular FET being

used.

_____________________________________________________________________________________________________________________


21.4 CLASS NOTES

21.1 THE NEED FOR BIAS IN TRANSISTOR AMPLIFIERS

What is amplification?

+

_

+

_iV

oV

Figure 21.1 Schematic symbol for an amplifier

Where does the energy come from to perform this operation on the signal?

AC inputAC output

DC input

Figure 21.2 Overall viewpoint of amplification

What are two common active devices that are used in amplifier circuits?

Is the purpose here to investigate every amplifier circuit configuration? Why or why not?

What are the two main reasons that DC bias is required in amplifier circuits?

_____________________________________________________________________________________________________________________


21.2 BIPOLAR JUNCTION TRANSISTOR (BJT) AMPLIFIERS




What is the typical base-emitter voltage VBE for a npn silicon transistor?__________________

Is the base-collector junction forward- or reverse-biased? Why, based on the circuit in Fig. 21.3?

C

E

BIB

IC

IE

n

p

n

B

C

E

Depletion

Regions

VCC

VBB

Figure 21.3 npn BJT diagram

How does current cross reverse-biased collector-base junction?

How does the increased base-emitter voltage (more forward bias) increase the collector current?

_____________________________________________________________________________________________________________________


What is the following current ratio represented by the Greek letter symbol beta (β)?

CDC

B

I

I (21.162)

What are some typical values for β, IB and IC?

How does the magnitude of the emitter current compare to the collector current? Why?


Bias Analysis

Identify the following regions in Figure 21.4: cutoff region, saturation region, and active region

0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.02

0.0 2.0 4.0 6.0 8.0 10.0

I C(A

)

VCE (Volts)

BJT IC versus VCE

IB=100uA

IB=80uA

IB=60uA

IB=40uA

IB=20uA

IB = 0uA

Figure 21.4 Plot of the IC versus VCE at various values of IB for a 2N3904 transistor

(The characteristic curve values were calculated with PSpice®.)

_____________________________________________________________________________________________________________________


What do the following ranges of collector current and collector–emitter voltage represent?

max

max

max

sat

sat

CE C C

CE CE CE

CE C C

I I I

V V V

V I P

(21.163)

What is the general strategy to determine the bias point of a BJT amplifier?

Example 21.2.2 For the emitter-stabilized bias circuit shown in Figure 21.5,



RB = 200 kΩ, RE = 300 Ω, and RC = 900 Ω.

VCC

Cgen

RB

RC

CL

RE C

E

AC

input

signal

AC

output

signal

E

BC

IC

IE

IB

Figure 21.5 CE amplifier with voltage divider bias

__________: The CE amplifier circuit in Figure 21.5

VCC = 12 V β = 100 VBE = 0.7 V

RB = 200 kΩ RE = 300 Ω RC = 900 Ω

__________: a) development of the bias equations to solve for IB, IC, IE, and VCE


__________: All capacitors appear as open circuits at DC.

_____________________________________________________________________________________________________________________


a) Apply KVL around paths and KCL at nodes that include the variables of

interest (IB, IC, IE, and VCE) and solve for those variables.


Solution: (Explain each step.)

0CC B B BE E EV I R V I R (21.164)

0B C EI I I (21.165)

C BI I (21.166)

1E B B BI I I I (21.167)

1 0CC B B BE B EV I R V I R (21.168)

1 1CC BE B B B E B B EV V I R I R I R R (21.169)

1

CC BEB

B E

V VI

R R

(21.170)




1

CC BEB

B E

V VI

R R

(21.174)

_____________________________________________________________________________________________________________________


C BI I (21.175)

1E BI I (21.176)


b) Calculate IB, IC, IE, and VCE; answers: 49.1 ABI , 4.91mACI , 4.96 mAEI , 6.09 VCEV

Why is the value of VCE approximately half of the supply voltage?

Example 21.2.3 For the voltage divider bias BJT amplifier shown in Figure 21.6,



R1 = 60 kΩ, R2 = 30 kΩ, RE = 100 Ω, and RC = 600 Ω.

VCC

Cgen

R1

RC

CL

RE

R2

CE

AC

input

signal

AC

output

signal

BC

EIB

IC

IE

IR1

IR2

Figure 21.6 CE amplifier with voltage divider bias and an emitter resistor

_____________________________________________________________________________________________________________________


__________: The CE amplifier circuit in Figure 21.6

VCC = 5 V β = 100 VBE = 0.7 V

R1 = 60 kΩ R2 = 30 kΩ RE = 100 Ω RC = 600 Ω

__________:

__________: a) Determine the Thévenin equivalent circuit of the supply voltage, R1 and

R2 as seen from the base. Apply KVL around paths and KCL at nodes

that include the variables of interest (IB, IC, IE, and VCE) and solve for

those variables.


Solution: Explain the steps being performed in Figures 21.7 and 21.8:

VCC

Cgen

R1

RC

CL

RE

R2

CE

VCC

a

b

Thev.

R1

VCC

R2

Thev.

a

b

Figure 21.7

_____________________________________________________________________________________________________________________


VCC

RC

RE

RTh

VTh

IB

IC

IE

Figure 21.8

What are the equations used to calculate Th Thand ?R V

Develop the bias equations to solve for IB, IC, IE, and VCE on separate paper; then insert values

and calculate.

Results:

Th

Th 1

BEB

E

V VI

R R

, C BI I , 1E BI I , 1CE CC C E BV V R R I

Th 20 kR , Th 1.6667 VV , 32.116 A 32.1 ABI , 3.21mACI , 3.24 mAEI ,

2.75 VCEV

_____________________________________________________________________________________________________________________


21.3 FIELD EFFECT TRANSISTOR (FET) AMPLIFIERS




Identify the terminal names on the FET in Figure 21.9.

D

S

G

ID

IS

n

pG

D

S

Depletion

Region

VDS

VGS

Figure 21.9 n-channel FET diagram

Does VGS establish a forward or reverse bias of the gate-channel junction? Why?

Does the combination of VGS and VDS establish a larger or smaller reverse bias between the gate

and the drain? Why?

If the gate-source voltage were zero volts (a short), what are the two counteracting effects on VDS

(one effect increases VDS, the other effect decreases VDS; identify the effects)?

The condition where these two effects balance and the current levels off is called ___________

Results: the current levels off in the characteristic curves (see the top curve in Figure 21.10).

_____________________________________________________________________________________________________________________


The voltage is called the pinchoff voltage, VP, and the current remains relatively constant despite

further increases in VDS.

0.00E+00

2.00E-03

4.00E-03

6.00E-03

8.00E-03

1.00E-02

1.20E-02

1.40E-02

1.60E-02

1.80E-02

2.00E-02

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00

I D(A

)

VDS (Volts)

FET ID versus VDS

Vgs = 0

Vgs = - 0.25 V

Vgs = - 0.50 V

Vgs = - 0.75 V

Vgs = - 1.00 V

Vgs = - 1.25 V

Figure 21.10 Plot of ID versus VDS at various values of Vgs for a 2N4394 JFET transistor

(The characteristic curve values were calculated using PSpice®.)

Explain how amplification is possible in terms of the gate-to-source reverse-bias voltage:

Given that the pinchoff voltage, VP, is the value of VDS where the channel current levels off when

VGS = 0, does any other voltage contribute to the reverse bias between the gate and the channel?

Explain.

_____________________________________________________________________________________________________________________


As VGS increases, why does the channel current level off at lower level?

When VGS equals VP, where does the channel current ideally level off ? Why?

Hence, when VGS reaches the pinchoff voltage, the channel is cut off (zero current).

Identify the following symbols:

VGS

ID

VDS

What is the relationship

2

1 GSD DSS

P

VI I

V

? ________________________________ (21.151)

What is IDSS ?

What is VP ?

Why does ―pinchoff‖ occur?

What is VGS(cutoff) or VGS(off)?

_____________________________________________________________________________________________________________________


Note that the pinchoff voltage is used in two respects: one in terms of drain-source voltage and

one in terms of gate-source cutoff voltage.

Identify the approximate pinchoff voltage in the characteristic curves in Figure 21.10 from both

viewpoints.


How does the circuit below operate to compensate for the variation in FET specifications?

RG

RD

Cgen

CL

VDD

GD

S

VGS

RS C

SiVoV R

L

oZiZ

Rgen

genV

Figure 21.11 Self-bias FET circuit

Explain each equation in the bias analysis:

0S SGS R GS R GS D SV V V V V I R (21.152)

2

1 GSD DSS

P

VI I

V

(21.153)

_____________________________________________________________________________________________________________________


GS D SV I R (21.154)

2 2

1 1D S D SD DSS DSS

P P

I R I RI I I

V V

(21.155)

2

1 2 D S D SD DSS

P P

I R I RI I

V V

(21.156)

2 2 2 2 2 2 22 2D P DSS P D S P D S P DSS D S P DSS D S DSSI V I V I R V I R V I I R V I I R I (21.157)

2 2 2 22 0D S DSS D S P DSS D P P DSSI R I I R V I I V V I (21.158)

2 2 2 22 0D S DSS D S P DSS P P DSSI R I I R V I V V I (21.159)

2 2 22S DSS S P DSS P P DSSA R I B R V I V C V I (21.160)

2 4

2D

B B ACI

A

(21.161)

How many solutions does the quadratic equation produce? _____ Why?

Solutions to reject are:

a complex number solution

ID greater than IDSS (explain why)

|VGS| = ID RS greater than VP (explain why)

transconductance gm greater than gmo (these quantities are covered in the AC discussion)

VGS = -ID RS

How is VDS then determined?_____________________________________________________

_____________________________________________________________________________________________________________________


Example 21.3.1 For the self bias FET circuit shown in Figure 21.40 and component values

given below, determine the bias levels. [Note: the transconductance

solution will be utilized in a later chapter.]

Explain each step in the following bias solution:

gm2 2.538 103

gm1 8.598 103

gmo 3.6 103

gm2 gmo 1VGS2

VP

gm1 gmo 1VGS1

VP

gmo 2IDSS

VP

transconductance:



ID2 4.472 103

ID2B B

24 A C

2 A



criterion: reject a solution if:

1) I-D is greater than I-DSS

2) V-GS is greater than V-P

3) g-m is greater than g-mo

ID1 0.051ID1B B

24 A C

2 A

C VP2

IDSSB 2 IDSS RS VP VP2

A RS2

IDSS

RD 1000VDD 15RS 330VP 5IDSS 0.009

Which solution is rejected? ___________________ Why?

Is the other solution viable? ___________________ Why?

_____________________________________________________________________________________________________________________


21.5 HOMEWORK PROBLEMS

1. Define amplification.

2. Identify the two most common active devices utilized in amplifier circuits.

3. What are the two main reasons why bias is required in transistor amplifier circuits?

4. For the amplifier circuit in Example 21.2.2,

a) Recalculate the bias levels for β = 50. What happened to each bias level relative to the

β = 100 case? Explain why for each bias quantity.

b) Develop the equations for IB, IC, IE, and VCE for this amplifier circuit if RE = 0. Check

your results by substituting RE = 0 into the IB, IC, IE, and VCE equations when RE ≠ 0.

c) Calculate the bias levels for β = 100 and β = 50 in the amplifier circuit of part b (RE =

0). Compare and explain the changes in IB, IC, IE, and VCE from β = 100 to β = 50 in

this amplifier circuit to the changes in the previous amplifier circuit where RE = 300 Ω.

5. For the amplifier circuit in Example 21.2.3,

a) Calculate the values for IR1 and IR2 . Are these currents approximately equal? Explain

why or why not. Which one is technically larger? Why?

b) Re-calculate the values for IB , IR1 and IR2 for the case where R1 and R2 are increased by

a factor of five.

c) Re-calculate the values for IB , IR1 and IR2 for the case where R1 and R2 are decreased

by a factor of five.

d) Compare and explain the changes in IB , IR1 and IR2 for this amplifier circuit between

the three sets of values for R1 and R2.

6. Determine the bias for the circuit shown in Figure P21.6 given:

R1 = 6.8 kΩ

R2 = 1 kΩ

RC = 560 Ω

RE = 120 Ω

RL = 820 Ω

Cgen = 1 μF

CL = 1 μF

CE = 22 μF

VCC = 9 V

Rgen = 50 Ω

β = 165

Figure P21.6 BJT amplifier circuit for Problem 6

VCC

Cgen

R1

RC

CL

RER

2C

E

Rgen

RL

genV ~

iV

~

oV

_____________________________________________________________________________________________________________________



RB = 220 kΩ

RC = 330 Ω

RE = 560 Ω

RL = 820Ω

β = 165

Cgen = 1 μF

CL = 1 μF

CE = 10 μF

VCC = 9V

Rgen = 50 Ω

Figure P21.7 BJT amplifier circuit for Problem 7


RG = 510 kΩ

RD = 1 kΩ

RS = 560 Ω

RL = 1 kΩ

IDSS = 20 mA

VDD = 9V

Rgen = 50 Ω

VGS(off) = -1.5 V

Cgen = 1 μF

CL = 1 μF

CS = 10 μF

Figure P21.8 FET amplifier circuit for Problem 8

VCC

Cgen

RB

RC

CL

RE

CE

Rgen

RL

genV ~

iV

~

oV

RG

RD

Cgen

CL

VDD

GD

S

RS C

SiVoV R

L

Rgen

genV

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Chapter 21 Bias in Transistor Amplifiers - Welcome to MATCecampus.matc.edu/.../electronics/662_112_lectures/ch21biasSp09m.pdf · Chapter 21 Bias in Transistor Amplifiers* by Robert