CHAPTER 2 Fabrication

CHAPTER 2 Fabrication

Synopsis

Process flow: deposition, lithography, removal

Conformality of deposition, anisotropy of etching and selectivity of etching, and their relationship to cross-sections.

Process incompatibility due to thermal constraints and topographic constraints.

Introduction

MEMS fabrication is based on IC technology. As a result, the vast majority of the processes are identical in MEMS fabrication and IC fabrication. In this chapter we will explore the tradition IC fabrication techniques, and then take a look at the MEMS specific techniques in subsequent chapters.

Throughout the chapter the emphasis will be on how the processes affect and con-strain the designer. How does the process affect the cross-section. What are the restrictions on composing a process?

As a result, we will focus on compatibility, conformality and isotropy, selectivity.

Introduction to MEMS Design 27

Fabrication

28

Substrate

PolysiliconPhotoresis

LTO

Substrate

Polysilicon

MaskPhotoresis

Light

LTO

Substrate

PolysiliconPhotoresis

LTO

Cl−Cl

−Cl

− Cl−

Cl−

Photoresist

Polysilicon

Process Flow

The IC process consists of variations on a theme of deposition, lithography, and removal. These operations are performed on a starting substrate made of silicon in the vast majority of cases.

FIGURE 11. Basic process flow for ICs and MEMS.

FIGURE 12. Example of one trip through the basic process flow. A thin film is deposited, followed by a thin film of photoresist. The PR is exposed and developed, leaving some regions of the first film protected, and other regions exposed.

FIGURE 13. (in the margin) Example of a typical single-mask surface micromachining process. A sacrificial low temperature oxide is followed by a layer of polycrystalline silicon. The silicon layer is etched with a photoresist mask. The remaining structures will be undercut at different times in an HF etch.

Pattern Definition(masking)

ChipsWafer

Removal(etching)

Deposition

500µm

<1 µm

Wafer

Thin film

Wafer

Photoresist

Mask

Light

WaferWafer

Patterned thin film

t

t

t

Introduction to MEMS Design

Process Flow

Substrates

Wafer fabrication for MEMS and ICs is very much the same. The process starts with single crystal silicon wafers. These wafers themselves are a miracle of engi-neering, made from silicon stock which is “nine 9s” pure, having only one impurity per billion atoms. Typically the silicon in the wafers has impurities intentionally added in order to achieve certain electrical properties discussed in Chapter xxx (materials).

FIGURE 14. Silicon wafer fabrication (from Streetman and Sze).

FIGURE 15. Silicon wafer fabrication.

Silicon wafers commonly available around 2000 are 100, 150, or 200 mm in diam-eter. These wafers are typically approximately 0.55, 0.65, and 0.8 mm thick respec-tively. One side of the wafer will be polished smooth, with a surface roughness of a


Fabrication

30

Vacuum line

Motor

Wafer

Liquid

few tens of nanometeres over millimeter to centimeter distances, and variations of a few microns across the whole wafer.

FIGURE 16. Wafer identification flats. (Sze)

Silicon wafers are made of crystaline silicon and are often referred to as “single crystal silicon”. This is not strictly true, in that there are many defects in the crystal structure, but it is true that with the exception of a few hundred trillion defects the remaining hundreds of billions of trillions of atoms in a silicon wafer are arranged in perfect crystalline order and beauty. The orientation of the surface of the wafer relative to the symmetries of the crystal is important, and will be discussed in Chap-ter XXX (mems etching).

Many other types of wafers are available, including quartz, pyrex, saphire, salt (crysalline NaCl), and plastic. These substrates are often extremely useful for spe-cific tasks, but are not part of the general fabrication flow of either ICs or MEMS.

From the starting substrate, devices and systems are made by a repetitive applica-tion of conceptually simple processes: deposit something on the wafer, cover part of it up, and remove the part that you didn’t protect. In implementation, of course, this turns out to be a little tricky.


Deposition

Deposition

Most IC deposition processes put down a “thin film”. This term is defined in rela-tion to the “thick film” processing of the circuit board industry. From a macro-scopic point of view, both types of films are pretty thin, but the thin films get down to the limit of what we can call a film: single molecule thicknesses in some cases.

Spin Casting

Nature has given us a remarkable largesse in the physics of viscous flow on spin-ning disks. It turns out that if you put a viscous liquid on the center of a flat disk and spin the disk, the resulting film on the surface of the disk will be quite uniform. The thickness is a strong function of the viscosity of the liquid, and only a weak function of the spin speed and spin time. The final thickness is also almost com-pletely independent on the shape of the original blob of fluid on the wafer, so long as the blob has sufficient volume and covers the center of rotation of the wafer.

The most commonly used spin-on material is photoresist (see Lithography XXX). Additional materials include polymers (polyimides, Teflon, and PMMA) and many sol-gel materials (silicon dioxide, PTO, PZT). In general, the polymer films do not survive temperatures above 400 C, and most will not survive that high. Polyimides go to higher temperatures than any other commonly used polymers, surviving tem-peratures around 500C. Sol-gel ceramics can usually withstand much higher tem-peratures.

Spin cast sol-gel silicon dioxide is usually refered to as spin-on glass, or SOG. The pre-cursor liquid contains solvents and a molecule with silicon and oxygen in the correct proportion (1:2), along with organic radicals. SOG films are generally quite inviscid, and typically give thicknesses in the tenths of microns. Once the liquid is spun on, the solvents evaporate and a thin solid film is formed. When this film is raised to a temperature of between 400 and 500 C, the organic radicals on the mole-cule are driven off, leaving behind mostly pure silicon and oxygen1. The material properties of this silicon dioxide film can be dramatically improved by raising the temperature above 900 C, but in most processes this is not necessary. SOG films have no upper temperature limit, other than the intrinsic limits of silicon dioxide films.

1. In many cases impurities such as boron and phosphorous are added intentionally to the original mix, and remain behind in the solid silicon dioxide layer.


Fabrication

32

Spin cast materials tend to planarize the wafer surface. If there is topography due to previous fabrication steps, the wafer surface after spin casting will be flatter than it was before.

Thermal Oxidation

Silicon is the second most plentiful element in the earth’s crust, making up 28% of it’s weight. Most of this silicon is bound in silicates. We walk on silicon all the time - it’s one of the key ingredients of sand, which is mostly SiO2. Silicon wafers are made by removing the silicon from SiO2, and one of the most common thin film processes is to recreate SiO2 from a silicon surface using high temperature and oxygen or water. The process is very similar to rusting of metal, with the key dif-ference that the “rust” that forms on silicon forms a very stable bond to the silicon beneath it. It is this property that made silicon the material of choice for the IC industry.

Table 1: Spin cast materials

Material thickness bake temp oC

photoresist 0.1 -- 10 µm 90-150

polyimide 0.3 -- 100 µm 350--450

silicon dioxide (SOG)

0.1 -- 0.5 µm 450 or 900

lead titanate (PTO)

0.1 -- 0.3 µm 650


Deposition

FIGURE 17. Thermal oxidation. The silicon surface is consumed during the formation of the silicon dioxide.

The rate of oxide growth on bare silicon is initially linear, dependent on the reaction rate of oxygen or water with the surface. This reaction rate is a strong function of the temperature. Once a film of silicon dioxide has been grown, further growth is slowed due to the time for oxygen to diffuse through the existing layer. Don’t for-get that the growth occurs at the interface between the silicon and the oxide - not at the surface of the oxide. This results in an oxidation rate that slows continually as the existing oxide thickness increases. This leads to a practical upper bound on thermal oxide film thickness of a few microns.

FIGURE 18. Silicon dioxide growth rate. (Sze)

Since silicon is consumed in the formation of SiO2, the interface between the sili-con surface and the silicon dioxide surface moves into the silicon wafer as the oxide

0.54 tox0.46 tox

tox


Fabrication

34

thickness increases. The ratio of the silicon thickness consumed to the oxide thick-ness formed is 0.46 .

Low Pressure Chemical Vapor Deposition

Some gases will disassociate spontaneously on contact with a surface. For silane (SiH4), this disassociation generates solid silicon on the surface and liberates hydrogen gas. This reaction takes place very slowly below temperatures of 580 C (happening essentially not at all at room temperature). It turns out that if a low pressure gas source is used, and the temperature is controlled accurately, then the deposition rate can be accurately controlled along with the quality and uniformity of the thin film. This process is known as low pressure chemical vapor deposition (LPCVD). If the process is done at atmospheric pressure, it is known as APCVD.

FIGURE 19. LPCVD systems (Sze).

FIGURE 20.

Step coverage in deposited films. Non-conformal, perfectly conformal, and poorly conformal. Notice that in the conformal films the obtuse corners are rounded and the acute corners are sharp.


Deposition

LPCVD processes have very different surface coverage properties. Polysilicon and silicon nitride are both quite conformal, able to uniformly coat large cavities through small openings. Silicon dioxide, on the other hand, is typically not very conformal, giving much thin coatings at the bottom of trenches than at the top. Even trenches with aspect ratios as low as 1 will still have substantial variation in film thickness.

[xxx - do they know about stress yet?]

Poorly conformal films can be used to seal a buried cavity, while highly conformal films can be used to coat the inside surface. Figure xxx shows a common problem with the poor conformality of low temperature oxides when used to film high aspect ratio trenches. Because the film deposits faster at the top of the trench than at the bottom, the top seals shut before the bottom has been fully filled.

The deposition temperatures for polysilicon and silicon nitride preclude their use if aluminum is present on the wafer. Clearly none of these films can be deposited on a wafer with any polymer films. Silicon dioxide is deposited at around 450C, which means that it can, in principle, be put down on top of aluminum, although this is not allowed in many clean rooms. The low deposition temperature of LPCVD silicon dioxide, compared to the high temperature of thermal oxide growth, leads to the name LTO (low temperature oxide).

FIGURE 21. Pinch off and keyholes. With a poorly conformal film deposited over a high aspect ratio trench the top of the trench can be sealed before the

TABLE 2. LPCVD deposition.

film Source gases temp conformal stress

polysilicon SiH4

(PH3, AsH3)

580-630 excellent +/0/-

silicon nitride SiCl2H2

NH3

800xxx good very tensile

silicon diox-ide

SiH4, O2

(PH3, B2H6)

450 poor compressive

polysilicon-germanium

SiH4, GeH4

(...)

400-500? ? ?


Fabrication

36

bottom is filled, resulting in a keyhole shaped void.

.

Silicon nitride deposited under normal conditions for ICs is extremely tensile. This is fine for applications in which it remains bolted to the substrate, but in many MEMS applications the silicon nitride will play a structural role. In this case, its internal stress can actually tear it apart (see section xxx for examples of how to cal-culate when this will happen).

It is possible to reduce the stress in a silicon nitride film by growing a film which is silicon-rich. (A naive way of looking at this is that silicon is a bigger atom than nitrogen, so putting a little more of it into the film makes it less tensile.) Silicon nitride is deposited by flowing dichlorosilane and ammonia in a ratio of about 1:5. Nitride likes to deposit in its stoichiometric form, Si3N4. In order to add more sili-con to the film, more dichlorosilane is added to the mix. It turns out that a film composed of roughly the same number of silicon and nitrogen atoms gives an acceptable stress level. To achieve this, it is necessary to invert the ratio of the source gases - 5 parts dichlorosilane to 1 part ammonia.

Silicon dioxide is deposited from silane (SiH4) and oxygen. It goes down in a rela-tively stress-free state, but because the thermal expansion coefficient of silicon is fairly high, and that of silicon dioxide is fairly low, as the wafer cools the silicon shrinks and the silicon dioxide doesn’t. As a result, oxide films are compressive. This is also true of thermal oxides.

LTO, PSG, BPSG, densification. reflow, etch rates

Often silicon films or silicon dioxide films are doped with phosphorous or boron during deposition. This is done by adding phosphine (PH3) or diborane (B2H6) to the source gases during deposition. 1 A phosphorous-containing oxide deposited by LPCVD is a phosphosilicate glass, or PSG. Adding boron, or both boron and phosphorous, gives borosilicate and borophosphosilicate glasses (BSG and BPSG).

All of the low temperature glasses have very poor mechanical properties as depos-ited. They are porous, and filled with cracks and voids. This makes their etch rates


Deposition

both fast and unpredictable. As a general rule, low temperature glasses should be annealed as soon as they are deposited. This will result in a densification of the film (up to 10% decrease in thickness), and make its mechanical and chemical properties more uniform and predictable. Annealing at 900C or above for 30 min-utes is common.

During the annealing process, surface tension will have an effect on the overall shape of the film, in a process called reflow. Adding either phosphorous or boron decreases the temperature at which the glass will begin to reflow.

FIGURE 22. Reflow of a glass during annealing. Convex corners are flattened, while concave corners are rounded. In extreme cases, the underlying material of a convex corner may be exposed.

In general, any combination of thermal oxidation and LPCVD is acceptable. Oxide, nitride, and poly can be deposited on top of each other, and on top of ther-mal oxide. Polysilicon can be thermally oxidized after deposition as well.

At least one combination of LPCVD films should be avoided, however. Often a sil-icon nitride layer will be deposited first, then a heavily phosphorous doped oxide, followed by a polysilicon structural layer. If this particular combination is annealed at temperatures over 900C (xxx check Roger’s email and get reference), bubbles will appear in the polysilicon! These bubbles are quite repeatable, and in fact have been proposed as caps or reservours. This particular combination of layers comes up quite often, and has ruined the wafers of countless graduate students at UC Ber-keley (Roger Howe, Bill Tang, Mike Judy, and the author, among many others - you’d think that we’d learn!).

1. It is worth noting that these gases are extremely lethal, with fatal levels in th ppb range. As a result, both typically are delivered mixed with silane, which is pyro-phoric (burns on contact with air), under the theory that you’d rather have fires and explosions than kill everyone for blocks with poison gas.

before (poorly conformal) after reflow


Fabrication

38

As deposited, polysilicon has very high resistivity - on the order of 105 Ωcm, giving films with sheet resistance above a GΩ/square. In some cases this is desired (load resistors for static RAM bits, for example), but in general, people like their polysil-icon to be conductive.

Polysilicon can be made conductive by doping it with either phosphorous, arsenic, or boron using the same additive gases described above for LPCVD silicon dioxide. When polysilicon is deposited with the boron or phosphorous incorporated during deposition, this is refered to as “in-situ” doped poly. Dopants can also be added to polysilicon films by diffusion after the film has been deposited. This is typically done by depositing a phosphorous doped oxide (PSG) followed by an undoped pol-ysilicon layer, and a second PSG layer on top of the undoped poly. This oxide/poly/oxide sandwich is then annealed at 900-1100 degrees for 1-60 minutes to allow the phosphorous to diffuse out of the oxide and into the polysilicon. The top layer of oxide is used to generate a symmetric doping profile vertically through the polysilicon film. Without this symmetric doping, the polysilicon would end up with a higher concentration of phosphorous on the bottom surface, which would generate compressive stress, and result in structures which curve out of the plane of fabrication in an annoying and non-useful way.

Polysilicon which is doped by annealing typically does not have Phosphorous lev-els as high as in-situ poly, and as a result the conductivity is lower than a compara-ble thickness film of in-situ doped poly.

Evaporation

Evaporation is a conceptually simple way of depositing many films, in particular most metals. The simplest evaporators consist of a source boat made of a refractory metal such as tungsten which is heated by passing current through it. The desired material (e.g. aluminum) is placed in the boat, and the target wafers are placed face down above the boat. The chamber is pumped down to high vacuum, and the mate-rial is melted, and then boiled. The deposition is line-of-site, so confomality is nearly zero.


Deposition

FIGURE 23. Thermal evaporators (Sze).

More sophisticated evaporators use an electron beam to heat the target material. In this case even refractory metals and ceramics can be evaporated.

Although the material is boiled as it leaves the source, the total heat energy sup-plied to the target substrate can be kept fairly low by controlling the deposition rate. As a result, it is possible to evaporate thin films onto wafers with thermally sensi-tivie layers (such as photoresist).

PECVD

Using low power plasmas (discussed under etching) it is possible to deposit a vari-ety of thin films, including anything that can be deposited by LPCVD (poly, nitride, oxide, ...) PECVD films are typically lower quality than their LPCVD partners. In particular, silicon nitride and silicon dioxide films deposited by PECVD often suf-fer from pinholes, which can make them unsuitable for masking isotropic etches.

PECVD deposition is generally not very conformal.

Sputtering

Sputtering is a material removal process, but it appears here under deposition because the material removed from one place (the target) ends up being deposited on another (your wafers). In a sputter deposition, a plasma is used to generate high energy ions which can knock material off of a target. This will be covered under plasma etching, below.


Fabrication

40

FIGURE 24. Sputtering system and yield. (Sze)

Layout and Lithography

Once we have a thin film on the wafer surface, we need to sculpt it into the desired shape. The methods of material removal are covered in the next section. This sec-tion is concerned with determining which parts of the material will be removed, and which will be kept.

Layout and mask making

Layout is the heart of MEMS design. It is the process by which your creative ideas are turned into geometry which will implement them. You “do layout” using any of a number of CAD programs which offer varying degrees of computer assistance. Ultimately, the goal is to draw a collection of geometric elements which will be transfered into the thin film currently sitting on the wafer.

Photoresist and lithography

Incompatibilities

No photoresist over big steps or deep holes. Depth of focus related to feature size leads to topography problems. No photoresist for masking KOH etc.


Removal

Removal

Wet etching

An in-depth discussion of wet etching involves several courses in chemistry which most of us have not had. The chemistry of silicon etching is complex, and is still an area of active research. Silicon etching will be covered in some depth in the next chapter.

Wet etching is typically done in glass or Teflon beakers, with wafers supported in a Teflon carrier. Etching times vary from a 10 second dip that might be used to strip off a so-called “native oxide”, through several-day soaking to etch a thin layer between two flat surfaces.

FIGURE 25. Isotropic etching profiles. Small apertures generate

hemispherical etch cavities, while larger apertures generate oval shape cross-sections. From a top view, external corners remain sharp as they etch back under the mask, but internal corners are rounded.

Most wet etching is isotropic, with silicon etching being a very important exception (more on this in Chapter xxx). Isotropic etching means that the etch rate is inde-pendent of direction. In principle, etching through a small hole using an isotropic etchant should yield a hemispherical etch cavity. In practice it doesn’t always work out that way. There can be variation due to temperature gradients in the etchant and the material being etched, surface effects under the mask, bouyancy effects due to different density of etchants and etch products, and bouyancy effects due to thermal gradients near the etch surface.

Cross section Top view

Masking layer


Fabrication

42

FIGURE 26. HNA etching curves (from Sze).

The most common wet etchants are listed in table xxx.

TABLE 3. Wet etchants.

Etchant SiO2 Si3N4


Removal

Plasma etching


Fabrication

44

Removal

MATERIAL <100> n+ undop Ox Ox undop unanl annld Nitrid Nitrid 2% Si Tung Ti Ti/W 820PR HniiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiSilicon - 0 - 23k F >14k F 36k 140 52 42 <50 F - P 0 Poxides 18k 30 0

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1080 4400 4 20iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiSilicon - 7 - 0.7 0.8 <1 37 24 28 19 9800 - - - 550nitrides 9 28 19

24 42 42iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii5 NH

4F) Silicon 1500 3100 1000 87 W 110 4000 1700 2 3 4000 130 3000 - 0

12006000iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

<100> Silicon 14k >10k F 77 - 94 W 380 0 0 F 0 - - F


: 1 HNO3

: 1 HAc : 2 H2O) Alumnium - <10 <9 0 0 0 - <10 0 2 6600 - 0 - 0


HF) Titanium - 12 - 120 W W W 2100 8 4 W 0 8800 - 0

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Tungsten - 0 0 0 0 0 0 0 0 0 <20 190 0 60 <2

190 601000 150iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

Cleaning off - 0 0 0 0 0 - 0 0 0 1800 - 2400 - F

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Photoresist - 0 0 0 0 0 - 0 0 0 0 - 0 - >44k >

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hamber 2900 1100 1100 120 0 440 50100k 2500 2300 180 2 1000 380iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

RCP Thin W 6400 7000 300 W 280 530 540 1300 870 - W W W 1500 1

silicon 2000 220 830 13006MHz nitrides 7000 400 2300 1500iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiCP Thick W 8400 9200 800 W 770 1500 1200 2800 2100 - W W W 3400 3

silicon 2100 31006MHz nitrides 4200 3400iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

Silicon W 1900 2100 4700 W 4500 7300 6200 1800 1900 - W W W 2200 2

oxides 1400 1500 2400 3000 2500Hz 1900 2100 4800 7300 7200iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiIO2ET.RCP Silicon W 2200 1700 6000 W 6400 7400 6700 4200 3800 - W W W 2600 2

oxides 2200 1700 2500 6000 5500 5000 4000 2600 2Hz 2700 2100 7600 6400 7400 6700 6800 6700 7iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

m) Aluminum W 4500 W 680 670 750 W 740 930 860 6000 W - - 6300 6

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0, 500, 550 Silicon W 5700 3200 8 - 60 230 140 560 530 W W - - 3000 2

a 5000 3400 3200 8 2400, 13.56MHz 5000 6300 3700 380 3000iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii, 550 Silicon W 450 460 4 - 0 0 0 870 26 W W - - 350

a 450 4 350, 13.56MHz 740 10 500iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

Descumming - 0 0 0 0 0 0 0 0 0 0 0 0 - 350

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Ashing - 0 0 0 0 0 0 0 0 0 0 0 0 - 3400 3

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Silicon 300 730 670 310 350 370 610 480 820 620 - W W W 690

sma nitrides 300 730 670 230 550 690z sq. wave 1000 800 760 480 800 830iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

Silicon 1100 1900 W 730 710 730 W 900 1300 1100 - W W W 690

sma nitridesz sq. waveiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

Tungsten W 5800 5400 1200 W 1200 1800 1500 2600 2300 - 2800 W W 2400 2

2000 1900 2800 24002000 2300 4000 4000iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

Thin W 1700 2800 1100 W 1100 1400 1400 2800 2300 - W W W 3400 3

silicon 1100 2800 2900nitrides 1600 2800 3400iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiSi-rich W 350 360 320 W 320 530 450 760 600 - W W W 400

siliconnitridesiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiic

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performed, but known to Work ( >∼ 100 A./min); F=not performed, but known to be Fast ( >∼ 10 kA

./min);

en rinsed; A=film was visibly Attacked and roughened.ificant figures.e transparent films and half of the wafer for single-crystal silicon and the metals.

d prior use of solution or plasma chamber, area of exposure of film, other materials present (e.g., photoresist), film impurities and microstructure, etc. Some variation should be expected!


Fabrication

46

Other Processes

Ion implantation

FIGURE 27. Ion implanter (from Runyan and Bean).

FIGURE 28. Ion implantation range and straggle (from Sze).


Layout and Lithography II: Design rules

Liftoff

Wafer Sawing

Die Attach and Wire Bonding

FIGURE 29. Two types of wire bonders.

Packages

ceramic, injection molded plastic, ???

Layout and Lithography II: Design rules

Minimum Feature Size

non-conformal photoresist

edge effects


Fabrication

48

stringers

FIGURE 30.

test structures

1. conduction between interdigited conductors on layer 2 above lots of topography on layer 1.

Simulation Tools

Process simulation

Other figs:

Streetman p11,14, 371

Sze p109,305,315,343,350,355,359, 366a, 366c, 371, 410, 411fig23, 453, 456,

Runyan p506,

tply2

t + t + tply2 ply1 ox2 stringer


References

References

Neudeck, G.W. and Pierret, R.F., Introduction to Microelectronic Fabrication, Vol-ume V in the Modular Series on Solid State Devices, R. Jaeger ed., Addison-Wes-ley, 1993.

Sze, S.M., Semiconductor Devices Physics and Technology, Wiley and Sons, 1985.

W. M. Runyan, K.E. Bean, Semiconductor Integrated Circuit Processing Technol-ogy, Addison-Wesley, 1990

B.G. Streetman, Solid State Electronic Devices, Prentice-Hall, 1990.

Questions

1. Find the flaw(s) in the following process flows.

2. Design a process flow to create the following cross-sections.

3. What are the advantages and disadvantages of integrated circuit fabrication techniques compared with: injection molded plastics, machine tool based fabri-cation, ...

4. What viscosity should I use to get a 1 micron thick film when spin-casting at 1000 rpm?

5. How long should I oxidize a bare silicon wafer in dry O2 at 1000C to get a 0.1 micron thick film? How about a 1 micron thick film? What if I use steam?

6. A silicon wafer has 1 micron of thermal oxide on it. If I oxidize in dry O2 at 1000C, how long will it take to grow 0.1 micron more oxide? What if I use steam?

7. Calculate the angle between the 100 plane and the 111 plane.

8. KOH has a selectivity between 100 and 111 of at least 400:1 . Calculate the actual sidewall slope of a pit etched with such a solution. EDP selectivity is typically closer to 20:1. Calculate the slope of sidewalls etched in EDP.

9. A 2 micron film of LTO is deposited on a wafer with 10 micron deep trenches. Draw the cross section of trenches with widths of 10, 3, and 1 micron widths. Assuming that the trenches are simple rectangular patterns on the wafer and do not widen anywhere along their length, which of these three trenches will be sealed, and what will be the composition and pressure of the gas inside?


Fabrication

50

10. In the problem above, assume that at both ends the 3 micron wide trench slowly expands to a 20 micron width. What will the final “sealed” shape look like? What if the expansion were abrupt, i.e. a 3micron wide rectangle abutting a 20 micron square at either end?


Documents

CHAPTER 2 Fabrication