CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 1 Power Converters and Drives Lab -a Research Overview Prof. K. Gopakumar Centre for Electronics Design

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 1

Power Converters and Drives Lab-a Research Overview

Prof. K. GopakumarCentre for Electronics Design and Technology

Indian Institute of Science, BangaloreINDIA: 560012


A1

S1

S4

S5

S2

B1

S3

S6

C1

Vdc

Conventional two-level inverter structure

Inductionmotor


Vdc /2

-Vdc /2

0

C1

wt

asV bs

V Vcs

SVPWM for conventional two-level inverter


Ref

eren

ce s

ign

als

and

car

rier

(wt)

vAN vBN vCN0.5

-0.5

V a0

V b0

V c0

Vdc/2

Vdc

/2

Vdc/2

-Vdc/2

-Vdc/2

-Vdc/2

Vt

π/2 π 3 π/2 2 π

Pole voltage waveforms in conventional two-level inverter


Multilevel inverters Topologies

Inverter topologies cascading two level inverters Inverter topologies with open-end IM drive Inverter topologies with asymmetric DC link voltages

Multilevel inverter topologies for common mode voltage elimination

Two-level inverter scheme with common mode voltage elimination Higher level of multilevel inverter scheme

DC-link capacitor voltage balancing winding induction motor drive Three-level structure with single power supply

PWM signal generation for multilevel inverter A Space Phasor Based Self Adaptive Current Hysteresis

Controller Multi-phase (six-phase) and multi motor drive Sensorless control scheme for IM drive 12-sided polygonal voltage space phasor generation.

Presentation outline


Multilevel inverters


•Synthesis of higher voltage levels using power devices of lower voltage ratings

• Increased number of voltage levels which leads to better voltage waveforms and reduced Total Harmonic Distortion (THD) in voltage • Reduced switching stresses on the devices

Advantages of multilevel inverters over the two-level inverters


CAo

S11

S12

S13

S14

S21

S24

S23

S22

S31

S32

S33

S34

B

C1

C2

Vdc

+

_

3-ph Ac mains

Neutral clamped inverter topology for 3-level inversion

• The neutral point fluctuates as the capacitors C1 and C2 carry load currents• Bulkier capacitors are needed to check the neutral point fluctuation• PWM strategies aim to balance the neutral point dynamically


Dual Inverter fed induction motor with open end winding


a’

Vdc/4

Vdc/4

o ab c

b’ c’

Inverter-I Inverter-II

Dual Inverter fed induction motor with open end winding

3-ph IM with open wdg.

• The neutral point of the conventional IM is opened and is fed from both sides.• The DC - bus voltage is Vdc/2 .


Space phasor locations for Inverter-I (Left) and Inverter-II (Right)

6 (+-+)

(-++) 4 1 (+--)

2 (++-)(-+-) 3

(--+) 5

7 (+++)(---) 8(-++) 4’ 1’ (+--)

2’ (++-)(-+-) 3’

(--+) 5’ 6’ (+-+)

7’ (+++)(---) 8’

Vdc/2 Vdc/2


Voltage space phasor combinations from the dual inverter scheme

• A total of 64 space phasor combinations are available


Dual Inverter fed induction motor with open end winding with isolated DC power supply

Inverter - 2

c

a’b’

IM withopen-endwinding

ba

c’

Inverter - 1

Vdc/2 Vdc/2

• Triplen harmonic suppression is achieved through the transformer isolation.


A new three-level inverter circuit topology cascading two two-level inverters


The power circuit configuration of a three-level inverter cascading conventional two two-level inverters


Space vector locations of the proposed three-level inverter

Similar to the conventional three-level inverter


• The power Bus structure is simple• Can work as a conventional 2-level inverter in the lower voltage range• The total VA rating of the the transformers is the same as that of the NPC

configuration• High voltage fast recovery diodes are not needed Three devices need to support the total DC bus voltage

Salient features of the proposed three-level inverter configuration


Pole Voltage waveforms of Inverter-1 (Top) and Inverter-2 (Bottom) Phase voltage

Phase current at no-load

|Vsr| = 0.4Vdc

A2

Vdc/2 = 150V

Vdc/2 = 150V

O

A1

Experimental results: lower modulation range




|Vsr| = 0.6Vdc

Experimental results: higher modulation range




|Vsr| = Vdc (Over-modulation)

Experimental results: over modulation range


A new five-level inverter circuit topology cascading two three-level inverters


Introduction

• An inverter system for open-end winding induction motor is presented.

• Open-end winding IM is fed by two three-level inverters• The 3-level inverters are realised by cascading two 2-level

inverters• This inverter scheme results in space phasor locations

similar to a conventional Five-level Inverter


Vdc/4

Vdc/4

Inverter A

+

+

S12S16

S15S13

S22S26S24

S5’

S23S21S25

INV 2

INV 1S11

S14-

C1

-

C2

C4

S32 S36

S35 S33

S42 S46 S44

S43S45

A4B4

INV 4

INV 3Inverter B

S41

S34

S31

-

+

Vdc/4

-

+

Vdc/4

C3 B3 A3 C3

C4

IM

O O’

A2

A1 B1 C1

B2C2

The schematic for the proposed five-level drive

• Inverter A and Inverter B are 3-level inverters• Each three level is formed by cascading two 2-level inverters

INV1,INV2 Inverter A INV3,INV4 Inverter B


Vdc/4

Vdc/4

Inverter A

+

+

S12S16

S15S13

S22S26S24

S5’

S23

S21 S25

INV 2

INV 1S11

S14

-

C1

-

C2

O

A2

A1 B1 C1

B2C2

VA2O

The 3-level inverter topology

Levels in A-leg

0 when S24 is on

( VA2O )

Vdc/4 when S21 and S14 on

Vdc/2 when S21 and S11 on

• The 2-level inverters have DC-link of• This 3-level structure does not require neutral point clamping

diodes

Vdc/4


• All legs of the three-level inverter can independently take any of the three levels

• when inverter-A and inverter-B are switched independently 5-levels can be generated across the winding.

VA20 VA40’VA2A4= VA20- VA40’

000Vdc/4

Vdc/2

Vdc/2

Vdc/4

0 0 0

-Vdc/2 ( L1)-Vdc/4 ( L2)0 ( L3)Vdc/4 ( L4)Vdc/2 ( L5)

* for the first three levels only Inverter-B is switching

Realization of five voltage levels across motor phases


Space vector representation of the proposed Drive

• Similar to a five-level inverter

• 125 space vector combinations • 96 sectors• 61 locations• Four layers


The Modulation scheme

Multi-carrier PWM method is used

Four triangular carriers

20% third harmonic added to the 3 reference signals

A discreet DC shift is given to the reference signals depending on the speed range

With this modulating scheme the inverter starts with 2-level operation and then moves to 3-level, 4-level and 5-level operation as speed increases


• The reference wave set is placed at the middle of the carrier set• Three levels are involved, therefore three-level waveform

Conventional SPWM For Low modulation index

SPWM for the proposed Drive

• The reference wave set is placed at the middle of the lowermost carrier• Only two levels are involved, therefore two-level waveform• Only INV3 is switching ( the top 2-level inverter of Inverter-B) hence losses are only due to INV3


Conventional SPWM


For next speed range (Vc /2< Vm <Vc )

Vc : Peak to peak amplitude of the carrier

Vm : Peak amplitude of the reference wave

• The reference wave set is placed at the middle of the lower two carriers• Three levels are involved, therefore three-level waveform• Only INV4 and INV3 are switching (2-level inverters of Inverter-B)• losses are only due to Inverter-B


Conventional SPWM


For next speed range (Vc <Vm<3Vc/2 )

•Five levels are involved, therefore five-level waveform• All the 2-level inverters have to be switched

•The reference wave set is placed at the middle of second carrier ( C2)• Four levels are involved, therefore four-level waveform• Only INV2, INV4 and INV3 are switching • INV1 is not switching


For the maximum speed range ( Vm> 3Vc/2 )

• The reference set is at the center of the carrier set• All the Five-levels are involved• All the inverters have to be switched


2-Level operation

• Phase voltage shows 2-level waveform

•Inverter-B,is switching between Vdc/2 and Vdc/4 ( 200V and 100V)

•This is due to the switching of INV3 ( top inverter of Inverter-B). INV4 is clamped.

•Inverter-A is clamped to zero

Motor phase voltage during 2-level operation

Pole voltage of Inverter-B during 2-level operation

Pole voltage of Inverter-A during 2-level operation


3-Level operation

• Motor Phase Voltage shows 3-level waveform

• Inverter-B is switching as 3-level inverter (200V,100V,0V)

•Both the 2-level inverters of Inverter-B ( INV3 and INV4 are switching)

•Inverter-A still clamped to zero


Pole voltage of Inverter-B during 3-level operation


4-Level operation



• Inverter-A is switching as 2-level inverter (100V,0V)

•This is due to the switching of INV2( bottom 2-level inverter )


Pole voltage of Inverter-B

Pole voltage of Inverter-A


5-Level operation



• Inverter-A is also switching as 3-level inverter (200V,100V,0V)

Pole voltages of Inverter-A and Inverter BShowing the phase relation (simulation results)


Pole voltages of Inverter-A (top) and Inverter B (bottom) [ experimental results]


Motor phase current

2-level operation

3-level operation

4-level operation

5-level operation


Salient Features

Feeding the open-end winding induction motor by 3-levelinverters, results in voltage space phasors similar to a 5-level inverter

The three level inverters used are realised by cascading Two 2-level inverters. This structure does not require neutralClamping diodes .

Compared with series connected H-bridge topology, the proposed drive scheme uses less number of power Supplies ( four against six required for H-bridge).


Open end winding IM drive (Three level operation) with a single DC link


Dual Inverter fed induction motor with open end winding with isolated DC power supply

Inverter - 2

c

a’b’


ba

c’

Inverter - 1

Vdc/2 Vdc/2

• Triplen harmonic suppression is achieved through the transformer isolation.• All the 64 - space phasor combinations can be used in this case.• The transformers are bulky and expensive.


-Vdc / 2 - Vdc / 3 -Vdc / 6 0 Vdc / 6 Vdc / 3 Vdc / 2

8 – 7’ 8 – 4’ 8 – 5’ 8 – 3’

1 – 1’ 2 – 2’ 3 – 3’

5 – 8’ 3 – 8’

4 – 8’ 7 – 8’

8 – 6’ 5 – 4’ 3 – 4’

4 – 4’ 5 – 5’ 6 – 6’

4 – 5’ 4 – 3’

6 – 8’

8 – 2’ 8 – 1’ 5 – 6’

7 – 7’ 8 – 8’ 1 – 3’

4 – 1’ 1 – 8’

2 – 8’

5 – 7’ 5 – 2’ 3 – 6’

6 – 4’ 1 – 5’ 2 – 4’

6 – 5’ 6 – 3’

7 – 5’

3 –7’ 3 – 2’ 4 – 7’

3 – 5’ 2 – 6’ 3 – 1’

2 – 5’ 2 – 3’

7 – 3’

1 – 7’ 1 – 4’ 1 – 6’

4 – 6’ 5 – 1’ 4 – 2’

7 – 4’ 6 – 1’

7 – 1’

1 – 2’ 6 – 7’

5 – 3’ 6 – 2’

2 – 1’ 7 – 6’

2 – 7’ 7 – 2’

Triplen harmonic contribution from various space- vector combinations (Twenty combinations are available with a triplen harmonic content of zero)


Space phasor combinations with zero triplen harmonic contribution


Proposed power circuit schematic (switched neutral)

+

Vdc

-

3-ph Open-end winding IM

Aux. Sw1 Aux. Sw2

Aux. Sw3 Aux. Sw4

Inv.1 Inv.2

C1C2

• Auxiliary switches SW 1 and SW 3 are opened when inverter-1 assume states 7 or 8.( switched neutral)• Auxiliary switches SW 2 and SW 4 are opened when inverter-2 assume states 7’ or 8’.• For “safe” combinations auxiliary switches are kept closed.


Space phasor combinations used in the proposed control strategy• Space phasor locations G,I,K,M,P,Q and R are forbidden.• For combinations at H,J,L,N,Q and S the auxiliary switches need not be opened ( safe

states).• Other combinations have a zero state at one end. Appropriate auxiliary switches are

opened to achieve triplen harmonic suppression

Title


Pole voltages of individual inverters and the phase voltage (middle)with triplen content when |Vsr| = 0.4Vdc

Actual motor phase voltage (left) and the motor phase current (right)when |Vsr| = 0.4Vdc

Experimental results



Actual motor phase voltage (left) and the motor phase current (right)when |Vsr| = 0.6Vdc




Actual motor phase voltage (left) and the motor phase current (right) when |Vsr| = 0.9Vdc



A Dual Two Level Inverter Scheme for an Open-end winding Induction Motor Drive with a Single DC Power Supply and improved

DC bus Utilization


O

C

D

E F

B

A

14

13

V1V1

G

H

IK

L

M

NS

1817

16

15 V2

V2

8

• The extreme vertices G, I, K, M, P and R are not switched. • The DC-bus utilization is lower by about 15%• Only 40 out of the 64 space vector combinations are used.

P R


• The triplen harmonic currents are denied a path by turning off the auxiliary switches.

• The auxiliary switch pairs toggle in this switching strategy with a fixed frequency.

• At a time only one inverter is connected to the DC link

• The DC-bus utilization is enhanced by about 15% compared to the earlier switching strategy.

Salient features of the switching strategy


• (SW1,SW3) and (SW2, SW4) toggle at a fixed frequency


The motor phase voltage The motor phase current

|Vsr| = 0.4Vdc



The triplen harmonic voltage in (vAO - vA’O’)

Top trace: Voltage across the auxiliary switchBottom trace: Current through the auxiliary switch

|Vsr| = 0.4Vdc



The motor phase voltage The motor phase current|Vsr| = 0.7Vdc

The motor phase voltage with the earlier strategy when |vsr| = 0.6Vdc

Experimental results: three-level operation




Experimental results: over modulation operation



The 12-step operation



Multi-level structures with asymmetric DC link voltages


A Multilevel Voltage Space vector Generation for an Open-end winding Induction Motor Drive using a dual-inverter scheme with

Asymmetrical DC-link voltages


• A dual-inverter fed open-end winding IM drive is proposed, with asymmetric DC-link voltages (in the ratio 2:1). • In this scheme, 64 space vector combinations are distributed over 37 space vector locations with 54 sectors. • The switching ripple is lesser compared to the earlier scheme i.e. with equal DC-link voltages.• The motor phase voltage waveform exhibits either 2-level waveform, 3-level waveform or the 4-level waveform depending upon the motor speed.

Salient features of the proposed Drive


Inverter - 1

Dual Inverter fed induction motor with open end winding with asymmetric voltages showing individual space phasor combinations

(- + - ) 3

(+++) 7 8 (- - -) 1 (+- -)

2 ( ++ - )

( - + + ) 4

( - - + ) 5 6 ( + - + )

2 / 3 Vdc

(+++) 7’ 8’ (- - -) 1’ (+- -)

2’ ( ++ - )

( - + + ) 4’

( - - + ) 5’ 6’ ( + - + )

(- + - ) 3’

1 / 3 Vdc

Inverter - 2

c

a’b’


ba

c’

2/3Vdc1/3Vdc


Space phasor combinations for asymmetrical voltage dual - inverter drive

• 64 space vector combinations • 54 sectors• 37 locations• three layers


Motor phase voltage (left) and the motor phase current (right)when |Vsr| = 0.2Vdc (2-level waveform)

Normalized harmonic spectrum of the motor phase voltage illustrating the absence of the triplen -harmonic content for |Vsr| = 0.2Vdc



The actual motor phase voltage and motor phase current when |Vsr| = 0.5 Vdc (3-level waveform)

Normalized harmonic spectrum of the motor phase voltage illustrating

the absence of the triplen -harmonic content for |Vsr| = 0.5Vdc



Normalized harmonic spectrum of the motor phase voltage illustrating the absence of the triplen -harmonic content for |Vsr| = 0.8Vdc

The actual motor phase voltage and motor phase current when |Vsr| = 0.8 Vdc (4-level waveform)



The actual motor phase voltage and motor phase current when |Vsr| = Vdc

The harmonic spectrum of the motor phase voltage (showing the absence of the triplenharmonic content) for |Vsr| = Vdc



The actual motor phase voltage and motor phase current during square wave ( 18 - step operation)

Normalized harmonic spectrum of the motor phase voltage illustrating the absence of the triplen -harmonic content for 18-step operation



A Multilevel Inverter System for an Open-end Winding Induction Motor


• In the proposed scheme, a total of 512 voltage space vector combinations are present, distributed over 91 space vector locations.

• The three-level inverter in this scheme is realized by cascading two two-level inverters.

• In the lowest speed range, only one of the three inverters is switched. In the medium speed range two inverters are switched and in the higher speed range, all the three inverters are switched.

• This feature ensures that the switching losses are reduced in the lower and the middle range of speed.

• The motor phase voltage shows a 2-level waveform in the lowest speed range, a 3-level or a 4-level waveform in the medium speed range, a 5-level or a 6-level waveform in the higher speed range.

• This configuration needs three isolated power supplies.

The salient features of the proposed scheme


Schematic circuit diagram of the proposed inverter scheme

vA2O vA3O’ vA2A3 = vA2O – vA3O’

0 0

2/5Vdc

2/5Vdc

4/5Vdc 4/5Vdc

1/5Vdc

0

1/5Vdc

1/5Vdc

0

0

-1/5Vdc

0

1/5Vdc

2/5Vdc

3/5Vdc

4/5Vdc


• In the lower speed range, only inverter-3 is switched (2-level waveform)• In the medium speed range Inverter-2 and Inverter-3 are switched (3-level or 4-level waveforms)• In the higher speed range, all the inverters are switched. ( 5-level or 6-level waveform)

Space vector locations from the individual inverter structures


Resultant space vector locations when inverter-1 is inactive i.e. clamped to the state 8(---)

Combined space vector locations (inner layers)


• A total of 91 vector locations with 83 = 512 space vector combinations organized into 5 layers

Combined space vector locations (outer layers)


Motor phase voltage Motor phase current

|Vsr| = 0.12 Vdc (Inner hexagon)

• Inverter-3 is alone switched

Title


Motor phase voltage Motor phase current at no-load|Vsr| = 0.3Vdc (Layer-2)

|Vsr| = 0.48Vdc (Layer-3)Motor phase voltage Motor phase current at no-load

• Inverter-1 and inverter-2 are switched in these two layers



Motor phase voltage Motor phase current at no-load|Vsr| = 0.65Vdc (Layer-4)

|Vsr| = 0.83Vdc (Layer-5)Motor phase voltage Motor phase current at no-load

• All the three inverters are switched in these two layers



Motor phase voltage Motor phase current at no-load


30 – step operation Motor phase voltage Motor phase current at no-load

• All the three inverters are switched in these two cases



Seven-level voltage space phasor generation scheme for an open-end winding induction

motor drive with asymmetric dc link voltages


+

1C

2C

3dcV

6dcV

INV1

INV2

-

1C

2C

3dcV

6dcV

+INV3

INV4

-Inductionmotor

• Higher-level voltage waveforms can be synthesized when individual inverters are supplied with unequal DC link voltages

• Seven-level space phasor generation from a five-level inverter• DC link voltage of the top two-level inverters is Vdc/3• DC link voltage of the bottom two-level inverters is Vdc/6

+-

+-

Multi-level inverter configuration for induction motor with open-end winding structure with asymmetric DC Links


• Requires only four isolated power supplies

+

1C

2C

3dcV

6dcV

INV1

INV2

-

1C

2C

3dcV

6dcV

+INV3

INV4

-Inductionmotor

+-

+-

Multi-level inverter configuration for induction motor with open-end winding structure with asymmetric DC Links


O’

Vdc/2

Vdc/6

Seven-level inverter configuration with asymmetric dc link voltages


Seven-level voltage space phasor generation


343 space vector combinations127 space vector

locations 216 triangular

sectors

Space vector diagram of seven-level inverter


Comparison: proposed inverter scheme withH-bridge inverter configurations

Proposed seven-level inverter

H-bridge seven-level inverter with symmetric DC links

H-bridge inverterasymmetric DC links

Maximum device rating

Top inverter: Vdc/3 Bottom inverter:

Top devices Vdc/6 Bottom devices Vdc/2

Vdc/6 Vdc/3

Switches 8 per phase 12 per phase 8 per phase

DC link power supplies

2 (Vdc/3)

2 (Vdc/6)

9 (Vdc/3) 3 (2Vdc/3)

3 (Vdc/3)

Seven-level voltage space phasor generation scheme


12

3

45

6

78

910

1112

13

141516

17

1819

2021

22

2324

2526

2728

2930

3132

3334

35

3637

3839

4041

4243

4445

4647

4849

50

5152

5354

5556

5758

5960

6162

6364

6566

6768

69

7071

7273

7475

7677

7879

8181

8283

8485

8687

8889

90

9192

9394

9596

163164

165166

167168

169170

159160105106

107108

109110

113114

115174

175

151152

153154

155156

157

29210

212

214

216

9798

99100

101102

103

143144

146

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150

145

147

149

211

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194195

196197

1989199

200201

202205

206203

204

132133

134135

136137

138139

140207

208141

142

118119

120121

122123

124125

126127

128129

116117176

177

178179

180181

182183

184185

186187

188189

190191

130131

192193

161162172

173 171

112111

158104

A

B

C

axis

axis

• 216 sectors• 6 layers• Over-modulation

In V/f mode, the length of the reference space vector is decided by the speed command.

Space vector diagram of seven-level inverter


Phase-A voltage, phase-A current and common mode voltage waveforms for M.I.= 0.14 (Layer 1 operation)

VA2A4

IA

VOO’


Phase-A voltage, phase-A current and common mode voltage waveforms for M.I.= 0.28 (Layer 2 operation)

VA2A4

IA

VOO’


Phase-A voltage, phase-A current and common mode voltage waveforms for modulation index 0.57 (Layer 4 operation)

VA2A4

IA

VOO’



VA2A4

IA

VOO’



VA2A4

IA

VOO’


Phase-A voltage and phase-A current waveforms for modulation index 0.94 (over- modulation operation)

VA2A4

IA


Inverter operation under speed reversal:- Phase-A voltage and phase-A current

VA2A4

IA


A High-Resolution Multi-Level Voltage Space Phasor Generation for an Open-end Winding Induction Motor Drive


• A topology for high resolution voltage space phasor generation for an open-end winding induction motor drive is presented

Introduction

• The open-end winding induction motor is fed from both ends by two 3-level inverters with asymmetrical DC links

• This results in voltage space phasors equivalent to a conventional 9-level inverter

• The 3-level inverters used in the proposed drive, are realised by cascading two 2-level inverters


3/8Vdc

3/8Vdc

Inverter A

+

+

A2

S12S16

S15S13

S22S26S24

S23S21S25

INV 2

INV 1S11

S14-

C1

-

C2

C4

S32 S36

S35 S33

S42 S46 S44

S43S45

A4B4

INV 4

INV 3Inverter B

S41

S34

S31

-

+

1/8Vdc

-

+

1/8Vdc

C3 B3 A3 C3

C4

IM

O O’

B2C2

A1 B1 C1

The power Circuit

Inverter A and Inverter B are formed by cascading 2-level inverters

INV1,INV2 Inverter A ||| INV3,INV4 Inverter B

INV1,INV2 3/8Vdc INV1,INV2 1/8Vdc

•Inverter A and Inverter B are 3-level inverters


Inverter ALevels in A-leg

( VA2O )

Inverter BLevels in A-leg

( VA4O’ )

Levels in A-phaseof the machine ( VAA’= VA2O - VA4O’)

0003/83/83/86/86/86/8

2/81/802/81/802/81/80

-2/8 L1-1/8 L2 0 L31/8 L42/8 L53/8 L64/8 L75/8 L86/8 L9

The levels across the machine phase winding


217 Locations384 Sectors

Space vector representation

9-levels in space vectorAmplitudes along :0,1/8, Vdc,2/8 Vdc, 3/8 Vdc ,4/8 Vdc , 5/8 Vdc , 6/8 Vdc , 7/8 Vdc and Vdc

axisα

axisβ

axisα


•The reference wave set is placed at the middle of the carrier set• Three levels are involved, therefore three-level waveform

Conventional SPWM


•The reference wave set is placed at the middle of the lowermost carrier• Only two levels are involved, therefore two-level waveform• Only INV3 is switching ( the top 2-level inverter of Inverter-B) hence losses are only due to INV3

For Low modulation index


• A progressive discreet DC shift in steps of Vc/2 is given to the reference wave set as the speed increases

9-level operation for the maximum speed range

• The inverter then moves through 3-level,4-level,5-level, 6-level,7-level,8-level and 9-level operation


INV1 and INV2 DC-link : 150V ( 3/8 Vdc) INV3 and INV4 DC-link : 50V ( 1/8 Vdc)

Layer 1

Phase voltage – 2-level waveform

Pole voltage of Inverter-B

Only INV3 of Inverter-B is switching in 2-level mode( 100 V and 50V)

Experimental results :


Experimental results -Layer 2


Inverter-B in 3-level operationInverter-A not switching( 100V, 50V and 0V)




Inverter-B in 3-level operation

Inverter-A starts switching in2-level mode ( 100V and 0V)




Inverter-A in 2-leveloperation

Inverter-B in 3-level mode


Experimental results -Max speed range

Phase voltage –9-level waveform

Inverter-A also in 3-leveloperation ( 300V,150V,0V)

Inverter-B in 3-level mode ( 100V,50V,0V)

Inverter-A switching lessfrequently than Inverter-B


The Current waveforms

During 8-level operation During 9-level operation

The Harmonic Spectrum of

the Phase Voltage During 9-level operation


Common mode voltages and its effect on induction motor drive operation


Ao

S11

S12

S13

S14

S21

S24

S23

S22

S31

S32

S33

S34

B

C1

C2

Vdc

+

_

AO AN NO

BO BN NO

CO CN NO

v v v

v v v

v v v

NO AO BO CO

1v v v v

3

InductionMotor

N

a1 b1 c1

C

Common-mode Voltage Generation by a Multi-level VSI


Three-level inverter configuration with common mode voltage elimination


PWM inverters generate high frequency, high amplitude common mode voltages, which induces ‘shaft voltage’ on the rotor side

When the induced shaft voltage exceeds the breakdown voltage of the lubricant in the bearings, result in large bearing currents

Problems associated: erosion of the bearing material, premature mechanical failure of bearings leading to motor failure, increase in total leakage current through the ground conductor resulting into increased conducted EMI and false tripping of relays

PWM inverters which do not generate common mode voltage are suggested as a solution to the above problems

Common mode voltages and its effects




A dual two-level inverter scheme with common mode voltage elimination for an induction motor drive


S41

A1

B1

C1

S12S16S14

S13S11S15

INV 1

+

-

Vdc/2

S22 S26 S24

S23S25

INV 2

IM

S24

C2 B2

A2

+

-

Vdc/2

O O’

Schematic of dual inverter fed open end winding induction motor drive with isolated DC-links


A

BC

D

E F

O

A’

B’C’

D’

E’F’

O

INV1 INV2

Magnitude of spacePhasors : 2Vdc

1

23

4

5 6

1’

2’3’

4’

5’ 6’

The voltage space vectors of the individual inverters


18’

28’

22’,44’

85’86’

77’

38’

81’ 11’, 33’

56’

82’

87’,78’

43’ 67’

88’74’

73’

55’,66’

24’

14’74’

16’

17’

15’

25’

75’

26’

27’34’76’

35’36’

37’46’ 21’

45’

47’

31’

41’71’48’

58’

32’

72’51’

52’

57’

42’

61’ 68’

62’

83’

53’63’

12’ 64’

23’

54’13’

65’A -phase axis

A

BC

D

E F

G

H

IJK

L

M

N

P Q R

S

O

The voltage space vectors and space phasor combinations of the dual inverter


Voltage space vector combinations producing zero common mode voltage in the motor phase windings


S41

A1

B1

C1

S12S16S14

S13S11S15

INV 1

+

-

Vdc/2

S22 S26 S24

S23S25

INV 2

IM

S24

C2B2

A2

O

Schematic of dual inverter fed open end winding induction motor drive with single DC-links


S

24’

15’

26’35’

51’

42’

62’ 53’

64’

13’

A -phase axis

G

H

IJK

L

M

N

PQ

R

46’31’

O 1

23

4

5 6

11’

22’33’

44’

55’ 66’

77’ 88’

Voltage vectors without triplen contribution


S

15’

35’

51’

53’

13’

A -phase axis

G

H

IJK

L

M

N

PQ

R

31’

O 1

23

4

5 6

11’

33’ 55’

55’

11’

33’

2V3 dc

The space phasor combinations for active vectors and zero vectors used in the present work (for

sequence-1)


S

15’

35’

51’

53’

13’

A -phase axis

G

H

IJK

L

M

N

PQ

R

axis

31’

O1

23

4

5

6

11’

33’ 55’

55’

11’

33’

srV

2V3 dc

The reference space phasor Vsr for the dual inverter


Experimental results : lower speed range

Pole voltage and its FFT Phase voltage and its FFT


Experimental results : higher speed range

Pole voltage and its FFT Phase voltage and its FFT


Three-level inverter configuration with common mode voltage elimination for an induction motor drive


A three – level inverter scheme based on open-end winding configuration is proposed, which, uses only half the DC link voltage, compared to the scheme based on conventional NPC inverter

The proposed scheme generates the three-level voltage waveforms across the motor phases with

Zero common mode voltage in the motor phase voltage

Zero common mode voltage in the pole voltage



The five-level inverter configuration


B axis

C axis

A axis

-+- 0+- ++-

+0-

+--

00-++0

-0-0+0

0--+00

0-0+0+

--000+

-000++

-+0

-++

-0+

--+ 0-+ +-+

+-0

+++000---

Vdc /2

K J I

H

G

BC

A

FE

D

L

M

N

O P Q

R

0

axis

axisspace vector combinations for inverter-A , inverter-B


1

A-phase Axis

B-phase Axis

C-phase Axis

axis

axis

2

34

5

6 7

8

9

101112

13

14

15

17 18

19

20

21

22

23242526

27

28

29

30

31

32

16

33 34 35

36

37

38

39

40

41

4243444546

47

48

49

50

51

52

53

54 55 56 57 58

59

60

61

12

3

45

6

78

910

1112

13

1415

1617

1819

2021

22

2324

2526

2728

2930

3132

3334

35

3637

3839

4041

4243

4445

4647

4849

50

5152

5354

5556

5758

5960

6162

6364

6566

6768

69

7071

7273

7475

7677

7879

8181

8283

8485

8687

8889

90

9192

9394

9596

Vdc

Five-level Inverter voltage space vector representation

Shaded inverter voltage space phasor locations produce zero common mode voltage in the phase voltage of IM


B-phase Axis

C-phase Axis

axis

axis

Vdc

A- phase axis

0A’

B’

C’

D’

E’

F’

R’

H’J’

L’

N’ P’

G’

I’

K’

M’

O’

Q’

Inverter voltage space phasor locations with zero common mode voltage in the phase voltage of IM


Vcm

-+-

+--

--+

-00

00-

0-0

++-

-++

+-+

+00

0+0

00+

0+-

+0--+0

-0+

0-+

+-0

0000

12dcV

12dcV

Vcm1

Group E

Group C

Group D

Voltage space vectors of inverter-A (belonging to group C, D and E) in a three dimensional plane: α-β-0 plane


The resultant three-level space vector configuration when group D switching states are used to switch inverters-A and inverter-B


Inverter configuration with common mode voltage elimination



• A three-level inverter configuration with common mode elimination is proposed for an induction motor drive with open-end windings. • Common mode voltage generated across the motor phases is zero.• Suppresses the common mode currents which otherwise will flow in the machine windings. • Common mode voltage in the inverter pole voltage is zero. • The problems associated with the common mode voltages inducing currents in the leakage capacitances are completely eliminated (as the electrostatic coupling between stator winding to stator iron and between stator winding and rotor iron is ineffective)• Only two power supplies are required whereas the equivalent three-level inverter configuration with common mode elimination based on H-bridge topology requires six isolated power supplies.• DC link voltage requirement is only half to that of the conventional three-level inverter configuration with common mode elimination.

Salient Features


B-phase Axis

C-phase Axis

axis

axis

1

Vdc

A –phaseaxis

+0- , 000

000 , 0-+

-+0 , 000

000 , +0-

0-+ , 000

000, -+0

0+- , -0+

-0+, +-0

+-0 , 0+-

+0- , -0+

0+- , 0-+

-+0 , +-0

-0+ , +0-

+-0,-0+

0+-,+-0

-0+ , 0+-

+-0 , -+0

0-+ , 0+-

000, 000

Output vectors selected for inverter switching


Pole voltage waveforms for modulation index 0.4 (Layer 1 operation) and its FFT


Phase-A voltage and phase-A current waveform for modulation index 0.4 and FFT of phase voltage (Layer 1)


Pole voltage waveforms for modulation index 0.7 (Layer 2 operation) and its FFT


Phase-A voltage and phase-A current waveform for modulation index 0.7 and FFT of phase voltage (Layer 2)


Pole voltage waveforms for modulation index 0.95 (over-modulation operation) and its FFT


Phase-A voltage and phase-A current waveform for modulation index 0.95 and FFT of phase voltage


Pole voltage waveforms for twelve-step mode and its FFT


Phase-A voltage and phase-A current waveform for twelve-step mode and FFT of phase voltage


Five-level inverter configuration with common mode voltage elimination for an induction motor drive


Power Scheme of One Leg of Proposed Five-level Inverter by Cascading Conventional Two-level and Three-level VSIs

Level

PoleVolta

ge

State of the switch*

S11 S21 S24 S41

2 Vdc/4 1 1 0 1

1 Vdc/8 0 1 0 1

0 0 0 0 0 1

-1 -Vdc/8 0 0 1 1

-2 -Vdc/4 0 0 1 0

*[“1” ON, “0” OFF]S11-S14, S21-S34, S24-S31, and S41-S44 are

complementary pairs of switches

IGBT Gating Logic


Power Schematic for The Nine-level Inverter Configuration


Switching States and Voltage Space Vector Locations of Inverter-A (a Five-level Inverter)

96 Sectors61 Vectors125 Switching States


Groups of Common-mode Voltage Generated by Individual Five-level Inverter

Group Switching state of five-level inverter VCM

1 222 Vdc/4

2 122, 212, 221 5Vdc/24

3 022, 112, 121, 202, 211, 220 Vdc/6

4 012, 021, 102, 111, 120, 201, 210, 22-1, 2-12, -122 Vdc/8

5 002, 011, 020, 101, 110, 12-1, 1-12, 200, 21-1, 22-2, 2-11, 2-22, -112, -121, -222

Vdc/12

6 001, 010, 02-1, 0-12, 100, 11-1, 12-2, 1-11, 1-22, 20-1, 21-2, 2-10, 2-21, -102, -111, -120, -212, -221

Vdc/24

7 000, 01-1, 02-2, 0-11, 0-22, 10-1, 11-2, 1-10, 1-21, 20-2, 2-1-1, 2-20, -101, -110, -12-1, -1-12, -202, -211, -220

0

8 00-1, 01-2, 0-10, 0-21, 10-2, 1-1-1, 1-20, 2-1-2, 2-2-1, -100, -11-1, -12-2, -1-11, -1-22, -201, -210, -22-1, -2-12

-Vdc/24

9 00-2, 0-1-1, 0-20, 1-1-2, 1-2-1, 2-2-2, -10-1, -11-2, -1-10, -1-21, -200, -21-1, -22-2, -2-11, -2-22,

-Vdc/12

10 0-1-2, 0-2-1, 1-2-2, -10-2, -1-1-1, -1-20, -20-1, -21-2, -2-10, -2-21 -Vdc/8

11 0-2-2, -1-1-2, -1-2-1, -20-2, -2-1-1, -2-20 -Vdc/6

12 -1-2-2, -2-1-2, -2-2-1 -5Vdc/24

13 -2-2-2 -Vdc/4


Groups of Switching States and Amplitude of Resulting Common-mode Voltage in Five-level Inverter (Inverter-A and Inverter-A’)


Voltage Vector With Corresponding Switching State Resulting Zero Common-mode Voltage in Five-level Inverter (Inv.-A and Inv.-A’)



Combined Voltage Space Vector Locations of a Dual Five-level Inverter Fed Open-end Winding IM Drive (a Nine-level Inverter)

384 Sectors217 Vectors15,625 Switching States


Number of Redundant Switching States Available for Voltage Vectors of Five-level Inverter with Zero Common-mode

Voltage



Switching State Combination Selected to Generate The Voltage Space Phasors of Five-level Inverter With Zero CMV



Power Scheme of Proposed Five-level Inverter With CME


Two-leveloperation

m=0.2

Pole voltage spectrum Phase voltage spectrum


Three-leveloperationm=0.33



Four-leveloperation

m=0.6



Five-leveloperationm=0.72



Over modulation

m=0.97



Four-leveloperation

m=0.6

Five-level operation m= 0.72 Over modulation m = 0.97


Three-level inverter scheme with common modevoltage elimination and dc-link capacitor

voltage balancing for an open end winding induction motor drive


Power schematic of a three-level inverter with common-mode voltage elimination

The proposed scheme generates the three-level voltage waveforms across the motor phases with

Zero common mode voltage in the motor phase voltage Zero common mode voltage in the pole voltage

Each side on motor is fed with three-level inverters Requires half the DC link voltage, compared to the scheme based on conventional NPC inverter


• Multiplicity of inverter vector locations has been effectively utilized to arrive at a DC Link capacitor voltage-balancing scheme

• The proposed capacitor voltage-balancing scheme is implemented without compromising on the SVPWM scheme and a simple hysteresis controller can be used to balance the DC link capacitor voltages

• Requires only one isolated passive front-end power supply

Salient Features

Three-level inverter with common-mode voltage elimination


The switching combinations for three-level inverter with common mode voltage elimination

•Proposed scheme generates the three-level voltage waveforms across the motor phases with

•Zero common mode voltage in the motor phase voltage

•Zero common mode voltage in the pole voltage

•The DC Link voltage is half as compared to the three-level NPC inverter

Switching combination ‘+0-, -0+’ means inverter-A state is ‘+0-‘ inverter-B state is ‘-0+’


Inverter-induction motor system model

• Each leg of individual three-level inverter is modeled as a three pole switch

1 => - Vdc/22 => 03 => + Vdc/2

• Switching function ‘S’ = 1 if switch is connected to -Vdc/2

2 if switch is connected to – 0 3 if switch is connected to Vdc/2


Inverter-induction motor system model

• Source current – iS

• Currents drawn from DC link- i1, i2, i3

• Inverter-A currents -i1A,i2A,i3A, Inverter-A currents -i1B,i2B,i3B

• Induction motor currents- ia, ib, ic


The inverter pole voltages with respect to negative DC rail, in terms of capacitor voltages

Analysis of DC link capacitor voltage unbalance for proposed three-level inverter configuration


The currents drawn from the DC Link nodes (i1,i2,i3) in terms of motor currents (ia, ib, ic)


Inverter-A:

Inverter-B:

Motor currents

Motor currents



The current drawn from the middle point on the DC linkis responsible for unbalance


1

SV

SV

SV

SV

SV

SV

MV

MV

MV

LV

LV

LV

LV

MV

MV

ZV

MV

LV

LV• LV: Large Voltage Vectors • ZV: Zero Voltage Vectors• SV: Small Voltage vectors• MV: Medium Voltage vectors

Classification of the inverter voltage vectors

Classification is based on• Voltage produced in the output• Connection of IM phase winding

to the Capacitors


G’ (+0-, -0+)

C2

C1

A C

B

Large Voltage Vectors (LV) and their effect on DC link capacitor voltages

• Two windings directly across full DC link

• One winding short circuited at middle DC link point

• No effect on capacitor voltages as load current is drawn directly from source


C2

C1

+0- , 0-+

C

B

A

(b)

C2

C1

0+- , -0+

C

A

B

(a)

Middle Voltage Vectors (MV) and their effect on DC link capacitor voltages

• One winding directly across full DC link• One windings across each capacitor• The difference between these two

winding currents is drawn through the mid-point of DC link

• Has unbalancing effect on capacitor voltages

• Each MV vector location has two switching combinations• The IM phase windings are connected to opposite capacitors in these two

combinations• Ex: vector location H’

(a) 0+-,-0+ A phase bottom capacitor and B phase top capacitor (b) 0+-,-0+ A phase top capacitor and B phase bottom capacitor


C2

C1

(a) 000,-0+A

CB

C2

C1

(b) +0-, 000C

AB

C2

C1

(c) +-0 , 0-+

AC

B

C2

C1

(d) 0+- , -+0

AC

B

Space vector combinations and their effect on DC link capacitor voltages inverter vector location A’ (Small Voltage vector)

One winding across each capacitor

One winding across each capacitor

Two windings across TOP capacitor

Two windings across BOTTOM capacitor

NSV NSV

LSVUSV

Normal Small Voltage Vector

Normal Small Voltage Vector

Lower Small Voltage Vector

Upper Small Voltage Vector


+-0 , 0-+000 , -0++0- , 0000+- , -+0

-+0 , -0+0+- , 000000 , 0-++0- , +-0

0+- , +0-000 , +-0-+0 , 000-0+ , 0-+

0-+ , +-0-0+ , 000000 , +0--+0 , 0+-

-0+ , -+0000 , 0+-0-+ , 000+-0 , +0-

+0- , 0+-+-0 , 000000,-+00-+ , -0+

0+- , -0++0- , 0-+

-0+, +-0-+0 , +0-

+-0 , 0+-0-+ , -+0

+0- , -0+

0+- , 0-+

-+0 , +-0

-0+ , +0-

+-0,-0++0-,-+0

-+0 , 0-+0+-,+-0

-0+ , 0+-0-+ , +0-

+-0 , -+0

0-+ , 0+-

0

LV: Large Voltage Vectors ZV: Zero Voltage VectorsMV: Medium Voltage vectorsUSV: Upper Small Voltage vectorsNSV: Normal Small Voltage vectorsLSV: Lower Small Voltage vectors

Summary: Classification of switching combinations of proposed inverter voltage vector locations


• Thus inverter voltage vectors belonging to ZV, NSV, MV and LV can be used effectively to maintain the voltage balance across the DC Link capacitors

• No voltage/current feedback required• Works on alternate switching of NSV and MV switching combinations

DC link capacitor voltage balancing scheme for the proposed three-level inverter fed induction motor drive

• ZV and LV do not have any unbalancing effect on the DC link capacitor voltages

• MV and NSV group generate very low voltage unbalance. Each have two switching combinations with phase windings EXCHANGING their connections to DC link capacitors.

• Thus, effect of one switching combination on the capacitor voltages is nullified by another switching combination

• Alternate switching of NSV and MV switching combinations in consecutive sampling durations will maintain the capacitor voltages balanced.

000 , -0++0- , 000

0+- , 000000 , 0-+

000 , +-0-+0 , 000

-0+ , 000000 , +0-

000 , 0+-0-+ , 000

+-0 , 000000,-+0

0+- , -0++0- , 0-+

-0+, +-0-+0 , +0-

+-0 , 0+-0-+ , -+0

+0- , -0+

0+- , 0-+

-+0 , +-0

-0+ , +0-

+-0,-0++0-,-+0

-+0 , 0-+0+-,+-0

-0+ , 0+-0-+ , +0-

+-0 , -+0

0-+ , 0+-

0


POS_SEQNEG_SEQ

A’ G’ R’ A’ G’A’ R’ A’+0-, -+0000, -0+ +0-, 000000, -0+ +0-, 000+0-, -0++0-, -0+

TS

2*TS

+-0, -0+

(a) Sector formed by inverter vectors A’-G’-R’

0 A’ B’ 0 A’0 B’ 00+- , 000000, 000 000, 000000, -0+ 000,000000, 0-+000, 000 +0-, 000

(b) Sector formed by inverter vectors 0-A’-B’

(c) SEQ signal

high

low

TS TS

The sequence of various switching combinations during POS_SEQ and NEG_SEQ


POS_SEQ NEG_SEQ

A’ G’ R’ A’ G’A’ R’ A’+0-, -+0000, -0+ +0-, 000000, -0+ +0-, 000+0-, -0++0-, -0+

TS2*TS

+-0, -0+

Sector formed by inverter voltage vectors A’-G’-R’

high

low

TS TS

0’

A’

B’

H’

Y’

G’

C’

R’

K’

I’

J’

L’

M’

N’

O’

Q’

D’

E’

F’

P’

Q’

• Alternate switching combinations are selected for A’ (NSV) and R’(MV) inverter voltage vectors in the consecutive sampling interval

• The capacitor voltage unbalance in sampling interval POS_SEQ is nullified in next sampling interval NEG_SEQ


POS_SEQ NEG_SEQTS

2*TS

high

low

0’

A’

B’

H’

Y’G’

C’

R’

K’

I’

J’

L’

M’

N’

O’

Q’

D’

E’

F’

P’

Q’

0 A’ B’ 0 A’0 B’ 00+- , 000000, 000 000, 000000, -0+ 000,000000, 0-+000, 000 +0-, 000

Sector formed by inverter voltage vectors 0-A’-B’

TS TS

• Alternate switching combinations are selected for A’ (NSV) and B’(NSV) inverter voltage vectors in the consecutive sampling interval

• The capacitor voltage unbalance in sampling interval POS_SEQ is nullified in next sampling interval NEG_SEQ


SVPWMmodulator

SEQ

Switching Combination

SelectorGate signal

decoding

Gate signalsState

DSP PAL

Open loop DC Link capacitor voltage balancing scheme


Open loop DC Link capacitor voltage balancing controller (Simulation results)

DC Link Voltage

Capacitor voltages


Deviation in the capacitor voltages when the open loop DC Link balancing controller is turned off (Simulation results).

DC Link Voltage

Capacitor voltages


Harmonic frequency distribution of phase voltages for balanced and unbalanced capacitor voltage conditions

Low order even harmonics causes damaging effects to the machine because of the current harmonics resulting in torque pulsations and increased machine losses


sec

Disadvantage: Gradual drift in the capacitor voltages in the open loop schemePossible Reasons:

• Use of the asynchronous PWM,• Unequal time durations of the MV and NSV inverter vectors in

consecutive switching intervals• Unbalanced load currents etc

Open loop DC Link capacitor voltage balancing scheme


HysteresisController0 /O P

vC2

vC1

cV

1

0 HPLPLNHN

1

/O P

Control Band

vC

Hysteresis controller based closed loop DC Link balancing scheme

• Switching combinations from USV charge lower capacitor and discharge upper capacitor

• Switching combinations from LSV discharge lower capacitor and charge upper capacitor

• USV and LSV group switching combinations are used to balance the capacitor voltages

• Hysteresis controller selects the LSV or USV group instead of NSV depending upon the difference in the capacitor voltages, vC

• Closed loop scheme involves sensing the capacitor voltages


Inverter Switching

VectorLocation

Switching Combination

Selector

Inverter gate signals

decoding

HysteresisController

SEQ

State/O P

vC2

vC1

0

DSP

PWMAlgorithm

InverterA

InverterB

Inductionmotor

InverterA Inverter

B

PAL

Hysteresis controller based closed loop DC Link balancing scheme


Operation of closed loop controller for DC link balancing (Simulation results)

Capacitor voltages

vC

Controller output ‘state’


The deviation in the capacitor voltages when the DC Link voltage-balancing scheme is turned off for a small interval


DC Link voltage-balancing scheme in 12-step mode

• SV are not switched for longer duration in the 12-step mode• Capacitor voltages deviate from the balanced state


DC Link voltage-balancing scheme in 12-step mode

Slight reduction in the modulation index restores the capacitor voltages to balanced state in 12-step mode


Experimental Results


Balancing of DC link capacitor voltages VC1 and VC2 during steady state operation

VC1, VC2


Balancing of the DC Link capacitor voltages after the controller is disabled for small interval, inner layer operation

VC1

VC2


Balancing of the DC Link capacitor voltages after the controller is disabled for small interval, outer layer operation

VC1

VC2


The DC link voltages and machine phase current under while machine operating in inner layer is accelerated to outer-layer and then to over-modulation

VC1,VC2

Phase current


The DC link voltages and machine phase current under while machine operating in inner layer is subjected to speed reversal

VC1,VC2

Phase current


Space vector PWM signal generation for multi-level inverters using only the sampled amplitudes of

reference phase voltages


Conventional Space Vector Based PWM

1. Identify the sector2. Determine the timings 3. Determine the Actual vectors4. Generate the Gate signals

Sector Identification a. With Angle and magnitude information b. Using level comparators

Timing a. Direct equations b. Mapping the sector to an appropriate inner sector

Space vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages


In the Proposed Work

1. Sector identification is not required2. No need to compute switching times for each vector3. Does not use look-up tables to select vectors4. The inverter leg switching times are directly obtained with a simple algorithm using only the sampled amplitudes of the reference phase voltages

• Faster computations • Generate the inverter gate signals for the entire

modulation range extending up to six step mode

Space vector PWM signal generation for multi-level inverters using only the sampled amplitudes of reference phase voltages


Two level SVPWM


1 max min / 2offsetV V V

max , ,is maximum of A B CV V V V

min , ,is minimum of A B CV V V V

• Addition of Voffset1 centers the active inverter vectors in the switching interval for two-level inverters but not for multilevel inverters• The max phase may not determine the third cross, min phase may not determine the first cross• Correct determination of the phases which determines the first -cross,second-cross and third-cross is required for multilevel inverters

Offset voltage determination for Two level SVPWM


Reference voltages and triangular carriers for a five-level SPWM

Documents

CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 1 Power Converters and Drives Lab -a Research Overview Prof. K. Gopakumar Centre for Electronics Design