Ce g 3150 Lab 4 Traffic Light

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CEG 3150: Digital Systems II

(Fall 2004)

Prof. Rami Abielmona

Laboratory #3: Sequential Machine Design I

Traffic Light Controller

October 17, 2004

Contents

1 Objective 2

2 Pre-Lab 2

3 Introduction to Synchronous Sequential Machine Design 23.1 Problem Specification . . . . . . . . . . . . . . . . . . . . . . . . 33.2 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.3 State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.4 State Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . 43.5 State Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.6 Transition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.7 Design Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.8 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . 12

3.8.1 Moore vs. Mealy . . . . . . . . . . . . . . . . . . . . . . . 123.8.2 Moore VHDL Model . . . . . . . . . . . . . . . . . . . . . 133.8.3 Mealy VHDL Model . . . . . . . . . . . . . . . . . . . . . 153.8.4 Final Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Laboratory 174.1 Problem Specifications . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 Laboratory Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.2.1 Component Breakdown . . . . . . . . . . . . . . . . . . . 184.2.2 System-Wide Hints . . . . . . . . . . . . . . . . . . . . . . 19

4.3 Bonus: Visualize Counter on BCDs . . . . . . . . . . . . . . . . . 20

5 Design Restrictions 21

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6 Report Reminders 22

7 Acknowledgements 22

1 Objective

The objective of this laboratory is to design and build a synchronous sequentialmachine in VHDL.

Upon completion, the student must be able to:

Design, realize and test a finite state machine;

Design, realize and test a traffic light controller;

Demonstrate a complete understanding for synchronous sequential ma-chine design.

2 Pre-Lab

Go through the first six steps of the FSM method presented in section 3 for thetraffic light controller discussed in this laboratory. Starting with the problemspecifications given in section 4.1, create a state diagram, convert it to a statetable, reduce the latter, choose a state assignment and synthesize a transitiontable for the traffic light controller you are going to implement in this laboratory.Present and explain your work to the TA at the beginning of the session.

3 Introduction to Synchronous Sequential Ma-chine Design

Designing sequential machines can be very daunting, with all the functionaland timing requirements that are imposed on the circuit, as well as the race,hazard and synchronization conditions that could occur, and should be designedagainst. That said, taking a set of requirements and translating them to adigital synchronous sequential circuit should follow a systematic and definedprocedure. We have already seen such a procedure in laboratory #1, namelythe algorithmic state machine (ASM) methodology, and in this laboratory, wewill be introduced to another systematic procedure for the design of synchronoussequential machines, known from here on simply as sequential machines: the

finite state machine (FSM).It is worth noting at this point that this procedure is suitable for describ-

ing machines that have a relatively small number of inputs and outputs. Forcomplex machines, the ASM methodology is a more scalable form of representa-tion. Keep this in mind while going through this experiment. The FSM designprocedure can be summarized as follows:

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Problem specification Obtain the specification of the desired circuit;

State diagram Create a state diagram which shows all the states that themachine can be in, and how it transitions from one state to another;

State table Extract a state table from the state diagram. More advanceddesigners can create this table without the diagram;

State minimization Reduce the number of states in the table by eliminatingredundant ones;

State assignment Choose a suitable assignment for the states in your table;

Transition table Convert the state table into a transition table by incorpo-rating the state minimization and assignment step results;

Design equations Choose the type of flip-flops to be used in the circuit, anddevelop the design equations for the next-state variables and outputs ofthe circuit; and

Circuit implementation Implement the circuit as indicated by the logic ex-pressions in the previous step.

This laboratory will attempt to

3.1 Problem Specification

Every circuit designer receives problem specifications and attempts to conceivea solution that meets those specifications by demonstrating the correct function-ality and timing of the circuit. Let us view an example of such a specification.

Conceive a synchronous sequential machine required to recognize

the 4-bit sequence "1101" by producing an output 1 whenever the

sequence occurs in a continuous serial input, and a 0 otherwise.

For example, if the input sequence is "0101101011010", the output

sequence is "0000001000010". Note that all changes in the circuit

occur on the positive edge of a clock signal, and there is one

input and one output to the circuit.

3.2 State Diagram

The second step of the FSM procedure is to create a state diagram based on theproblem specification, which shows the states and transitions of the machine.

Following through with our specification presented in the previous section, thestate diagram shown in figure 1 can be synthesized.

The state transitions are indicated by arrows out of a state and into an-other, while the input and output specifications are indicated by labels on eachtransition. For example, the transition leaving state A and entering state B hasa 1/0 label, which indicates that when an input of 1 is received while in

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Figure 1: Sequence detector state diagram

state A, transition to state B and output a 0. Note that this state diagraminitializes into state A and outputs a 1 only during the transition from stateD to state B, indicating that a 1101 sequence has been detected at the serial

input stream. Also, note that as soon as one sequence is detected, we transitionto state B, rather than the initial state A, in case another 1101 sequence isupon us (we already caught the first bit at state D).

3.3 State Table

Having conceived a state diagram that resolves our original specification, it isnow time to convert it to a state table. The state table extracted from thesequence detector state diagram is shown in table 1. This table can be devisedfrom the problem specifications directly, however a state diagram eases the flowand aids in debugging the solution.

Present Next state Output

state x = 0 x = 1 x = 0 x = 1A A B 0 0B A C 0 0C D C 0 0D A B 0 1

Table 1: Sequence detector state table

Now that we have seen an example of state table extraction, let us examinea more complicated state diagram, that we will be referring to throughout thetheoretical discussion of this laboratory. The particular state diagram is shownin figure 2, and its extracted state table in table 2.

3.4 State Minimization

The complexity of a sequential machine depends on the number of states in thecircuit. That said, it is advantageous to us to attempt and minimize (or at

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Figure 2: Example state diagram

least reduce) the number of allocated states, by eliminating two or more statesthat play identical roles (i.e. are equivalent to each other in all respects). Thisprocess is called state minimization, or state reduction. The resulting minimizedtable or diagram should have the same behavior as the original table or diagramwith a smaller total number of states.

Let us begin with two definitions that will aid us in the discussion of stateminimization (extracted from chapter 8 of our textbook).

Definition 3.4.1 Two states Si and Sj are said to be equivalent if and onlyif for every possible input sequence, the same output sequence will beproduced regardless of whether Si or Sj is the initial state.

Definition 3.4.2 Two states Si and Sj are said to be k-equivalent if and onlyif for every possible input sequence of length k, the same output sequencewill be produced regardless of whether Si or Sj is the initial state.

Definition 3.4.3 A partition P(k) of a set of states in a FSM is a partitioningof the set of states such that the states in a single partition are all k-equivalent.

Now, we can define the equivalence-class partitioning method (ex-tracted from Sunggu Lee, see acknowledgements), which is one of the methodsthat is used in the step of state minimization:

1. Form 1, where all states in a single partition are 1-equivalent;

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Present Next state Output state x = 0 x = 1 x = 0 x = 1

A B A 0 0B D D 1 0C A C 0 0D B F 1 0E B E 0 0F D E 1 0

Table 2: Example state table

2. Form 2 from 1, where states Si and Sj are grouped together ifSi andSj have 1-equivalent next states and and are 1-equivalent;

3. Form k+1 from k, where states Si and Sj are grouped together if Siand Sj have k-equivalent next states and and are k-equivalent;

4. Repeat step 3 until no change occurs from k to k+1; and

5. Relabel each group of the final partition and produce a reduced state tableusing states identified by the new labels.

In order to illustrate the method, let us apply it to our running example.Last time we left it, we had derived the state table in table 2; now let us try andreduce that table by applying the aforementioned minimization method. Theoutput produced for each of the states A, C and E is 0 for both x = 0 andx = 1. The output produced for each of the states B, D and F is 1 when x = 0

and 0 when x = 1. Hence, our first partition 1 is

1 = (ACE)(BDF) (1)

For our next partition, 2, let us consider the first block of states (ACE).When x = 0, the next states are (BAB) which are not present in the sameblock of 1, and when x = 1, the next states are (ACE), which are present inthe same block of 1. Henceforth, since states A and E are 1-equivalent witheach other but not with state C, we form two separate blocks: (C)(AE). Asfor our second block of states (BDF): when x = 0, the next states are (DBD),which are present in the same block of 1, and when x = 1, the next states are(DFE), which are not present in the same block of 1. Henceforth, since statesB and D are 1-equivalent with each other but not with state F, we form two

separate blocks: (F)(BD). Thus, our second partition becomes:

2 = (C)(AE)(F)(BD) (2)

For our next partition, 3, the next states for both x = 0 and x = 1 forthe first block of states (AE) are present in the same block of 2, hence the

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block is not separated. For our second block of states (BD), the next statesfor x = 0 are (DB) which are present in the same block of 2, however, for

x = 1, the next states are (DF), which are not present in the same block of2. Henceforth, states B and D are not 1-equivalent and have to be separated:(B)(D). Thus, our third partition becomes:

3 = (C)(AE)(F)(B)(D) (3)

Applying step 3 again to form our next partition, we obtain:

4 = (C)(AE)(F)(B)(D) (4)

Since 3 and 4 are identical, we move to step 5 of the equivalence-classpartitioning method of relabelling our states within our table: in our case, 3is considered to be the equivalence partition and states A and E are consideredto be equivalent. The reduced (or minimized) state table is shown in table 3,where state E has been eliminated and replaced by state A!

Present Next state Output state x = 0 x = 1 x = 0 x = 1

A B A 0 0B D D 1 0C A C 0 0D B F 1 0F D A 1 0

Table 3: Example reduced state table

The state diagram can, but is not required to, be updated according to thenewly reduced state table. The reduced state diagram is shown in figure 3.

Section 8.6.1 of your textbook take you through other examples of this min-imization procedure, and the student is referred to that section for more detailon this topic, including the minimization of incompletely specified FSMs. Inconcluding this sub-section, it is important to take note of the following issues:

Reduction does not necessarily imply minimization: throughout this dis-cussion, we have implied this equivalence, however, state reduction is abetter description of these techniques, as there is no deterministic way ofguaranteeing optimal minimization of state tables;

CAD tools utilize proprietary heuristic techniques to achieve state re-

duction that borders on optimal state minimization. The CAD vendorsusually guard these techniques very cautiously as state minimization andlogic minimization methodologies are two main factors that separate onetool from the next;

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Figure 3: Example reduced state diagram

There are other reduction techniques, such as reduction by implication,that will not be covered here due to a shortage of time and space, howeverthe student is advised to research them on their own time.

3.5 State Assignment

Looking at our reduced state table, we notice that we have 5 states. Whenimplemented in a logic circuit, each state is represented by a combination ofstate variables, the latter being the output of a flip-flop. In order to realize thestate table in a logic circuit, it is necessary to encode the states in binary form,a step known as state assignment. There are numerous state encodings, withthe most popular ones being:

Sequential

Gray

One-hot

Random

Auto (area minimization)

Each has its associated advantages and disadvantages, with no deterministicmethod to picking which encoding is best for which circuit. Worse yet, each en-coding has different state assignment combinations with table 4 showing that fora sequential state encoding, there are 140 unique state assignment combinationsfor a 5-state circuit and over 75 million for a 9-state circuit!

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# states # state variables # state assignment combinations

2 1 13 2 34 2 35 3 1408 3 8409 4 10,810,800

10 4 75,675,600

Table 4: Number of state assignment combinations

All is not lost, as modern CAD tools utilize heuristic techniques to establishthe best state encoding and state assignment for a particular circuit. Again,

these proprietary techniques are seldom publicized. Never the matter, since weare not designing circuits with the intent of optimally minimizing their areaconsumption whilst optimally maximizing their operating frequency, it is inter-esting to attempt to encode the circuits using at least one of the aforementionedmethods. Since our running example has 5 states to it, table 5 demonstrates aparticular state assignment for each aforementioned state encoding (note thatthe area optimized one is the CAD tool-specific encoding).

Sequential Gray One-hot Random

A=000; A=000; A=00001; A=011;B=001; B=001; B=00010; B=111;C=010; C=011; C=00100; C=001;D=011; D=010; D=01000; D=000;F=100; F=110; F=10000; F=101;

Table 5: Example state assignment

Sequential and random encodings are self-explanatory, while Gray encodingimplies that just one bit in the state vector changes value when the state machinechanges state. Finally, one-hot encoding has as many flip-flops as states, withonly one flip-flop set at any one clock cycle. It may seem that the one-hotencoding is wasteful of sequential resources, but with the new era of FPGAswith high flip-flop counts, it sometimes is more effective to utilize this encodingwhen synthesizing to an FPGA. Also, it is quite interesting to note that it hasbeen proven that a random encoding may produce, in certain situations, resultsas good as, if not better, any other encoding scheme! In this example, we willpick the Gray state encoding, but the student is advised to retry the exampleusing the sequential as well as the one-hot encoding techniques. Thus, ourfinal state assignment becomes: A=000, B=001, C=011, D=010 andF=110.

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3.6 Transition Table

Having chosen a state encoding and state assignment, it is now time to convertour reduced state table into a state transition table, or just transition table.This is the easiest step of the entire procedure, with our running examplestransition table shown in table 6. Note that we have denoted our state variablesas y2, y1 and y0, while our next-state variables are denoted as Y2, Y1 and Y0(more on this later).

Present Next state Output state x = 0 x = 1y2y1y0 Y2Y1Y0 Y2Y1Y0 x = 0 x = 1

A 000 001 000 0 0B 001 010 010 1 0C 011 000 011 0 0

D 010 001 110 1 0F 110 010 000 1 0

Table 6: Example transition table

3.7 Design Equations

Having obtained a transition table for our circuit, the next step is to choosethe type of flip-flops to be used as our sequential components, and develop thedesign equations for the next-state variables (called excitation equations) andfor our system outputs. There are three main types of flip-flops to choose from:

D, J-K and T. The simplest and most common flip-flop in todays FPGAs isthe D-type flip-flop. Let us develop the excitation equations for our D flip-flops.Referring to table 7, we can see the inputs that must be given to each flip-flopto cause a specific state transition, and for that reason this table is called anexcitation table.

Present State Next State D Flip-Flop J-K Flip-Flop T Flip-FlopQt Qt+1 D J K T

0 0 0 0 d 00 1 1 1 d 11 0 0 d 1 11 1 1 d 0 0

Table 7: Excitation table for flip-flops

We can hence, using 4-variable Karnaugh-maps (see figure 4), derive ourexcitation and output equations as follows (note that for all other state assign-ments, the next state variables and outputs are taken as dont cares):

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Y2 = y2 y1 y0 x (5)

Y1 = (y2 x) + (y0 x) + (y1 y0) + (y2 y1 x) (6)

Y0 = (y2 y0 x) + (y1 y0 x) (7)

z = (y1 y0 x) + (y1 y0 x) (8)

Figure 4: Karnaugh-maps for Y2, Y1, Y0 and z

To conclude this sub-section, let us compare the excitation tables of D vs.J-K vs. T flip-flops, as shown in table 8. A similar approach can be taken to ex-tract the excitation and output equations for a J-K or T flip-flop implementation(this is left as an exercise for the student).

Present Next state Output state x = 0 x = 1y2y1y0 Y2Y1Y0 J2K2 J1K1 J0K0 T2T1T0 Y2Y1Y0 J2K2 J1K1 J0K0 T2T1T0 x = 0 x = 1

A 000 001 0d 0d 1d 001 000 0d 0d 0d 000 0 0

B 001 010 0d 1d d1 011 010 0d 1d d1 011 1 0

C 011 000 0d d1 d1 011 011 0d d0 d1 000 0 0

D 010 001 0d d1 1d 011 110 1d 0d 1d 100 1 0

F 110 010 d1 d0 0d 100 000 d1 d0 0d 110 1 0

Table 8: Example excitation table

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3.8 Circuit Implementation

The final step of the FSM design procedure involves the realization of the cir-cuit as indicated by the logic expressions derived in the previous step. Beforewe present our running examples final circuit, it is important to discuss thedifferent generic structures of a synchronous sequential circuit. Presented infigure 5 is a synchronous sequential circuit with system inputs and system out-puts and sequential components to keep the system states. As we can now see,the next-state variables become the present-state variables at each edge of thesystem clock. The system outputs however, are generated by a combination ofsystem inputs and the present-state variables, or by the present-state variablesonly. We will see the difference in the next two (sub-)sub-sections.

Figure 5: Generic synchronous sequential circuit

3.8.1 Moore vs. Mealy

If the system outputs of a sequential circuit depend on only the state of thecircuit, then it is considered to be of the Moore type, whereas if the systemoutputs of a sequential circuit depend on both the state and the system inputs

of the circuit, then it is considered to be of the Mealy type. These types arenamed after their primary investigators, Edward Moore and George Mealy, whodiscovered their differences in the 1950s. A Moore-type FSM, normally called aMoore machine, is customarily more common than a Mealy machine, howeverthe latter does provide the designers with additional flexibility, as the systemoutputs can change with the system inputs, a feature lost on Moore machines.

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That said, the author tends to remember one over the other through the idiomless is more, which implies that with a Moore machine, less variables affect the

outputs (i.e. only the state variables). Figure 6 represents the main differencebetween the two types of FSMs.

Figure 6: Moore vs. Mealy machines

3.8.2 Moore VHDL Model

In a Moore machine, there are three separate actions that have to be constantlymonitored: (i) updating the next-state variables, (ii) updating the system out-puts, and (iii) maintaining the present state. The first two actions are notdriven by the clock and hence are combinational circuits, whilst the last actionis driven by the clock and hence is a sequential circuit. All three can be modeledby VHDL processes as follows:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY FSM IS PORT (i_clk, i_resetb : IN STD_LOGIC);i_x : IN STD_LOGIC;

o_z : OUT STD_LOGIC));

END FSM;

ARCHITECTURE Moore OF FSM IS

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TYPE state_type is (A, B, C, D);

SIGNAL presentState, nextState : state_type;

BEGIN-- Comb. process to update the next-state variables

PROCESS (presentState, i_x)

BEGIN

CASE presentState is

WHEN A => IF i_x = 0 THEN

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when C => o_z o_z IF i_x = 0 THEN

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3.8.4 Final Circuit

Assuming we are using D flip-flops, our running examples final circuit is shownin figure 7. The reader can notice that since our example turned out to be aMealy machine, the output z is driven by both the system states y2, y1 and y0,as well as the system input x.

Figure 7: D flip-flop realization of our example

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4 Laboratory

In this lab, you will, utilizing the eight steps of the FSM method, proceed toimplement a traffic light controller by first identifying its state diagram andcorresponding reduced state and transition tables (in the pre-lab), then realizingthe circuit of the controller and interfacing it to real-world sensors and lights.Starting from given problem specifications, your goal is to design, realize andtest the synchronous sequential circuit, using the Quartus II software and theUP-2 board from Altera (for more details, see section 5).

4.1 Problem Specifications

Your team has been hired to design a traffic light controller. A traffic lightcontrols the traffic at an intersection between a main street MS and a sidestreet SS. The main street has higher priority than the side one, and thus stays

green until at least one car on the side street arrives at the intersection. Acar sensor SSCS is present on the side street for such a purpose. The sensoroutputs a 1 at the presence of a car on the side street and a 0 otherwise.Normal operation of the traffic light consists of the main streets traffic light(MSTL) being green and the side streets (SSTL) being red. The MSTL staysgreen for a in-system-programmable (ISP) period of time MSC, after which ifthere is a car on the SS, the MSTL turns yellow for a set period MT, thenturns to red. The SSTL then turns green for a ISP period of time SSC, afterwhich it automatically turns yellow (even if there are cars at the intersection)for a set period SST, then red. The MSTL goes back to green at that point. Ifafter MST, there are no cars on the SS, then the MSTL stays green until a cararrives, at which time, the MSTL immediately cycles through its yellow thenred changes. The input/output specifications of the traffic light controller is areshown in table 9.

Figure 8: Traffic light controller

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Port Type Name Description Input GClock Global clock needed to synchronize the circuitry

Input GReset Global reset needed to bring the internals to known statesInput MSC[3..0] Main street counter 4-bit inputInput SSC[3..0] Side street counter 4-bit inputInput SSCS Side streets car sensor input

Output MSTL[2..0] Main streets traffic light output using one-hot encodingOutput SSTL[2..0] Side streets traffic light output using one-hot encodingOutput BCD1[3..0] BCD 4-bit output for left digit of current counter valueOutput BCD2[3..0] BCD 4-bit output for right digit of current counter value

Table 9: Input/Output Specification

4.2 Laboratory Hints

The following section is meant to introduce a possible solution to the problem,while discussing the major parts of that solution.

Shown in figure 9 is a potential system solution to the traffic light controllerproblem. Included in this figure are the major inputs and outputs of the system,as well as the essential building blocks. The shaded region indicates the bonusmark block, which is not a requirement of the laboratory.

4.2.1 Component Breakdown

We can break down the system diagram into five major components:

FSM Controller This component is the kernel of the system, and drives

all the system outputs, after making decisions depending on the systeminputs;

Main/Side Street Counters These components act as the timersof the MSTLand SSTL, respectively;

Comparator This component signals back to the FSM controller that a countermaximum has been reached;

Clock Divider This component is used to slow down the system clock, andeffectively reduce the overall power of the design;

Debouncer This component is used to handle mechanical switch debouncing,and transmit clean car sensory readings to the FSM controller;

Timer This component is used to time yellow and red lights for both the mainand side street traffic lights; and

BCD Decoder This component is used to visually demonstrate the currentcounter status onto a dual-digit BCD 7-segment display.

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Figure 9: A potential system diagram

4.2.2 System-Wide Hints

It is worthy to note that a global reset is provided to the FSM controller,which effectively resets all the state registers within the FSM, as well as anyoutputs of the FSM (going out of the system or to other building blocks withinthe system). This will cause the other blocks to enter their reset condition,and thus for example, cause the timer circuit to reset back to its initial countvalue. This reset distribution is not shown in figure 9, but it is assumed that

the designers will take care of this network.Speaking of global reset, it is up to the designer to input this asynchronous

signal to the FPGA. An idea would be to use the second push-button switchavailable on the board, but the issue of mechanical switch debouncing has tobe considered in that case. Other more elaborate ideas would involve using an

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interrupt scheme, with the global reset being input to the system, external tothe UP-2 development board, or using a scheme to detect longer periods where

the first push-button (used as the car sensor signal) is pressed down, and henceindicating a global reset. Actually, the global reset signal has to be asserted fora longer period of time than the car sensor signal in order for the system to reset.Thus, the settling time of the reset signal must be greater than that of the carsensor signal. Note that since the car sensor signal is asynchronous tothe FSM controller, synchronizing it would help avoid timing issues.

It is also necessary to remember that the on-board LEDs are activatedthrough negative logic, as mentioned in the board specifications:

The UP Education Boards contain 16 LEDs that are pulled-up with a

330-. resistor. An LED is illuminated when a logic 0 is applied to

the female header associated with the LED.

The timer outputs Main Street Timer (MST) and Side Street Timer (SST)are used to time yellow lights for the main street and the side street. Thesecan be set by the designer, and will not be in-system programmable. They arehard-wired to a set count value, which does not have to be the same for boththe main and side streets. Thus, the side street traffic light can stay at yellowfor longer or shorter than that of the main street, although it makes sense tomake it shorter, as there is a higher chance of having more cars crossing themain street at any time, compared to the side street.

Now, the counters that are in-system-programmable are the main andside street counters. These are to be used alongside the DIP switches atMAX SW1 (or FLEX SW1) and MAX SW2 (or FLEX SW2) in order to beable to change the maximum value to wait for a traffic light switch, on eitherthe main street or the side street. Please refer to figure 9 for a potential solutionto that specification.

Presented in this sub-section are the system-wide hints that will aid thedesigners in the realization of the basic building blocks. There are however, twoblocks, that require a bit more attention: the debouncer and the clock dividerblocks. The reader is referred to the accompanying Debouncing a Switch andDividing a Clock document if interested in the theory behind these functions,as well as their alternative realizations.

4.3 Bonus: Visualize Counter on BCDs

For an extra 5 marks, include a BCD decoder block to realize the displayof the current counter values onto the 7-segment BCDs in decimal format. Thedisplayed values must not exceed the programmable MSC maximum value, setthrough the 4-bit DIP switch (SW2). As for the SSC maximum value, as soonas the counter reaches that value, a switch must occur in the traffic lights,and thus the displays can be updated accordingly. Thus, it is required thatthe displays, when reaching the MSC maximum, must remain at that value,until a car arrives at the side street, indicating that a traffic light switch is

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required. Make the necessary changes to your module and present and discussthose modifications. You have to demonstrate your new design to your TA.

5 Design Restrictions

Verilog implementations will not be accepted. Perform all implementa-tions in VHDL code only

Behavioral level of modeling will not be accepted. Design should be doneat the structural level of modeling

Register Transfer Logic (RTL) design and coding is mandatory

Use graphical design for the top-level entity, and use your judgement forany other sub-blocks. However, all atomic modules have to be imple-

mented in VHDL (i.e. D flip-flop, 1-bit adder, 1-bit comparator and soon)

No core instantiations are allowed (i.e. LPMs from Altera or free IP coresfrom the Internet). All building blocks have to be designed and realizedby the group

The group may use any of the course-provided cores in their design (i.e.debouncer, clock divider, register, shift register, adder, counter, compara-tor and so on). Remember to reference all cores that the group has notthemselves developed

If using the clock divider core in particular, its behavioral level of modelingis accepted

The group may use a Mealy or Moore machine as their FSM controller

The top level entity is given in input/output specification format, but theinternals are left up to the group

The design has to be synchronous and globally reset-able. This meansthat global clock and reset signals are required in all functional blocks

Simulate all designs and check your simulation results with your theoret-ical ones (e.g. go through different intersection scenarios)

Download the design to the FLEX chip on your UP-2 boards, and use theon-board DIP switches to input MSC[3..0] and SSC[3..0], the on-board

push-button switch to input SSCS (the car sensor), and two sets of threeLEDs for the traffic lights, as shown in figure 8. If implementing the bonussection, the two 7-segment BCD decoders are to be used to demonstratecorrect counter functionality (BCD1[3..0] and BCD2[3..0])

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The group may use the MAX FPGA, but must be careful to note that itis smaller in logic capacity than the FLEX FPGA, however it is a non-

volatile device, hence the design will remain in the FPGA even thoughthe power is recycled

Each group must demonstrate a working version of the laboratory to theTA, before the due date of the report

6 Report Reminders

Include timing simulations with explanation for all VHDL source files

Describe and comment all your VHDL source files

Include a flowchart representation of your solution to the problem

Include a block diagram of your solution to the problem

If using ASM design, include all appropriate charts and paths (control anddata)

If using FSM design, include all appropriate diagrams, tables and circuitrealizations

Describe, in your own words, your solution to the problem

Describe your design obstacles and how they were overcome

Append all VHDL source code and graphical design files to your report

Submit a soft copy of all VHDL and graphical design files with your report

7 Acknowledgements

Figure 5 is extracted from our course textbook: Fundamentals of Digital Logicwith VHDL Design by Stephen Brown and Zvonko Vranesic. The equivalence-class partitioning method is extracted from Design of Computers and OtherComplex Digital Devices by Sunggu Lee.

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Documents

Ce g 3150 Lab 4 Traffic Light